JPS6229806B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to peripheral chips for microcomputer systems.

Recently, memory, clock pulse generator,
A so-called one-chip microcomputer has been developed in which a reset circuit, an I/O (input/output) port, etc. are housed on one chip.

In this one-chip microcomputer, the reset circuit is usually connected to an input pin, a resistor R and a capacitor C are connected to the input side of the input pin, a power supply E is connected to the other end of the resistor, and a power supply E is connected to the other end of the capacitor. is connected to the ground terminal. Therefore, the signal input to the reset circuit has a waveform that lags the power supply voltage by one order. The reset circuit is
The circuit is configured to obtain a reset signal within the chip by waveform shaping the input signal described above, and to provide this as an input to each circuit within the chip.

That is, by applying the power supply voltage, the inside of the chip is reset, ie, initialized, and the microcomputer becomes operable by the reset signal. This type of microcomputer chip poses no problem when used alone, but when peripheral chips are installed to configure an expanded system, it is necessary to reset the peripheral chips and the microcomputer chip, each of which has its own reset circuit. It is necessary to coordinate signals.

For this reason, as shown in FIG. 2, in an expanded system, the peripheral chip 101 may not have a reset circuit, but may receive a reset signal from the reset circuit 2 of the mask computer chip 100 through the signal line 300. However, for this purpose, the microcomputer chip 100 also requires an output signal pin for that purpose, and a signal line 300 is also required. Note that 200 is a bus for transmitting data and addresses between chips.

On the other hand, as shown in FIG. 3, a configuration may be adopted in which a reset circuit 2 is provided externally and its output is led to the microcomputer chip 100 and peripheral chips 101 as a system reset signal via a signal line 300. However, providing an external reset circuit in this manner has disadvantages in terms of cost compared to providing it within the chip.

On the other hand, if a system is constructed by using each chip's reset circuit independently, the microcomputer program will need to change the peripheral chip's reset circuit in order to absorb variations in the reset circuit in the microcomputer chip and the reset circuits in the peripheral chips. It is necessary to make a meeting equal to the time when the reset is completed plus an additional time. However, this method has a problem in that it is not suitable when it is necessary to have the microcomputer perform input/output control immediately after power is turned on.

The purpose of the present invention is to solve the problems in the prior art, and to eliminate the need for adding external additional circuits and signal lines.
A microcomputer peripheral in which the microcomputer reads the peripheral chip reset signal from the peripheral chip as one of the data, accurately determines when the peripheral chip can normally operate, and enables input/output control immediately after the peripheral chip has been reset. The goal is to provide tips.

An embodiment of the present invention will be described below with reference to a circuit configuration diagram shown in FIG.

In FIG. 1, reference numeral 100 indicates a microcomputer chip, and reference numeral 101 indicates a peripheral chip whose input/output is controlled by the microcomputer chip 100. A resistor R and a capacitor C are connected to the input side of input pin 1 of the peripheral chip 101.
A power source E is connected to the other end, and the other end of the capacitor C is grounded. Therefore, the signal input to the reset circuit 2 from the input pin 1 has a waveform that lags the power supply voltage by one order. Reset circuit 2
Now, waveform-shape this input signal and send it to peripheral chip 1.
01 is supplied to each predetermined location through the lead wire 3 as a reset signal.

In the microcomputer chip 100, a reset signal is obtained in the same manner, and when the reset signal is obtained, operation according to the program is started.

On the other hand, the output signal of the reset circuit 2 is sent to the driver 4.
The signal is further guided to the bus line 6 in the peripheral chip 101 via the transfer gate 5. This transfer gate 5 has an output obtained by decoding an address signal from a microcomputer chip 100 inputted to an input pin 7 by a decoder 8, and
An AND gate 10 performs a logical product with an input/output strobe signal from a microcomputer chip 100 input to an input pin 9, and its output is used as a gate signal.

Therefore, when the peripheral chip 101 receives a read access from the microcomputer chip 100 at a predetermined address, the reset signal in the peripheral chip 101 is transferred as data to the bus line 6 in the peripheral chip 101, and is then transferred to the bus line 6.
The signal is sent to the peripheral chip 101 via the buffer 11.
The signal is configured to be provided as an output (1-bit data signal) to the microcomputer chip 100 via the data bus pin 12 of the microcomputer chip 100.

Therefore, the microcomputer chip 100 can read the reset signal, and the program can accurately determine when the reset of the peripheral chip 101 is completed, and input/output control can be performed immediately after the reset of the peripheral chip 101 is completed. In this case, the reset circuit that outputs the reset signal, the circuit means that gives this reset signal to the bus line 6, and the circuit means that outputs the reset signal in the bus line 6 to the microcomputer side in response to a command from the microcomputer chip are basically Generally speaking, since the elements are required to be built into the peripheral chip itself, there is no need for external additional circuits, and among the above-mentioned circuits, even those that need to be added for the purpose of the present invention. The area occupied within the peripheral chip is extremely small.

FIG. 4 is a time chart for explaining the operation of the present invention. In the figure, there are 1 and 2 peripheral chips 101 for a microcomputer chip 100.
It is envisioned as an expanded system that includes: Now, when the power supply voltage E is applied at time _t0 , each chip completes its initialization within the time period _t1 to _t3 , and generates a reset signal. This is an example in which peripheral chip 1 requires a relatively short time, and peripheral chip 2 requires a relatively long time. At time _t2 , the microcomputer chip 100 starts operating according to the program, and accesses the peripheral chips 1 and ₂ as necessary according to the program. ₁ , so even if it is valid immediately, accessing peripheral chip 2 before t ₃ is invalid. The microcomputer chip 100 can naturally know this from the data of each peripheral chip.

As explained above, according to the present invention, the microcomputer reads out the reset signal from the peripheral chip without requiring an external additional circuit, accurately determines when to end the reset of the peripheral chip by a program, and resets the peripheral chip. It is possible to perform input/output control immediately after the reset is completed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing the configuration of a conventional example, and FIG. 4 is a time chart explaining the operation of the present invention. Explanation of symbols, 1, 7, 9...Input pin, 2...
Reset circuit, 5...Transfer gate, 6...
... bus line, 8 ... decode, 12 ... data bus pin, 100 ... microcomputer chip, 101 ... peripheral chip.

Claims (1)

[Scope of Claims] 1. In a peripheral chip of a computer system in which a microcomputer and a peripheral circuit are formed on different chips and are configured by exchanging necessary data and signals, the chip initializes in response to the application of power. a reset circuit for supplying a reset signal to a predetermined location in response to a rising edge of a power supply signal; and a first transfer means for supplying the reset signal to an internal bus line in response to an external access signal. , and second transfer means for outputting a reset signal on the intra-chip bus line to a data bus pin in response to the access signal. 2. The access signal includes an address signal from a microcomputer chip, and the first transfer means includes a decoder that decodes the address signal to generate a control signal and a gate circuit controlled by the control signal. A microcomputer peripheral chip according to claim 1, characterized in that: 3. The access signal includes an input/output control signal from a microcomputer chip, and the input/output control signal is applied to the first and second transfer means to control each transfer means. A microcomputer peripheral chip according to item 1 or 2.