JPS6229812B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a code conversion circuit that converts an input signal consisting of a fixed length code into a signal consisting of a variable length code, and outputs the signal. It is related to.

A fixed length code system is a code system in which the number of bits constituting one word is always constant, and corresponds to a variable length code system in which the number of bits in one word changes depending on the content of information. There is generally no flexibility between fixed-length codes and variable-length codes, and code conversion circuits are required between systems with different code formats.

FIG. 1 is a block diagram showing the configuration of a conventional code conversion circuit, and shows a code conversion circuit for converting input data consisting of fixed length codes into output data consisting of variable length codes. In the same figure, 1
is a matrix, 2 is a word length detection circuit, 3 is an adder circuit, and 4 and 5 are flip-flops.

In FIG. 1, input data consisting of fixed length codes is input into a matrix 1. Matrix 1 is an n×n rotating element that moves the n-bit data input in parallel by an arbitrary number of bits without changing the order, as if rotating the n-bit data in a ring. It has the function of converting the bit position and outputting it in parallel.

The word length detection circuit 2 detects the word length of the current output of the matrix 1. The input data consisting of fixed-length codes input to matrix 1 has a pattern indicating the boundary of the variable-length codes composing it inserted, so that the word length detection circuit 2 outputs the output of matrix 1. You can know the length of the variable length code in .

Depending on the word length detected by the word length detection circuit 2, a one-word variable length code at the output of the matrix 1 is read into the flip-flop 5. The variable length code read into the flip-flop 5 is read out using the basic clock and becomes output data.

On the other hand, the word length signal output from the word length detection circuit 2 is applied to an adder circuit 3 and added to the address used to control the matrix 1, which is stored in a flip-flop 4, and the output of the adder circuit 3 is The flip-flop 4 is rewritten by this. The output of flip-flop 4 is applied as an address to matrix 1, thereby causing matrix 1 to rotate by the number of bits corresponding to the detected word length.
Therefore, in the output of matrix 1, the head of the next variable length code appears at the most significant bit position, waiting for the next conversion operation.

FIG. 2 explains the operation timing in the code conversion circuit of FIG. 1. In the figure, a indicates the basic clock, and (1), (2), . . . are the clock timings, respectively. b indicates the operation at each stage, A is matrix control, B is word length detection, and C is addition. In this manner, the circuit shown in FIG. 1 can output one word of variable length code output data converted from fixed length code input data for each basic clock.

However, as mentioned above, the conventional code conversion circuit shown in FIG.
A loop consisting of a matrix, a word length detection circuit, and an adder circuit must operate. Therefore, when used in a high bit rate pulse circuit, the speed requirements for each circuit component are extremely strict.

The present invention attempts to eliminate such drawbacks of the prior art, and its purpose is to perform word length detection over n words (n is 2 or a positive integer greater than 2), and to perform word length detection over n basic time slots. An object of the present invention is to provide a code conversion circuit that can reduce speed requirements for circuit components by controlling a matrix within the process to obtain an output. In order to achieve this object, in the code conversion circuit of the present invention, input data consisting of fixed length codes is rotated in a ring in a circuit for converting data consisting of fixed length codes to data consisting of variable length codes. It is equipped with a matrix to output, a word length detection circuit for detecting the word length of a fixed length code at the output of the matrix, and a flip-flop for reading the output of the matrix, and the word length detection in the word length detection circuit is 2 or a positive integer greater than 2) words, and
The present invention is characterized in that the output data of the matrix is rotated to a fixed position by one fixed length code word each time the output data of the matrix is read out based on the word length detection result.

Examples will be described below.

FIG. 3 is a block diagram showing the configuration of an embodiment of the code conversion circuit of the present invention. In the same figure, 11
1 is a matrix, 12 is a word length detection circuit, 13 is a control circuit, and 14, 15, and 16 are flip-flops. In the figure, a case where n=2, that is, word length detection is performed every two words, is illustrated.

FIG. 4 is a diagram for explaining the operation timing in the code conversion circuit of FIG. 3. In the figure, a indicates the timing of the basic clock, and b indicates the processing at each stage. c is matrix 1, which is a code with bit positions shifted for variable length encoding.
1 to the flip-flop 14 or 15.

In FIG. 3, input data consisting of fixed length codes is provided to a matrix 11. The matrix 11 has the same function as that explained with reference to FIG. 1, and rotates the input data in a ring shape to move the bit position and output it.

When the first basic clock (1) is input, the control circuit 13 controls the matrix 11 to generate the next fixed-length code excluding the fixed-length code that has already been processed by the previous operation in the input fixed-length code data. The fixed length code data is rotated so that the beginning of the long code matches the most significant bit in the output of matrix 11. In FIG. 4b, A indicates the timing of such matrix control.

When the matrix control shown in FIG. 4bA is completed, one word of variable length code data in the upper bit of the matrix 11 is read into the flip-flop 14 (FIG. 4c). At the same time, the word length detection circuit 12 detects the word length of the output of the matrix 11 over two words (FIG. 4b).

When the next basic clock (2) is input, the contents of flip-flop 14 are read into flip-flop 16 (FIG. 4bC). flipflop 16
The contents of are further read out by the next basic clock, resulting in output data consisting of a code with bit positions converted for variable length encoding.

The control circuit 13 controls the matrix 11 again, and based on the word length information detected at step B,
The operation moves on to rotating the fixed-length code data so that the beginning of the next variable-length code, excluding the variable-length code that has been processed at step C, matches the most significant bit in the output of the matrix 11. The word length of the data input into the matrix is also counted. In FIG. 4b, D indicates the timing of such matrix control.

When the matrix control shown in FIG. 4bD is completed, one word of variable length code data in the upper bit of the matrix 11 is read into the flip-flop 15 (FIG. 4c). flip flop 15
The contents of the flip-flop 16 are further read into the flip-flop 16, and the contents of the flip-flop 16 are read out by the next basic clock to become output data consisting of a code with shifted bit positions for variable length encoding. Note that the operations of each component other than the matrix at each of the above-mentioned operation stages are also performed under the control of the control circuit 13.

By repeating such operations, the code conversion circuit shown in FIG. 3 detects the word length every two cycles of the basic clock and processes two words. Therefore, unlike conventional code conversion circuits, it is not necessary to complete loop operations including matrix control and word length detection in the cycle of the basic clock, and the speed requirements for each circuit component are greatly reduced. Even when the number of words n to be processed in one operation is 2 or more, the code conversion circuit of the present invention can be configured in the same way, and the larger n is, the easier the speed requirements for each circuit component are. Needless to say, it is advantageous.

As explained above, according to the code conversion circuit of the present invention, speed requirements for each circuit component can be relaxed, and therefore, it is particularly advantageous when used in a high bit rate pulse circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional code conversion circuit, FIG. 2 is a diagram for explaining the operation timing in the code conversion circuit of FIG. 1, and FIG. 3 is an implementation of the code conversion circuit of the present invention. FIG. 4 is a block diagram showing the configuration of an example, and is a diagram for explaining the operation timing in the code conversion circuit of FIG. 3. 1... Matrix, 2... Word length detection circuit, 3...
... Addition circuit, 4, 5 ... Flip-flop, 11
...Matrix, 12...Word length detection circuit, 13...
...Control circuit, 14, 15, 16...Flip-flop.

Claims (1)

[Claims] 1 In a circuit for converting data consisting of fixed-length codes into data consisting of variable-length codes, there is a matrix that rotates input data consisting of fixed-length codes in a ring and outputs the resultant data, and a word of the fixed-length code at the output of the matrix. a word length detection circuit that detects the word length;
a flip-flop for reading the output of the matrix, the word length detection circuit performs word length detection over n (n is 2 or a positive integer greater than 2) words, and the A code conversion circuit characterized in that output data of a matrix is rotated to a fixed position by one fixed length code word each time the output data is read.