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JPS6229835B2 - - Google Patents
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JPS6229835B2 - - Google Patents

Info

Publication number
JPS6229835B2
JPS6229835B2 JP57140303A JP14030382A JPS6229835B2 JP S6229835 B2 JPS6229835 B2 JP S6229835B2 JP 57140303 A JP57140303 A JP 57140303A JP 14030382 A JP14030382 A JP 14030382A JP S6229835 B2 JPS6229835 B2 JP S6229835B2
Authority
JP
Japan
Prior art keywords
line
circuit
line width
image
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57140303A
Other languages
Japanese (ja)
Other versions
JPS5930164A (en
Inventor
Takeshi Masui
Toshio Matsura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57140303A priority Critical patent/JPS5930164A/en
Publication of JPS5930164A publication Critical patent/JPS5930164A/en
Publication of JPS6229835B2 publication Critical patent/JPS6229835B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00Image analysis
    • G06T7/60Analysis of geometric attributes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00Indexing scheme for image analysis or image enhancement
    • G06T2207/30Subject of image; Context of image processing
    • G06T2207/30108Industrial image inspection
    • G06T2207/30141Printed circuit board [PCB]

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)

Description

【発明の詳細な説明】 (A) 発明の技術分野 本発明は自動設計システム等において用いられ
る画像入力装置あるいは画像読取装置等の線幅決
定回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a line width determining circuit for an image input device or an image reading device used in an automatic design system or the like.

(B) 技術の背景 プリント配線パターンの設計には早くから自動
設計システムが採用されているが、コンピユータ
等の設計においてプリント配線パターンの設計の
占める比率は近時ますます増大する傾向にあり、
したがつて、その設計時間の短縮および設計工数
の低減が非常に重要視されている。
(B) Technical background Automatic design systems have been used for the design of printed wiring patterns from an early stage, but the proportion of printed wiring pattern design in the design of computers and other devices has recently been increasing.
Therefore, much importance is placed on shortening the design time and reducing the number of design man-hours.

一方プリント配線パターンの自動設計において
画像データ処理の占める比率は非常に大きく、し
たがつて、一般に、プリント配線パターンを等ピ
ツチの格子線の交点を通るように描き、この画像
データを格子線の交点毎にコード化して大幅に圧
縮することによつてデータ処理時間を短縮し、前
記設計時間の短縮および設計工数の低減を図つて
いる。
On the other hand, image data processing occupies a very large proportion in the automatic design of printed wiring patterns. Therefore, generally, printed wiring patterns are drawn passing through the intersections of grid lines of equal pitch, and this image data is used at the intersections of the grid lines. The data processing time is shortened by encoding each data and significantly compressing it, thereby reducing the design time and the number of design man-hours.

(C) 従来技術と問題点 前述のように、プリント配線パターンは一般に
第1図に例示するように、すべてのピツチcが等
しく互に直交する格子線aの交点bを通つて描か
れており、このような線画像は格子線aの交点b
を中心とし、点線にて示すように一辺の長さをc
とする正方形の分割画像毎に、線幅を例えば大・
中・小の3種類のいずれかに決定し第2図に模擬
的に示すようにコード化をおこなつている。
(C) Prior Art and Problems As mentioned above, printed wiring patterns are generally drawn through intersections b of grid lines a, in which all pitches c are equal and orthogonal to each other, as illustrated in FIG. , such a line image has intersection point b of grid line a
Centered on , the length of one side is c as shown by the dotted line.
For each square divided image, set the line width to large or
One of the three types, medium and small, was determined and coded as shown schematically in Figure 2.

このような用途に対して従来から用いられてい
る線幅決定回路は、特定の格子線ピツチを対象と
するものであり、したがつて他のプリント配線パ
ターンに対しては利用できないという欠点があつ
た。
Line width determination circuits conventionally used for such applications target specific grid line pitches, and therefore cannot be used for other printed wiring patterns. Ta.

(D) 発明の目的 本発明の目的は前記従来例の欠点を排し、任意
の格子線ピツチのプリント配線パターンに対し利
用し得る線幅決定回路を得ることにある。
(D) Object of the Invention The object of the present invention is to eliminate the drawbacks of the conventional example and to provide a line width determining circuit that can be used for printed wiring patterns with arbitrary grid line pitches.

(E) 発明の構成 すなわち本発明になる線幅決定回路は、等ピツ
チの格子線の交点を通つて描かれた線画像を前記
交点毎に切取つて得られる分割画像をラスタ走査
し画素毎に2値データとして読取り、走査方向の
所定領域内における線画部に対応する画素の連続
数を所定の閾値と比較することによつて走査毎の
最大線幅を前記閾値によつて定まる複数種のいず
れかに決定する第1の決定回路と、副走査方向の
所定領域内における前記第1の決定回路による前
記複数種別の線幅決定数を所定の閾値と比較する
ことによつて前記分割画像の走査方向の線幅を決
定する第2の決定回路と、前記分割画像のラスタ
走査を水平方向におこなつたときの前記第2の決
定回路の出力と該分割画像のラスタ走査を垂直方
向におこなつたときの前記第2の決定回路の出力
とを統合する統合回路とを備え、前記線画像の線
幅を前記分割画像毎に決定するようにしたもので
ある。
(E) Structure of the Invention In other words, the line width determining circuit according to the present invention raster-scans a divided image obtained by cutting out a line image drawn through the intersections of equally pitched grid lines at each intersection, and calculates the divided image for each pixel. By reading it as binary data and comparing the number of consecutive pixels corresponding to a line drawing part in a predetermined area in the scanning direction with a predetermined threshold value, the maximum line width for each scan is determined by one of multiple types determined by the threshold value. scanning of the divided image by comparing the number of line widths determined for the plurality of types by the first determining circuit within a predetermined area in the sub-scanning direction with a predetermined threshold; a second determining circuit that determines a line width in a direction; and an output of the second determining circuit when the divided image is raster scanned in the horizontal direction, and the divided image is raster scanned in the vertical direction. and an integration circuit that integrates the outputs of the second determination circuit when the line width of the line image is determined for each of the divided images.

(E) 発明の実施例 以下、本発明の要旨を実施例により具体的に説
明する。
(E) Examples of the invention Hereinafter, the gist of the present invention will be specifically explained using examples.

第3図は本発明一実施例のブロツク図を示し、
1は各構成部の制御をおこなう制御回路、2は第
1図に例示したように等ピツチCの格子線aの交
点bを通つて描かれた線画像を、交点b毎に点線
のように方形に切取つて得られる分割画像毎に、
該分割画像と後記ビデオバツフアの出力とを交互
に切換えて後記第1の決定回路に供給する切換回
路、3は切換回路2から供給される分割画像をラ
スタ走査し画素毎に2値データとして読取り、走
査方向の所定領域内における線画部に対応する画
素の連続数を所定の閾値と比較することによつて
走査毎の最大線幅を前記閾値によつて定まる複数
種のいずれかに決定する第1の決定回路、4は副
走査方向の所定領域内における第1の決定回路3
による前記複数種別の線幅決定数を所定の閾値と
比較することによつて前記分割画像の走査方向の
幅を決定する第2の決定回路、5は前記分割画像
のラスタ走査を水平方向におこなつたときの第2
の決定回路4の出力と該分割画像のラスタ走査を
垂直方向におこなつたときの第2の決定回路4の
出力とを統合する統合回路、6は前記分割画像を
直角に回転して一時記憶するビデオバツフア、7
は第4図に示す分割画像の副走査方向Yの所定領
域AおよびBに関し第5図に示すような領域信号
dおよびeを発生する領域信号発生回路である。
FIG. 3 shows a block diagram of an embodiment of the present invention,
1 is a control circuit that controls each component, and 2 is a line image drawn through intersections b of grid lines a of equal pitch C, as illustrated in FIG. For each divided image obtained by cutting it into squares,
A switching circuit 3 alternately switches the divided image and the output of a video buffer described later and supplies it to a first determining circuit described later; 3 raster scans the divided image supplied from the switching circuit 2 and reads it as binary data for each pixel; a first step of determining the maximum line width for each scan to be one of a plurality of types determined by the threshold value by comparing the number of consecutive pixels corresponding to the line drawing portion within a predetermined area in the scanning direction with a predetermined threshold value; 4 is a first determining circuit 3 within a predetermined area in the sub-scanning direction.
A second determining circuit 5 determines the width of the divided image in the scanning direction by comparing the determined number of line widths of the plurality of types with a predetermined threshold; 2nd time when it was finished
An integration circuit 6 integrates the output of the second decision circuit 4 and the output of the second decision circuit 4 when the divided image is raster scanned in the vertical direction; 6 rotates the divided image at right angles and temporarily stores the resultant output; Video battle, 7
is an area signal generating circuit which generates area signals d and e as shown in FIG. 5 for predetermined areas A and B in the sub-scanning direction Y of the divided image shown in FIG.

第6図は第1の決定回路3の具体的構成例を示
し、切換回路2から検出される分割画像fをラス
タ走査し走査毎に走査領域内における線画部に対
応する画素の最多連続数をレジスタ31およびレ
ジスタ32に記憶する2種類の閾値と比較するこ
とによつて走査毎の最大線幅を大・中・小のいず
れかに決定しgおよびhの2ビツトによつて出力
するものである。
FIG. 6 shows a specific configuration example of the first determining circuit 3, in which the divided image f detected by the switching circuit 2 is raster-scanned and the maximum number of consecutive pixels corresponding to the line drawing part in the scanning area is calculated for each scan. The maximum line width for each scan is determined as large, medium, or small by comparing it with two types of threshold values stored in registers 31 and 32, and is output using two bits g and h. be.

第7図は第2の決定回路4の具体的構成例を示
し、前記領域信号dおよびeを用い前記副走査方
向の所定領域毎の第1の決定回路3の出力gおよ
びhのカウント数をレジスタ42に記憶する閾値
と比較することによつて、分割画像の走査方向の
線幅をk・l・mおよびnの4ビツトによつて出
力するものである。
FIG. 7 shows a specific example of the configuration of the second determining circuit 4, which uses the area signals d and e to determine the count numbers of the outputs g and h of the first determining circuit 3 for each predetermined area in the sub-scanning direction. By comparing it with the threshold value stored in the register 42, the line width in the scanning direction of the divided image is outputted as 4 bits k, l, m, and n.

また第8図は統合回路5の具体的構成例を示
す。
Further, FIG. 8 shows a specific example of the configuration of the integrated circuit 5.

以上のような構成によつて、任意の等ピツチの
格子線の交点を通つて描かれた線画像の線幅を、
格子線の交点毎に前記大・中および小のいずれか
に決定することができる。
With the above configuration, the line width of a line image drawn through the intersections of grid lines of arbitrary equal pitch can be calculated as follows:
Each intersection of the grid lines can be determined to be either large, medium, or small.

(G) 発明の効果 以上説明したように、本発明によれば、任意の
等ピツチの格子線の交点を通つて描かれた線画像
の線幅を格子線の交点毎に決定することができ
る。
(G) Effects of the Invention As explained above, according to the present invention, the line width of a line image drawn through the intersections of arbitrary grid lines of equal pitch can be determined for each intersection of the grid lines. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は線画像の例、第2図は線幅決定の説明
図、第3図は本発明一実施例のブロツク図であ
り、1は第1の決定回路、4は第2の決定回路、
5は統合回路を示す。 また第4図および第5図は本発明一実施例の説
明図、第6図、第7図および第8図は、それぞ
れ、第1の決定回路3・第2の決定回路4および
統合回路5の具体的構成例である。
FIG. 1 is an example of a line image, FIG. 2 is an explanatory diagram of line width determination, and FIG. 3 is a block diagram of an embodiment of the present invention, where 1 is a first determining circuit and 4 is a second determining circuit. ,
5 indicates an integrated circuit. Further, FIGS. 4 and 5 are explanatory diagrams of an embodiment of the present invention, and FIGS. 6, 7, and 8 are diagrams showing the first decision circuit 3, the second decision circuit 4, and the integrated circuit 5, respectively. This is a specific configuration example.

Claims (1)

【特許請求の範囲】[Claims] 1 等ピツチの格子線の交点を通つて描かれた線
画像を前記交点毎に切取つて得られる分割画像を
ラスタ走査し画素毎に2値データとして読取り、
走査方向の所定領域内における線画部に対応する
画素の連続数を所定の閾値と比較することによつ
て走査毎の最大線幅を前記閾値によつて定まる複
数種のいずれかに決定する第1の決定回路と、副
走査方向の所定領域内における前記第1の決定回
路による前記複数種別の線幅決定数を所定の閾値
と比較することによつて前記分割画像の走査方向
の線幅を決定する第2決定回路と、前記分割画像
のラスタ走査を水平方向におこなつたときの前記
第2の決定回路の出力と該分割画像のラスタ走査
を垂直方向におこなつたときの前記第2の決定回
路の出力とを統合する統合回路とを備え、前記線
画像の線幅を前記分割画像毎に決定することを特
徴とする線幅決定回路。
1. A line image drawn through the intersections of equally pitched grid lines is cut out at each intersection, and the divided images obtained are raster-scanned and read as binary data for each pixel,
a first step of determining the maximum line width for each scan to be one of a plurality of types determined by the threshold value by comparing the number of consecutive pixels corresponding to the line drawing portion within a predetermined area in the scanning direction with a predetermined threshold value; and determining the line width in the scanning direction of the divided image by comparing the number of line widths determined for the plurality of types by the first determining circuit in a predetermined area in the sub-scanning direction with a predetermined threshold value. an output of the second determining circuit when the divided image is raster scanned in the horizontal direction, and an output of the second determining circuit when the divided image is raster scanned in the vertical direction. A line width determination circuit, comprising: an integration circuit that integrates the outputs of the determination circuit, and determines the line width of the line image for each of the divided images.
JP57140303A 1982-08-12 1982-08-12 Line width determining circuit Granted JPS5930164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57140303A JPS5930164A (en) 1982-08-12 1982-08-12 Line width determining circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57140303A JPS5930164A (en) 1982-08-12 1982-08-12 Line width determining circuit

Publications (2)

Publication Number Publication Date
JPS5930164A JPS5930164A (en) 1984-02-17
JPS6229835B2 true JPS6229835B2 (en) 1987-06-29

Family

ID=15265644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57140303A Granted JPS5930164A (en) 1982-08-12 1982-08-12 Line width determining circuit

Country Status (1)

Country Link
JP (1) JPS5930164A (en)

Also Published As

Publication number Publication date
JPS5930164A (en) 1984-02-17

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