JPS6230384B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic waveform generation circuit for generating various logic waveforms for use in, for example, a logic circuit testing device.

When performing functional tests on logic circuits, the logic circuit under test should be equipped with NRZ (Non Retrun Zero) waveforms and RZ waveforms.
It is necessary to test by applying various logic waveforms such as (Retrun Zero) waveform or exclusive OR (E-OR) waveform of NRZ and RZ. For this reason, a conventional logic waveform generation circuit for generating logic waveforms has been configured as shown in FIG.

That is, the logic data (FIG. 2A) that controls the generated logic waveform is applied from the input terminal 11 to the data terminal D of the timing D-type flip-flop 12, and from the terminal 13 to the timing clock (FIG. 2B). A waveform as shown in FIG. 2D is obtained from the output terminal Q of the flip-flop 12. When outputting as an NRZ waveform, an NRZ selection signal is applied to the terminal 14. This signal opens the gate 15, and the waveform shown in FIG. 2D obtained at the output terminal Q of the flip-flop 12 passes through the gate 15. circuit 1
6. Sequentially through the polarity control circuit 17 to the output terminal 18
is output to. The polarity control circuit 17 is for determining whether or not to invert the polarity of the output waveform, and is composed of, for example, an exclusive OR circuit, and is configured to combine the polarity control signal from the terminal 19 with the output of the OR circuit 16. An exclusive OR is taken. When inverting the polarity of the output waveform, the polarity control signal applied to the terminal 19 is set to logic "1".

A second clock (C in FIG. 2) is input to the terminal 21, and the AND circuit 22 calculates the AND of this second clock and the output of the flip-flop 12.
The RZ waveform shown in Figure E is created. When the RZ selection signal is applied to the terminal 23 and the gate 24 is opened, this RZ waveform is supplied to the OR circuit 16 through the gate 24, and is obtained at the terminal 18. Further, the output of flip-flop 12 and the second clock at terminal 21 are exclusive-ORed in circuit 25, and the output is as shown in FIG. 2F. This EOR waveform is supplied to the OR circuit 16 with the gate 27 opened by the EOR selection signal applied to the terminal 26.

For example, as shown in FIG. 3, a plurality of such logic waveform generation circuits ₁₁ to _1o are provided, and the logic waveforms from these circuits are connected to the corresponding input terminals of the logic circuit under test 28 such as a microprocessor. are simultaneously supplied to the logic circuit under test 28 at that time.
It is tested whether the operation is performed correctly. In this case, the timings of the plurality of input waveforms input to the logic circuit under test 28 must be in a predetermined state. For example, set the timing of one input waveform to 1
Circuit under test 28 when changed within the operating cycle
The timing of the test waveform must be accurate.

However, in the logic waveform generation circuit shown in Figure 1, the rise and fall of each generated waveform and multiple time change points pass through the same path, so a circuit that accurately adjusts the time of each waveform change point is required. I couldn't insert it. That is, for example, the rising and falling edges of each waveform vary due to variations in the threshold values of each logic circuit such as a gate, but in this case, the rising and falling edges vary in opposite directions. For this reason, if a delay circuit is inserted into the logic waveform generation circuit to adjust one of the rising and falling edges, the deviation of the other will become larger.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logical waveform generation circuit that can independently adjust the times of the rise and fall of each waveform and the changing points of the waveform, in order to eliminate these drawbacks.

FIG. 4 shows an example of a logic waveform generation circuit according to the present invention. According to the present invention, logic data of opposite polarity is supplied to a plurality of coincidence selection circuits 31-36. For example, logic data from the input terminal 11 is supplied to the input gate 37, and positive logic data and negative logic data are output. These positive polarity logic data and negative polarity logic data are supplied to match selection circuits 31-36.

Coincidence selection circuits 31 to 36 are supplied with clocks generated at different points within one cycle of logic data, and when a coincidence between these clocks and the input logic data is detected and selected by a selection signal. , the match detection output is output. The coincidence selection circuits 31 to 36 have the same configuration. For example, the coincidence selection circuit 31 is provided with selection gates 38 and 39, and the selection gates 38 and 39 receive positive polarity logic data and negative polarity logic data from the input gate 37. Each is input. selection gate 38,
The output of 39 is wired-ORed and supplied to a coincidence detection gate 41, and the output of the gate 41 becomes the output of the coincidence selection circuit.

The selection gates 38 and 39 of the coincidence selection circuits 31 to 36 are connected to terminals 42 and 43, 44 and 4, respectively.
5, 46 and 47, 48 and 49, 50 and 5
When selection signals are applied from 1, 52 and 53, the corresponding gates are opened. Match selection circuits 31 and 34, 32 and 35, 33 and 3
A terminal 54 is connected to each coincidence detection gate 41 of 6, respectively.
55 and 56 clocks are input, respectively. Therefore, the coincidence selection circuits 31 to 36 are selected by the selection signals applied to the terminals 42 to 53, and one of the positive polarity and negative polarity logic data is selected, and the selected coincidence selection circuit selects the selected logic data. Coincidence between the data and the clock applied to the coincidence selection circuit is detected by a coincidence detection gate 41, and the detection result is output. Each clock is selected corresponding to the required change point within one cycle Tc of the generated logic waveform.

The outputs of the match selection circuits 31 to 33 are sent to the OR circuit 57.
is supplied to the set terminal S of flip-flop 58 through
It is supplied through circuit 59 to reset terminal R of flip-flop 61. The output of flip-flop 58 is outputted to output terminal 61 as a generated logic waveform.

Coincidence selection circuits 31 to 36 and flip-flop 5
A delay circuit is inserted in at least one of the paths between the 8 and 8. In the illustrated example, the match selection circuits 31 to 33 and
Delay circuits 62 to 6 are connected to the OR circuit 57, respectively.
4 are inserted in series, and match selection circuits 34 to 36
Delay circuits 65 to 67 are inserted in series with OR circuit 59.

In the configuration shown in FIG. 4, input terminal 1
The logic data of 1 is shown in Figure 5A, terminals 54, 55, 5.
6 clocks as shown in FIG. 5B, C, and D, to generate a positive NRZ waveform, the terminal 42
A selection signal is applied to the terminal 49 to set the flip-flop 58 with the output of the coincidence selection circuit 31, a selection signal is applied to the terminal 49 and the flip-flop 58 is reset with the output of the coincidence selection circuit 34, and the terminal 54 is set as shown in FIG. An NRZ waveform of input logic data that rises and falls at the clock is obtained at the output terminal 61. Similarly, when selection signals are applied to terminals 43 and 48, a negative NRZ waveform is obtained as shown in FIG. 5F.

By applying selection signals to terminals 44 and 52,
By applying selection signals to terminals 46 and 50, negative RZ waveforms shown in FIG. 5H are obtained. Terminals 42, 45, 46, 4
By applying selection signals to terminals 9, 50 and 51, the EOR waveform shown in FIG. 5I is obtained.
By applying selection signals to 4, 47, 48, 51, and 52, the negative EOR shown in FIG. 5J is obtained.

Various logic waveforms can be obtained by selectively applying selection signals to the terminals 42 to 53 in this way, and delay circuits 62 to 67 are inserted in the paths that determine the rise and fall of each waveform. , by adjusting these, the rise and fall timings of each waveform can be adjusted independently.

As explained above, in the logic waveform generation circuit according to the present invention, the time of each change point of the generated logic waveform can be adjusted independently. This is extremely effective when it is necessary to accurately adjust the time between each other. Furthermore, by making the circuit for adjusting the delay time externally controllable, the delay time can be automatically adjusted by a computer or the like.

At least one match selection circuit is provided for each clock, the number and number of clocks being determined by the required waveform. Also, depending on the required waveform, the selection gate 3 in the coincidence selection circuit may be
One of 8 and 39 is omitted.

[Brief explanation of the drawing]

Figure 1 is a logic circuit diagram showing a conventional logic waveform generation circuit, Figure 2 is a waveform diagram for explaining the operation of the circuit shown in Figure 1, and Figure 3 is a logic waveform generation circuit and logic circuit under test. Block diagram showing the relationship between
5 is a logic circuit diagram showing an example of a logic waveform generation circuit according to the present invention, and FIG. 5 is a waveform diagram showing an example of input logic data, clock, and output logic waveforms in FIG. 4. 11...Logic data input terminal, 31-36...Coincidence selection circuit, 38, 39...Selection gate, 41...Coincidence detection gate, 42-53...Selection signal input terminal,
54-56...Clock input terminal, 61...Output terminal, 62-67...Delay circuit.

Claims (1)

[Claims] 1. An input gate to which logical data is supplied and outputs positive polarity data and negative polarity data; a first selection gate pair group provided with a plurality of selection gate pairs whose output sides are connected to each other; and a first selection gate pair group provided with a plurality of selection gate pairs whose output sides are connected to each other; and the positive polarity data and negative polarity data are respectively supplied, one of which is selected by a selection signal. a second selection gate pair group including a plurality of selection gate pairs whose output sides are connected to each other; a plurality of clocks generated at different points within one cycle of the logic data; and the first selection gate pair group. first and second coincidence detection gate groups that detect coincidence with each output of the gate pair group and each output of the second selected gate pair group; and each gate of the first and second coincidence detection gate groups. a first and second delay circuit group inserted on the output side;
A logic waveform generation circuit comprising a flip-flop which is set by the output of the first delay circuit group, reset by the output of the second delay circuit group, and outputs a target logic waveform.