JPS6230455B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram-controlled data processing device, and particularly to speeding up the execution of instructions thereof.

FIG. 1 is a block diagram showing an example of a conventional data processing device. In the figure, 1 is a main memory that stores programs and data, 2 is a central processing unit, 3 is a memory bus between this central processing unit and the main memory 1, 20 is an internal memory of the central processing unit 2,
21 is a memory address register that holds memory addresses; 22 is a memory data register that exchanges data with the main memory 1; 23 is an arithmetic processing section that performs program operations; 24 is a data bus within the central processing unit; is a status flag that holds the status of the calculation result by the calculation processing unit 23;
26 is an arithmetic control unit that controls the operation of the central processing unit 2.

In the data processing device configured as described above, registers necessary for executing instructions, such as general-purpose registers, floating point registers, working registers, etc., are allocated to the internal memory 20 as shown in FIG. FIG. 2 is a register allocation diagram showing an example of register allocation within the internal memory 20. As shown in FIG.
In the example of FIG. 2, n general-purpose registers, n floating point registers, and working registers are allocated. Data is held in each of the above registers as shown in FIG. FIG. 3 is a data format diagram showing an example of data formats stored in general-purpose registers and floating-point registers. Figure 3a shows an example of a fixed-point number stored in a general-purpose register.The fixed-point number is one word long (one word is 16 bits), and negative numbers are in two's complement format. bit 15 is the sign S
It is. FIG. 3 shows an example of a floating point number stored in a floating point register, and the floating point number has a sign part S, an exponent part E,
It consists of a mantissa part M, and has a total length of two words. The number expressed in floating point format is (-1) ^S ×16 ^E-Eo
×0.M (E _p is a fixed value). It is also possible to construct each register in the internal memory 20 shown in FIG. 2 with independent hardware so that each register has a separate signal input terminal and signal output terminal, but in this case, Since the amount of hardware increases and the area for input signal lines and output signal lines increases, multiple registers are combined into one internal memory 20 as shown in FIGS. 1 and 2. It was. The internal memory 20 is equipped with a common data line and a common address line, and when attempting to retrieve desired data (that is, the contents of a desired register) from the internal memory 20, the address indicating the storage location of the data is transferred to the common address line. The data must be input from the address lines and read out onto the common data lines.

The address of the program stored in main memory 1 is set in memory address register 21, and instructions are read from main memory 1. The read instruction is set in the memory data register 22, decoded by the arithmetic control section 26, and a microprogram for executing the instruction is started. When the execution of instructions by a series of microprograms is completed, the next instruction address is set in the memory address register 21 and the above procedure is repeated. Through this operation, the programs read from the main memory 1 are sequentially executed.

FIG. 4 shows a microprogram flow of an instruction that determines whether the content of a general-purpose register is positive or negative and performs process 1 or process 2 depending on the result.

FIG. 4 is a flowchart of a microprogram for instruction execution, in which (40) is a general-purpose register read step, (41) is a sign determination step, (42) is a process 1 step, and (43) is a process 2 step. This is the step.

Since all the general purpose registers are allocated in the internal memory 20, a read step (40) of the general purpose registers is performed first. At this time, the arithmetic processing section 23 determines whether the data is positive or negative, and a status flag 25 indicating the positive or negative state of the data is set. Next microprogram sign determination step (41)
The contents of the status flag 25 are determined, and the microprogram is branched depending on whether the data is positive or negative. In process 1 (42) and process 2 (43), processes appropriate for the positive and negative data are performed, respectively.
Execution of one instruction is completed.

Conventional data processing devices required large numbers of general purpose registers and floating point registers to facilitate programming. Furthermore, in order to realize these with a minimum amount of hardware, it was necessary to eliminate the need for individual registers and instead construct the system using memory elements.

However, as described above, the conventional data processing apparatus has the disadvantage that microprogram steps are required for data sign determination, etc., which slows down instruction execution time and increases the number of microprogram steps.

This invention was made in order to eliminate the above-mentioned drawbacks of conventional devices, and its purpose is to provide a data processing device that can speed up instruction execution and reduce the capacity of microprograms with minimal addition of hardware. That is.

FIG. 5 is a block diagram showing one embodiment of the present invention, and numerals 1 to 3 and 20 to 26 indicate the same or corresponding parts as the same reference numerals in FIG. 1 above. 2
7 is an n-bit flip-flop. Also the 6th
The figure is a flowchart of a microprogram for executing instructions of the data processing device of the present invention.
In the figure, (50) is a sign determination step, (51) is a first processing step, and (52) is a second processing step.

In the case of this device as well, the allocation of the registers in the internal memory 20 is the same as that in FIG. 2, and the data formats of the general-purpose registers and floating-point registers are also the same as in FIG. 3.

In the data processing apparatus configured as described above, instructions are sequentially read out from the main memory 1, decoded, and executed in the same manner as in the conventional data processing apparatus shown in FIG. For example, when the contents of general-purpose register 1 (see FIG. 2) are written to internal memory 20, its sign bit (15th bit in FIG. 3a) is written to internal memory 20.
When the logic of the bit corresponding to the sign bit is set to the first bit of the flip-flop 27 and the contents of the general-purpose register 2 are written to the internal memory 20, the logic of the sign bit is
It is set to the second bit of 7. In the operation of the microprogram for executing instructions, the microprogram performs a step (50) to determine the sign of the general-purpose register, and depending on the result, branches to step 1 (51) or step 2 (52). Ru. This is because the codes of general-purpose registers 1 to n are all constructed by the flip-flop 27, and instead of reading the contents of the general-purpose registers and setting the result in the status flag 25, the code is directly output from the flip-flop 27. By determining this, the branch destination address of the microprogram in the arithmetic control unit 26 can be determined. In step (51) of processing 1 and step (52) of processing 2, processing appropriate for the positive/negative data is carried out, and the execution of one instruction is completed.

As mentioned above, in the case of the microprogram example shown in Figure 6, the number of microprogram steps required from the start to the end of an instruction can be reduced to 2/3 compared to the conventional device, and the number of microprogram steps required to execute the instruction can be reduced to two thirds. The speed can be increased by 1.5 times. Furthermore, since the general-purpose registers, floating-point registers, and working registers can all be stored in internal memory, the amount of hardware can be significantly reduced compared to the case where registers are provided individually. Furthermore, since only the code portion is individually provided as a flip-flop, the increase in hardware is at most n flip-flops, making it possible to minimize the increase in hardware. Furthermore, the capacity of the microprogram for realizing the instruction function can be reduced compared to the conventional method.

In the above embodiment, a case has been described in which the sign portion of the general-purpose register is used as a flip-flop, but similar effects can be expected in the case of a floating-point register. Furthermore, a similar effect can be expected if the data stored in the working register is stored individually as a flip-flop, particularly for data that is frequently used.

By the way, in the above embodiment, the case where one word is 16 bits has been described, but the bit length of one word may be arbitrary.
It goes without saying that the word lengths of the general-purpose registers and floating-point registers are also arbitrary.

As explained above, this invention has a simple configuration in which general-purpose registers, floating-point registers, and working registers are configured by memory elements, and only the code part is configured by individual flip-flops, thereby speeding up instruction execution and reducing the size of microprograms. This has the effect of making it possible to achieve the following.

[Brief explanation of the drawing]

Fig. 1 is a block wiring diagram showing an example of a conventional data processing device, Fig. 2 is a register allocation diagram, Fig. 3 is a data format diagram, Fig. 4 is a flowchart of a microprogram of the conventional device, and Fig. 5 is a diagram. FIG. 6 is a block diagram showing one embodiment of the present invention, and is a flowchart of the microprogram of the present invention. In the figure, 1 is the main memory, 2 is the central processing unit,
20 is an internal memory, 21 is a memory address register, 22 is a memory data register, 23 is an arithmetic processing section, 25 is a status flag, 26 is an arithmetic control section, and 27 is a flip-flop. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a data processing device that sequentially executes instructions using a microprogram control method, an internal memory that stores various data necessary for executing the above instructions, writes specified data to a specified address location in this internal memory, and A means for reading data at an address position is provided corresponding to each of the specific bits in the internal memory, and when data including the specific bit is written to the internal memory, the logic of the specific bit is read out. What is claimed is: 1. A data processing device comprising: each flip-flop circuit in which a microprogram is set; and an arithmetic control section that determines a branch address of the microprogram based on the contents of each flip-flop circuit.