JPS6230500B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a laminated electrical circuit in which electrical circuits are densely packaged.

Conventionally, as a technique for high-density packaging of electric circuits, a large number of wafers are stacked, as described in Japanese Patent Application Laid-Open No. 1527-1983 or the corresponding US Patent Nos. 3705332 and 3775844. 2. Description of the Related Art A technique is known in which a large number of electrodes are provided on opposing portions of stacked wafers and these electrodes are brought into contact with each other to transmit signals between the wafers.
This method of transmitting signals by bringing electrodes into contact has a practical problem because when the number of electrodes increases, poor contact occurs in some of the electrodes. SUMMARY OF THE INVENTION An object of the present invention is to provide a laminated electric circuit that does not suffer from the conventional problem of poor contact between electrodes.

To achieve this objective, in the present invention, signals are transmitted between the electrical circuit plates using capacitances provided on opposing surfaces of the opposing electrical circuit plates. For this reason, the electric circuit flat plate according to the present invention has a plurality of capacitance electrodes on the surface facing another electric circuit flat plate, and a pair of opposing electric circuit flat plates are connected to each other through a dielectric provided between the capacitance electrodes. are laminated.

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 1 is a diagram for schematically explaining signal transmission between a pair of electric circuit plates according to the present invention.

On the wafer 10A, there is a logic circuit 2A that outputs a digital signal and a "1" from this logic circuit 2A.
Alternatively, a drive circuit 4A that receives a "0" output and supplies a pair of high and low voltages, and one electrode of a pair of capacitors 20AB and 22AB that receive a pair of outputs from the drive circuit 4A are provided.
A pair of capacitances 20 are provided on the wafer 10B, which is provided opposite to the wafer 10A.
The other electrodes of AB and 22AB, an amplifier 6B that differentially amplifies the outputs of the capacitances 20A and 22AB, a flip-flop 8B that is set by the output of the amplifier 6B, and a digital logic circuit that responds to the output of the flip-flop 8B. A circuit 2B is provided. Wafers 10A and 10B are stacked with a dielectric material provided between electrodes of capacitances 20AB and 22AB. The drive circuit 4A is
When the output of the logic circuit 2A is "0", low level and high level voltages are input to the capacitances 20AB and 22AB, respectively, and when the output of the logic circuit 2A is "1", the capacitances 20AB and 22
Input high-level and low-level voltages to AB, respectively. Amplifier 6B has a capacitance of 20AB.
When the voltage on capacitance 22AB is higher than the voltage on capacitance 22AB, a set signal is input to flip-flop 8B to set it. Conversely, when the voltage on capacitance 20AB is lower than the voltage on capacitance 22AB, a reset signal is input to flip-flop 8B to reset it. Therefore, the output of logic circuit 2A is stored in flip-flop 8B. In this way, the output of the logic circuit 2A is transmitted to the logic circuit 2B which responds to the output of the flip-flop 8B.

Transmission of signals between wafers that do not face each other is performed by the circuit connections shown in FIG. When transmitting a signal from the logic circuit 2A in the wafer 10A to the logic circuit 2B in the wafer 10B, the parts of the wafers 10A and 10B involved in signal transmission and reception are configured in the same manner as in FIG. Wafer 10 inserted between wafers 10A and 10B
C connects a pair of outputs from a drive circuit 4A in a wafer 10A to a pair of capacitances 20
Differential amplifier 6C receiving via AC, 22AC
, a flip-flop 8C which is set or reset by the output of this amplifier, and a drive circuit 4C which supplies current at a pair of high and low voltages in response to the output of this flip-flop 8C.
The amplifier 6C, flip-flop 8C, and drive circuit 4C have the same configuration as in FIG. The output of the drive circuit 4C is a pair of capacitances 20
It is transmitted to the logic circuit 2B via the amplifier 6B and flip-flop 8B in the wafer 10B via CB and 22CB.

FIG. 3 is a cross-sectional view and a plan view of a wafer used in the present invention.

The laminated electric circuit flat plate according to the present invention is constructed by laminating these wafers 10. wafer 10
is a wiring area 30 provided on the upper surface of the substrate 20.
, a wiring region 40 provided below the lower surface, and capacitance forming regions 50 and 60 provided above and below the wiring regions 30 and 40, respectively. Board 2
0 contains boron atoms as impurities at approximately 7×10 ¹⁴ /cm ³
It is a p-type silicon single crystal substrate with a thickness of approximately 100 μm and a size of 10 cm square. Logic circuits 2A and 2B (FIGS. 1 and 2) are provided under the surface of the substrate 20.
Logic circuit area 22 for forming drive circuits 4A, 4C (Figs. 1 and 2), and amplifiers 6B, 6C.
(Fig. 1, Fig. 2) and flip-flop 8
B, 8C (FIGS. 1 and 2). A capacitance electrode 5 is provided in the capacitance forming regions 50 and 60.
2 and 62 are formed, respectively. These electrodes have a rectangular shape of 450 μm square, and 40,000 electrodes are arranged on one surface with a pitch of 500 μm. Each region 22 is connected to another region 22 or region 24 or 2.
6 through wiring in the wiring area 30. Members 32 and 34 exemplarily indicate these wiring members. The wiring 32 is a wiring member that is perpendicular to the plane of the paper, and the wiring 34 is a wiring member that is parallel to the plane of the paper. The member 36 is a conductive member for shielding these wiring members 32 and 34 from the capacitance electrode 52.

The transmitting circuit region 24 and the receiving circuit region 26 are connected to a pair of capacitance electrodes 52 or 62.
Connection between the regions 24 and 26 and the capacitance electrode 52 is made via a wiring member 38. Area 24,
26 and the capacitance electrode 62 are connected through a conductive region 28 provided in the substrate 20 to establish electrical continuity between the front and back sides of the substrate 20. The region 28 is an island-shaped N-type impurity region that penetrates between the front and back of the substrate 20 and is implanted with phosphorus ions to a concentration of 10 ²⁰ /cm ³ from both sides of the substrate 20 by a known selective diffusion technique. The region 28 has a substantially cylindrical shape and is electrically isolated from the surrounding p-type substrate 20. This separation is accomplished by applying a voltage to region 28 that is approximately 5 V lower than region 28 to the p-type substrate. A circuit (not shown) for generating this voltage is provided in each wafer 10 and connected to the p-type substrate 20 via a predetermined wiring (not shown).
The top of each region 28 is connected to one of the regions 24 or 28;
It is electrically connected by a wiring member (not shown). The lower end of each region 28 is one of the capacitor electrodes 62.
It is connected to the wiring member 42 via the wiring member 42.

It is desirable that the capacitor electrodes 52, 62 are flat. Therefore, the insulating layer between the wiring members in the regions 30 and 40 is formed of a known polyimide-iso-indoroquinazolindeion resin using a known spin-on technique. Furthermore, areas 50,6
An insulator is formed around the capacitor electrodes 52 and 62 of No. 0, and these insulators are also formed using the same material and the same technique as described above. Therefore,
The upper surface of region 50 and the lower surface of region 60 are both formed flat and parallel to each other. When the wafers 10 are stacked, the capacitor electrode 52 of one wafer faces the capacitor electrode 62 on the lower surface of the wafer above, with an insulator in the regions 50 and 60 between the two capacitor electrodes interposed therebetween. The thickness of the insulator on the capacitor electrodes 52 and 62 is 7.5 μm. When the above resin is used as an insulator, the specific inductivity is about 4, so the capacitance of one capacitance between wafers is about 0.5 pF.

When a logic circuit in region 22 receives a signal from a wafer stacked above the wafer to which it belongs, that region 22 is connected to one of regions 26 and that region 26 is connected to one of the regions 26 via a conductive member 38. It is connected to a pair of capacitance electrodes 52 .
When a logic circuit in a region 22 transmits a signal to a wafer stacked above the wafer to which it belongs, that region 22 is connected to one of the regions 24, and that region 24 is connected to one of the regions 24 via a conductive member 38. and is connected to a pair of capacitance electrodes 52. In FIG. 3, one area 26 shown on the left side of the figure is connected to the capacitance electrode 52, and one area 24 shown in the center of the figure is connected to the capacitance electrode 52. .
When a logic circuit in region 22 receives a signal from a wafer stacked below the wafer to which it belongs, region 22 is connected to one of regions 26, and region 26 is connected to a pair of capacitance electrodes 62. The connection is made via the conductive region 28 described above. Further, when a logic circuit in area 22 transmits a signal to a wafer stacked below the wafer to which it belongs, that area 22 is connected to one of the areas 24, and that area 24 is connected to a pair of capacitance electrodes. 62 via conductive region 28.

By stacking multiple wafers configured in this way, the circuit connection shown in Figure 1 can be made.
Signals can be transmitted between different wafers. Further, by the circuit connection shown in FIG. 2, wafer 10A is connected to wafer 10B.
When transmitting signals via C, wafer 1
The relay transmitting circuit area 24 and receiving circuit area 26 in 0C are not connected to area 22 in the same wafer 10C, and the output of area 26 is connected to area 2.
Regions 24 and 26 are connected as input in 4.

Note that power supply or signal input/output terminals are provided around each wafer, but these are not shown for simplicity. Further, a heat sink can also be provided on the uppermost or lowermost wafer.

FIG. 5 shows another embodiment of three wafers according to the invention. Three wafers 10 shown in FIG.
Among wafers A, 10B, and 10C, wafer 10B has exactly the same structure as that shown in FIG. The wafer 10C is equivalent to the wafer shown in FIG. 3 with the wiring region 40, capacitance region 60, and conductive region 28 omitted. wafer 10
A is equivalent to wafer 10C placed upside down. Wafers 10A and 10C are
The capacitance electrodes 62 of FIG. 3 are not necessary as they are the top and bottom of the three stacked wafers illustrated. wafer 10
Taking this point into consideration, wafers A and 10C are constructed by modifying the wafer 10 having the structure shown in FIG. The signal transmission between the wafers in FIG. 5 is very similar to that in the case of using multiple layers of wafers in FIG. 3, so a description thereof will be omitted.

Further, when transmitting signals only between two wafers, only wafers 10A and 10C shown in FIG. 5 may be used. Therefore, in this case, conductive regions 28 are not required on each wafer.

In the above embodiments, a circuit is provided to compensate for manufacturing variations in capacitance between wafers. Figure 6 shows wafers 10A and 1
FIG. 6 is a diagram illustrating compensation for variations in capacitance between 0Bs. The wafer 10A includes a circuit 3 that alternately oscillates logic "1" and "0" signals with a predetermined amplitude, and a circuit 3 that generates a pair of high and low voltages in response to the output of the oscillator 3. It has a drive circuit 4C that supplies the drive circuit. The wafer 10B includes a differential amplifier 7 that receives the voltage of the pair of capacitance electrodes, and a circuit 9 that rectifies the analog output of the amplifier 7. The output of the amplifier 7, and therefore the output of the rectifier circuit 9, is approximately proportional to the capacitance between the amplifier 7 and the drive circuit 4C. Therefore, the amplifier 6B in the wafer B is configured with an amplifier with a variable amplification degree, and the amplification degree is adjusted according to the magnitude of the output of the circuit 9.
By controlling the capacitance to be small or large, the operation of the amplifier 6B can be stabilized regardless of variations in capacitance between the wafers 10A and 10B.

As described above, in the present invention, since signals are transmitted between the laminated electric flat plates via capacitance, the conventional problem of poor contact between electrodes does not occur. Therefore, between opposing wafers,
A large number of signals can be stably transmitted and received.

It should be noted that the present invention is not limited to the above embodiments, but includes modifications that can be easily made by those skilled in the art within the scope of the claims.
For example, an insulator for forming a capacitor may be formed by inserting a sheet-like material provided separately from the wafers when the wafers are stacked. An insulating layer in region 50 or 60 of FIG. 3 may be formed. Furthermore, the present invention is applicable not only to electric circuit flat plates incorporated in semiconductor single crystal substrates, but also to circuit boards using conventionally used epoxy, ceramic, etc.

In addition, in FIG. 3, areas 22, 24, 26
At least one of the wafers may be provided on the lower side of the substrate 20 on the side facing other wafers.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating signal transmission between two laminated electric circuit plates according to the present invention, and FIG. 2 is a diagram explaining signal transmission between three laminated electric circuit plates according to the present invention. FIG. 3 is a cross-sectional view of a wafer according to the present invention, FIG. 4 is a plan view of a wafer according to the present invention, FIG. 5 is a diagram showing another embodiment of the laminated electric circuit plate according to the present invention, and FIG. FIG. 3 is a circuit configuration diagram for compensating for manufacturing variations in capacitance in the laminated electric circuit flat plate according to the invention. 10, 10A, 10B, 10C...wafer, 2
0... Semiconductor single crystal substrate, 30, 40... Wiring region,
50, 60... Capacitance formation area, 22... Logic circuit area, 24... Signal transmitting circuit area, 26... Signal receiving circuit area, 28... Conductive area, 52, 62
...Capacitance electrode.

Claims (1)

[Claims] 1. Each one has a plurality of electric circuits inside,
A plurality of laminated flat circuit mounting means, and adjacent first and second circuit mounting means among the plurality of circuit mounting means.
are provided between the circuit mounting means to form a plurality of capacitances for coupling the plurality of electrical circuits in the first circuit mounting means and the plurality of electrical circuits in the second circuit mounting means. a plurality of first electrodes provided on a first surface of the first circuit mounting means opposite to the second circuit mounting means, and each of the plurality of first electrodes. a plurality of second electrodes provided on the first surface of the second circuit mounting means, respectively facing each other; and a plurality of second electrodes provided between the plurality of first electrodes and the plurality of second electrodes. 1. A laminated electrical circuit comprising: means having a dielectric material; 2. The plurality of electric circuits in the first circuit mounting means are connected to one pair of the plurality of first electrodes, and are configured to switch a predetermined pair of different voltages to the pair of first electrodes. the plurality of electrical circuits in the second circuit mounting means are connected to the pair of second electrodes facing the pair of first electrodes; 2. The laminated electric circuit according to claim 1, further comprising a second electric circuit having means for differentially detecting the voltages of the pair of second electrodes. 3. The plurality of electric circuits in the first circuit mounting means are connected to one of the plurality of first electrodes, and are configured to switch between two predetermined different voltages to one of the first electrodes. the plurality of electrical circuits in the second circuit mounting means having an input electrical circuit connected to one of the second electrodes opposite to the one of the first electrodes; 2. A laminated electrical circuit according to claim 1, further comprising an electrical circuit having a flip-flop set in response to the voltage of said one of two electrodes. 4. A laminated electrical circuit according to claim 2, wherein said second electrical circuit includes a flip-flop that is set in response to the voltage at said pair of second poles. 5 The plurality of electric circuits in the first circuit mounting means have one alternating signal generation circuit connected to the plurality of first electrodes, and the plurality of electric circuits in the second circuit mounting means have an alternating signal generation circuit connected to one of the plurality of first electrodes. The electric circuit includes an alternating signal amplitude detection circuit connected to one of the plurality of second electrodes facing the one first electrode, and a plurality of second electrodes other than the one second electrode. A plurality of amplification circuits each connected to the electrode and amplifying the voltage of the second electrode, the amplification circuit including an amplification circuit whose degree of amplification changes in response to the output of the alternating signal amplitude detection circuit. A laminated electric circuit according to claim 1, characterized in that: 6. The dielectric covers a first portion that covers the plurality of first electrodes and is integrally formed with the first circuit mounting means, and covers the plurality of second electrodes. 2. The laminated electrical circuit according to claim 1, further comprising a second portion formed integrally with said second circuit mounting means. 7. The laminated electric circuit according to claim 6, wherein the surfaces of the first and second portions are formed flat. 8. The laminated electric circuit according to claim 7, wherein the first and second portions are made of polyimide iso-indoroquinazolinedeion resin. 9. The laminated electric circuit according to claim 1, wherein the plurality of first and second electrodes are two-dimensionally arranged at predetermined pitches. 10 The first electric circuit mounting means includes a wiring member for interconnecting the plurality of electric circuits therein, and a wiring member inserted between the wiring member and the plurality of first electrodes, and the wiring member is inserted between the wiring member and the plurality of first electrodes. The laminated electric circuit according to claim 1, further comprising a conductive member for shielding from the plurality of first electrodes. 11 The plurality of electric circuits in the first circuit mounting means include a plurality of electric circuits formed near a second surface of the first circuit mounting means opposite to the first surface, and The first circuit mounting means connects an electric circuit formed near the second surface to the plurality of first electrodes from near the second surface to the first electrode. The laminated electric circuit according to claim 1, characterized in that it has an island-shaped conductive member that is electrically insulated from its surroundings. 12. Claims 1 to 10, characterized in that the first and second circuit mounting means are obtained by incorporating the plurality of electric circuits into a semiconductor single crystal flat plate using integrated circuit technology. Laminated electrical circuit according to one of the paragraphs. 13 The first and second circuit mounting means incorporate the plurality of electric circuits into a semiconductor single crystal flat plate using integrated circuit technology, and the conductive member and its surroundings have different conductivity types. 12. The laminated electric circuit according to claim 11, wherein the laminated electric circuit is made of a semiconductor material and has a bias voltage applied thereto so as to be electrically insulated from each other.