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JPS6230556B2 - - Google Patents
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JPS6230556B2 - - Google Patents

Info

Publication number
JPS6230556B2
JPS6230556B2 JP54104657A JP10465779A JPS6230556B2 JP S6230556 B2 JPS6230556 B2 JP S6230556B2 JP 54104657 A JP54104657 A JP 54104657A JP 10465779 A JP10465779 A JP 10465779A JP S6230556 B2 JPS6230556 B2 JP S6230556B2
Authority
JP
Japan
Prior art keywords
circuit
output
circuits
signal
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54104657A
Other languages
Japanese (ja)
Other versions
JPS5628587A (en
Inventor
Hirotsugu Ishikawa
Shinji Yorihiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP10465779A priority Critical patent/JPS5628587A/en
Publication of JPS5628587A publication Critical patent/JPS5628587A/en
Publication of JPS6230556B2 publication Critical patent/JPS6230556B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/45Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
    • H04Q1/453Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling in which m-out-of-n signalling frequencies are transmitted

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【発明の詳細な説明】 本発明は多周波信号検出方式に関する。[Detailed description of the invention] The present invention relates to a multifrequency signal detection method.

従来の多周波信号検出方式においては、信号と
雑音との区別および信号受信中に雑音の影響を少
なくするために、一定のレベル以上の信号が一定
時間継続することを確認するための比較回路およ
び遅延回路が用いられているため、一定レベル以
上の雑音が受信されたときにもこの雑音を正規の
信号として誤検出してしまうという欠点を有して
いる。
In conventional multi-frequency signal detection methods, in order to distinguish between signals and noise and to reduce the influence of noise during signal reception, a comparison circuit and Since a delay circuit is used, it has the disadvantage that even when noise above a certain level is received, this noise is erroneously detected as a normal signal.

本発明の目的はかかる欠点を除去するために整
流回路の次段に微分回路を設け、整流回路の出力
を微分することにより時間に対するレベルの変化
の少ない信号と時間に対するレベルの変化の大き
い雑音とを区別し、従来誤検出していた雑音が受
信されても出力が生じないようにした多周波信号
検出方式を提供することにある。
The purpose of the present invention is to eliminate such drawbacks by providing a differentiating circuit at the next stage of the rectifier circuit, and by differentiating the output of the rectifier circuit, the output of the rectifier circuit is differentiated between signals with little change in level over time and noise with large change in level over time. It is an object of the present invention to provide a multi-frequency signal detection method that distinguishes between noises and does not generate an output even if noise, which has conventionally been erroneously detected, is received.

次に図面を参照して本考案を詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第1図は本考案の一実施例を示すブロツク図
で、第2図a〜iおよび第3図a〜iは第1図の
回路の動作を説明する波形図である。
FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 a-i and 3 a-i are waveform diagrams illustrating the operation of the circuit shown in FIG. 1.

第1図において、入力端子1に与えられた多周
波信号は、多周波信号に含まれる各周波数を抽出
するための複数の波器2−1および2−2に与
えられる。各波器の出力は各整流回路3−1お
よび3−2により整流された後(第2図a,c)
および第3図a,c、比較回路4−1および4−
2および微分回路5に供給される。比較回路4−
1および4−2においては、あるレベル以上の入
力例が在つたときには出力を生じ、その出力(第
2図b,dおよび第3図b,dはAND回路6−
1および6−2に与えられる。また、比較回路の
出力信号は加算器8で加算されて(第2図eおよ
び第3図e)微分回路5に与えられる。微分回路
5においては、時間に対するレベル変動が少ない
信号(正常信号)受信時には、整流回路3−1、
および3−2の出力レベルが入力時の過度現象を
除いては一定であるので、微少な出力しか発生し
ない(第3図f)。このため、次段の比較回路7
にも入力時の過度現象を除いては論理“0”の出
力が生じないので(第3図g)、AND回路6−
1,6−2の出力を禁止しない。一方、時間に対
するレベル変動が大きい雑音時には、整流回路3
−1および3−2の入力レベルが変動し、微分回
路5に出力を生ずる(第2図f)。このため、次
段の比較回路7は、この出力がある基準レベル以
上の入力であると判断した時には論理“0”の出
力を発生し(第2図g)、この出力信号により
AND回路6−1および6−2は禁止される。
NAND回路9はAND回路6−1および6−2の
出力が同時に存在するときに出力を発生する(第
2図hおよび第3図h)。遅延回路10はNAND
回路9の出力(“0”)が一定時間継続するとき出
力端子11に出力を与える(第2図i)。なお、
第2図h,iおよび第3図iでは、入力信号が雑
音信号の場合の出力信号を示している。このた
め、NAND回路の出力は一定時間“0”が継続せ
ず、出力端子11には“1”(第2図i)が表わ
れ、入力信号を雑音信号として検出する。入力信
号が正常な信号の場合には、比較回路4−1,4
−2の出力(第3図b,dは連続した“1”にな
るとともに比較回路7の出力(第3図g)も
“1”となり、これによりNAND回路9の出力
(第3図h)は連続した“0”となる。この結
果、遅延回路10は“0”が一定時間継続するこ
とを検出し、出力端子11に信号検出を表わす信
号“0”を与える(第3図i)。
In FIG. 1, a multi-frequency signal applied to an input terminal 1 is applied to a plurality of wave generators 2-1 and 2-2 for extracting each frequency included in the multi-frequency signal. After the output of each wave generator is rectified by each rectifier circuit 3-1 and 3-2 (Fig. 2 a, c)
and Fig. 3 a, c, comparison circuits 4-1 and 4-
2 and the differentiation circuit 5. Comparison circuit 4-
1 and 4-2, when there is an input example of a certain level or higher, an output is produced, and the output (FIG. 2 b, d and FIG. 3 b, d is an AND circuit 6-
1 and 6-2. Further, the output signals of the comparator circuit are added together by an adder 8 (FIG. 2e and FIG. 3e) and are applied to a differentiating circuit 5. In the differentiator circuit 5, when receiving a signal (normal signal) with little level fluctuation over time, the rectifier circuit 3-1,
Since the output level of 3-2 and 3-2 is constant except for transient phenomena at the time of input, only a small amount of output is generated (FIG. 3f). Therefore, the next stage comparison circuit 7
Since the logic "0" output does not occur except for transient phenomena at the time of input (Fig. 3g), the AND circuit 6-
1, 6-2 output is not prohibited. On the other hand, when there is noise with large level fluctuations over time, the rectifier circuit 3
The input levels of -1 and 3-2 vary and produce an output to the differentiating circuit 5 (FIG. 2f). Therefore, when the next-stage comparison circuit 7 determines that the input is above a certain reference level, it generates a logic "0" output (Fig. 2g), and this output signal
AND circuits 6-1 and 6-2 are prohibited.
NAND circuit 9 generates an output when the outputs of AND circuits 6-1 and 6-2 are present simultaneously (FIGS. 2h and 3h). Delay circuit 10 is NAND
When the output ("0") of the circuit 9 continues for a certain period of time, an output is given to the output terminal 11 (FIG. 2i). In addition,
Figures 2h and 3i and 3i show output signals when the input signal is a noise signal. Therefore, the output of the NAND circuit does not remain "0" for a certain period of time, and "1" (FIG. 2 i) appears at the output terminal 11, and the input signal is detected as a noise signal. When the input signal is a normal signal, the comparison circuits 4-1 and 4
-2 outputs (Fig. 3 b and d become "1" continuously) and the output of the comparator circuit 7 (Fig. 3 g) also becomes "1", thereby the output of the NAND circuit 9 (Fig. 3 h) becomes a continuous "0". As a result, the delay circuit 10 detects that "0" continues for a certain period of time and provides a signal "0" representing signal detection to the output terminal 11 (FIG. 3i).

以上のように、本発明においては微分回路を用
いているため、雑音の影響を受けずに多周波信号
を検出できる。なお、微分回路を整流回路毎に設
けることも可能である。
As described above, since the present invention uses a differentiating circuit, multi-frequency signals can be detected without being affected by noise. Note that it is also possible to provide a differentiator circuit for each rectifier circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロツク図お
よび第2図a〜iは雑音受信時の第1図の回路の
動作を、第3図a〜iは正常信号受信時の第1図
の回路の動作をそれぞれ説明するための波形図で
ある。 第1図において、2−1,2−2……波器、
3−1,3−2……整流回路、8……加算回路、
4−1,4−2,7……比較回路、5……微分回
路、6−1,6−2……AND回路、10……遅
延回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 a to i show the operation of the circuit in FIG. 1 when receiving noise, and FIGS. 3 a to i show the operation of the circuit in FIG. FIG. 4 is a waveform chart for explaining the operation of each circuit. In Fig. 1, 2-1, 2-2...wave devices,
3-1, 3-2... Rectifier circuit, 8... Adder circuit,
4-1, 4-2, 7...comparison circuit, 5...differentiation circuit, 6-1, 6-2...AND circuit, 10...delay circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 複数の周波数信号を含む多周波信号の前記そ
れぞれの周波数を抽出する複数個の波器と、該
複数個の波器と1対1対応で設けられ前記各々
の波器の出力をそれぞれ整流する複数個の整流
回路と、該整流回路と1対1対応で設けられ前記
整流回路の各々の出力が一定レベルに達したとき
に出力を生ずる複数個の比較回路と、これらの比
較回路からの出力を一定時間だけ遅延する遅延回
路と、前記複数の整流回路の1つまたは2つの出
力の和を微分する微分回路とから構成され、前記
微分回路の出力の大きさに基いて前記比較回路の
各々の出力を禁止するようにしたことを特徴とす
る多周波信号検出方式。
1. A plurality of wave generators that extract the respective frequencies of a multi-frequency signal including a plurality of frequency signals, and a plurality of wave generators that are provided in one-to-one correspondence with the plurality of wave generators and rectify the outputs of the respective wave generators, respectively. A plurality of rectifier circuits, a plurality of comparator circuits that are provided in one-to-one correspondence with the rectifier circuits and generate an output when the output of each of the rectifier circuits reaches a certain level, and outputs from these comparator circuits. and a differentiation circuit that differentiates the sum of one or two outputs of the plurality of rectifier circuits, and each of the comparison circuits A multi-frequency signal detection method characterized by prohibiting the output of.
JP10465779A 1979-08-17 1979-08-17 Multifrequency signal detection system Granted JPS5628587A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10465779A JPS5628587A (en) 1979-08-17 1979-08-17 Multifrequency signal detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10465779A JPS5628587A (en) 1979-08-17 1979-08-17 Multifrequency signal detection system

Publications (2)

Publication Number Publication Date
JPS5628587A JPS5628587A (en) 1981-03-20
JPS6230556B2 true JPS6230556B2 (en) 1987-07-02

Family

ID=14386527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10465779A Granted JPS5628587A (en) 1979-08-17 1979-08-17 Multifrequency signal detection system

Country Status (1)

Country Link
JP (1) JPS5628587A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03202166A (en) * 1989-12-27 1991-09-03 Alloy Koki Kk Atomizing apparatus and painting apparatus

Also Published As

Publication number Publication date
JPS5628587A (en) 1981-03-20

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