JPS6230641B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a schedule control device, and particularly to a schedule control device that controls a load according to a preset schedule. When the time corresponding to the time of this driving pattern is reached,
The present invention relates to a schedule control device that outputs a signal to turn on or turn off a load.

[Conventional technology]

Conventional schedule control devices have mainly used devices such as microcomputers that have an arithmetic and storage function. For example, in the case of a weekly program, the schedule settings include the day of the week, the time at which the load is to be controlled, the circuit name, on/off data, etc. These settings can be made using a predetermined procedure using the keyboard, etc., as shown in Figure 1. It was done according to.

FIG. 1 shows the display state of the display device set using the keyboard, and FIG. 2 shows the driving pattern set using the keyboard.

In Figures 1 and 2, to set the operating pattern at time t ₁ in Figure 2 to circuit name No. 2 for Wednesday, the day of the week is Wednesday and the load is controlled as shown in Figure 1. Set the time as 0400, the circuit name as 2, and the on/off data on the input set using the keyboard. These set values are stored in the memory circuit of the memory section of the microcomputer, and during operation, the set values stored in the memory circuit are sequentially read out and compared with the time and day of the week of the clock circuit built into the microcomputer. It was configured to output a control signal to turn on or off to the corresponding circuit if they matched.

[Problem that the invention seeks to solve]

Since the conventional device is configured as described above, in order to set the set value using the keyboard, for example, in the operation pattern shown in _FIG .
t ₆ , and the keyboard setting operation had to be performed six times. Therefore, the number of keyboard setting operations is large, the setting operations take time, and there is a risk that erroneous settings may occur. In addition, in order to call up and confirm the set values set in the microcomputer, the setting contents of the operation pattern shown in Figure 2 are called for each command, so 24 call operations are required. Not only does it take time to confirm, but it also has the drawback that the outline of the driving pattern shown in FIG. 2 cannot be determined at a glance.

This invention was made to eliminate the drawbacks of the conventional ones as described above, and by simplifying the setting operation of the keyboard, it shortens the time of setting operation and prevents setting operation errors. It is an object of the present invention to provide a schedule control device in which a driving pattern of set values can be read at a glance.

[Means for solving problems]

The schedule control device according to the present invention has an input signal that outputs an input signal and a disconnection signal for turning on and off a load.
In synchronization with the off setting switch and the clock pulse,
By switching the input signal and output signal of the on/off setting switch, the operation pattern setting circuit sets the operation pattern, and the operation pattern set in the operation pattern setting circuit is memorized, and the operation pattern is set at the time of this operation pattern. Therefore, it is equipped with a central processing unit that generates control signals for turning on and off the load, and a switch that displays the operating pattern setting status of the operating pattern setting circuit on a display device.

[Effect]

By switching the ON signal and OFF signal of the ON/OFF setting switch in synchronization with the clock pulse, the operation pattern setting device sets the operation pattern,
This is stored in the central processing unit, the load is turned on and off according to the time of this driving pattern, and the setting status of the driving pattern is displayed on the display device by a switch.

〔Example〕

An embodiment of the schedule control device according to the present invention will be described below with reference to the drawings.

FIG. 3 shows an embodiment of the schedule control device according to the present invention, and FIG. 4 shows an embodiment of the memory circuit of FIG. 3. In FIGS. 3 and 4, a clock device 1 generates a reference signal such as a clock pulse, and divides the frequency of this signal using a frequency dividing circuit to generate hour, minute, and second signals for timekeeping. The hour, minute, and second are applied to the central processing unit 15, which will be described later. The clock display device 2 displays the current time measured by the clock device 1. The day of the week device 3 counts the daily carry signal of the clock device 1 to create the days of the week, and applies the created days of the week to the central processing unit 15, which will be described later. The day of the week display device 4 is
The day of the week created by the day of the week device 3 is displayed. The day of the week setting device 5 sets, for example, Wednesday as shown in FIG. 1, and applies the same to a central processing unit 15, which will be described later, and is constituted by, for example, a digital switch. The circuit name setting device 6 sets the circuit name No. 2 shown in FIG. 1, for example, and applies it to the central processing unit 15, which will be described later, and is composed of, for example, a digital switch. On/off setting switch 7
When connected to terminal 7a, it sets the operating pattern shown in FIG. 2 (ON), and when connected to terminal 7b, it sets the operating pattern shown in FIG. 2 to off (OFF). first inverter 8
When the ON/OFF setting switch 7 is connected to the terminal 7a, the input is at the L level, so the output is at the H level, and when the ON/OFF setting switch 7 is connected to the terminal 7b, the output is output via the resistor 9. Positive power supply (+) applied by
Because of the H level input from , an L level output is generated. In the second inverter 10, when the ON/OFF setting switch 7 is connected to the terminal 7b, the input is at L level, so the output is at H level, and when the ON/OFF setting switch 7 is connected to the terminal 7a, Due to the H level input from the positive power supply (+) applied through the resistor 11, an L level output is produced. Oscillation circuit 12
For example, a clock pulse with a predetermined period of about 0.5 to 1 second is applied to the operating pattern shown in FIG.
It oscillates in response to 23. When the push button switch 13 is closed, it energizes the oscillation circuit 12 to oscillate a clock pulse of a predetermined period. The operation pattern setting circuit 14 generates an operation pattern as shown in FIG. 2, for example, and the oscillation circuit 12
The clock pulse from
is repeatedly applied to the timing input terminal T every 23 seconds,
The H level output from the first inverter 8 is
It is applied to the set input terminal S during times 4 to 8, 11 to 13, and 15 to 18 shown in the figure, and the H level output from the second inverter 10 is applied at times 0 to 4 shown in FIG.
Reset input terminal R between 8-11, 13-15, 18-23
is applied to generate an operating pattern at the output terminal Q as shown in FIG. 2, and a specific electric circuit thereof is shown in FIG.

FIG. 4 shows one embodiment of the memory circuit 14. Fourth
In the figure, the 24-decimal counter 14a is the oscillation circuit 1
Count the clock pulses from 2, and the count value is
When it reaches 23, the count value is reset to 0 again when the next clock pulse is applied, and the count value is output in binary code. The decoder 14b decodes the binary code applied from the 24-base counter 14a using the output of the inverter 14c in synchronization with the clock pulse from the oscillation circuit 12, and corresponds to the count value 0 to 23 of the 24-base counter 14a. and output terminal Q ₀
~Q ₂₃ produces sequential output. First gate circuit 1
4d0 to 14d23 become conductive when the output of the first inverter 8 and the outputs of the output terminals _Q0 to _Q23 of the decoder 14b are both at H level, and produce an H level output. Second gate circuit 14e0-1
4e23 is a flip-flop circuit 14f0 to 14f that becomes conductive when the output of the second inverter 10 and the outputs of the output terminals _Q0 to _Q23 of the decoder 14b are both at H level, and generates an H level output.
23 is the first gate circuit 14d0 to 14d23
The H level output from the second gate circuit 14e0 to 14e23 is applied to the set input terminal S to set it, producing an H level output to the output terminal Q, and the H level output from the second gate circuit 14e0 to 14e23 is applied to the reset input terminal R to reset it. and produces an L level output at output terminal Q. The output terminals 14g0 to 14g23 are connected to each output terminal Q of the flip-flop circuits 14f0 to 14f23.

In FIG. 3, the central processing unit 15 selects Wednesday set by the day of the week setting device 5, circuit name No. 2 set by the circuit name setting device 6, and second circuit name set by the operation pattern setting circuit 14. The driving pattern shown in FIG. It includes a comparison calculation unit 152 that performs a comparison calculation to determine whether or not times t ₁ to _{t 6} of the driving pattern match with Wednesday. When connected to the first terminal 16a, the mode setting switch 16 operates the central processing unit 15, and stores the Wednesday set by the day of the week setting device 5 and the circuit set by the circuit name setting device 6 in the storage section 151. 2 and the driving pattern set in the memory circuit 14 as shown in FIG.
When connected to the second terminal 16b, the storage unit 151
The operation pattern shown in FIG. 2 stored in is displayed on the display device 18, which will be described later, and when connected to the third terminal 16c, the operation of the central processing unit 15 is stopped. When the display set button switch 17 is closed, the operation pattern status set by the operation pattern setting circuit 14, that is, the flip-flop circuit 14 is displayed.
The output status of f0 to f23 is displayed on the display device 18. The display device 18 displays the driving pattern shown in FIG. 2 set by the driving pattern setting circuit 14 and the driving pattern shown in FIG. 2 stored in the storage unit 151 of the central processing unit 15. 24 light emitting diodes are installed as display elements corresponding to times 0 to 23 shown in Figure 2, and times 4 to 18, 11 to 13, and 15 to 18 shown in Figure 2.
Lights up the light emitting diode corresponding to the time 0~
The light emitting diodes corresponding to numbers 4, 8 to 11, 13 to 15, and 18 to 23 are turned off. The relay drive circuit 19 is a comparison operation section 15 of the central processing unit 15.
If the comparison operation in 2 matches, the circuit name No. 1 to No. 8
The relays 20a to 20h are energized according to the operation pattern shown in FIG. Make-up contacts 21a-21
h is relay 20a to 20h with circuit name No. 1 to No. 8
When energized, each closes and the load (not shown) is operated according to the operating pattern shown in FIG.

Next, the operations shown in FIGS. 3 and 4 will be explained. now,
When the mode setting switch 16 is connected to the first terminal 16a, Wednesday set by the day of the week setting device 5 and circuit name No. 2 set by the circuit name setting device 6 are set.
and the second set by the operation pattern setting circuit 14.
The driving pattern shown in the figure is based on the central processing unit 1.
5 is stored in the storage unit 151.

Here, the driving pattern shown in FIG.
How it is set in the driving pattern setting circuit 14 will be explained. When the pushbutton switch 13 is closed, the oscillation circuit 12 is energized and oscillates pulses synchronized with times 0 to 23 shown in FIG. The 24-digit counter 14a counts the number of pulses from the oscillation circuit 12, and when 24 pulses are counted, the count value becomes 0.
The count value is binary encoded and output to the decoder 14b. The decoder 14b decodes the binary code input from the 24-ary counter 14a in synchronization with the pulses from the oscillation circuit 12 applied via the inverter 14c, and sequentially produces outputs at output terminals _Q0 to _Q23 . Now, if the on/off setting switch 7 is connected to the terminal 7b at time points 0 to 4 in FIG.
Since the first gate circuits 14d0 to 14d3 are in a non-conductive state and the second gate circuits 14e0 to 14e3 are in a conductive state, the flip-flop circuit 14f
The outputs of 0 to 14f3 are at L level. Next, at time points 4 to 8 in FIG. 2, when the on/off setting switch 7 is connected to the terminal 7a, the first gate circuit 1
Since flip-flop circuits 4d4 to 14d7 become conductive, the outputs of flip-flop circuits 14f4 to 14f7 become H level. Similarly, output terminal 14g0
The operating pattern shown in FIG. 2 is obtained at ~14g23.

The driving pattern thus stored in the storage section 151 of the central processing unit 15 can be displayed on the display device 18 by connecting the mode setting switch 16 to the second connection terminal 16b. The display device 18 is connected to the operation pattern setting circuit 14.
24 corresponding to the output terminals 14g0 to 14g23 of
Output terminal 14g0~
14g23, the light emitting diode corresponding to the H level output is turned on, so that the operation pattern shown in FIG. 2 can be clearly distinguished. Also, the mode setting switch 16 is connected to the first terminal 16.
When the display set button switch 17 is closed while connected to a, the driving pattern set by the driving pattern setting circuit 14 and shown in FIG. . During this time, the central processing unit 15 is operating, and the storage unit 151 is in the comparison operation unit 152.
Time t ₁ of the driving pattern shown in FIG. 2 stored in
~t ₆ and Wednesday are compared with the current time and day of the week input from the clock device 1 and the day of the week device 3. Now, when the comparison calculation unit 152 confirms that the day of the week output of the day of the week device 3 is Wednesday and that the current value output of the clock device 1 has reached time t ¹ of the operation pattern shown in FIG. 2, the relay drive circuit 19 The relay 20b with circuit name No. 2 is energized, its make contact 21b is closed, and a load (not shown) is operated. Next, when it is confirmed that the current output value of the clock device 1 has reached time t ₂ of the operation pattern shown in FIG.
De-energize No. 2 relay 20b and its make contact 2
1b is opened to stop the operation of the load (not shown). Thereafter, the load (not shown) can be sequentially operated in the same manner according to the operation pattern shown in FIG.

In the above embodiment, the time of the operation pattern shown in FIG. 2 is set to bits 0 to 23, and 1 bit is 1
Although the 24-decimal counter 14a was used to correspond to the time, in practice, the time of the driving pattern shown in FIG.
It is appropriate to use a 48-decimal counter or a 96-decimal counter.

〔Effect of the invention〕

The present invention is constructed as described above, and in order to set the operating pattern shown in FIG. 2 by associating a certain time interval with one bit, flip-flop circuits 14f0 to 14f23 corresponding to said one bit are arranged, This flip-flop circuit 14f0-1
24 base counter 14a and decoder 14b on 4f23
The flip-flop circuits 14f0 to 14f1 are set and reset while sequentially scanning, and the set region corresponds to the ON state of a load (not shown), and the reset region corresponds to the OFF state of the load (not shown).
Since the schedule control of the load (not shown) is performed while each bit of 4f23 is set and reset, the operation pattern can be set in a short time, and the display set button switch 17 can be closed to start the operation. Since the driving pattern can be set while displaying the pattern setting state on the display device 18, erroneous settings can be prevented.

As described above, according to the present invention, the driving pattern can be set in a short time and erroneous settings can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the display state of the display device set with the keyboard, FIG. 2 is a driving pattern diagram showing the driving pattern set with the keyboard, and FIG. 3 is an embodiment of the schedule control device according to the present invention. FIG. 4 is an electrical wiring diagram showing an embodiment of the memory circuit shown in FIG. 3. In the figures, the same parts in each figure are given the same symbols, 1 is a clock device, 2 is a clock display device, 3 is a day of the week device, 4 is a day of the week display device, 5 is a day of the week setting device, 6 is a circuit name setting 7 is an on/off setting switch, 12 is an oscillation circuit, 14 is an operation pattern setting circuit, 14a is a 24-digit counter, 14b is a decoder, 14d0 to 14d23 are first gate circuits,
14e0 to 14e23 are second gate circuits, 14
f0 to 14f23 are flip-flop circuits, 15
1 is a central processing unit, 151 is a storage unit, 152 is a comparison calculation unit, 16 is a mode setting switch, 16
a, 16b are first and second terminals, 17 is a display set button switch, 18 is a display device, 19 is a relay drive circuit, 20a to 20h are relays, 21a to 21
h is a make contact.

Claims (1)

[Scope of Claims] 1. An on/off setting switch that outputs an input signal for turning on and off a load, an oscillation circuit that oscillates clock pulses with a predetermined period, and a clock pulse from the oscillation circuit that counts the clock pulses,
When the count value reaches a predetermined value (n-1), the count value is reset to 0 again when the next clock pulse is applied, and n output terminals corresponding to the count value of the counter are provided. a decoder that sequentially outputs outputs to the n output terminals in accordance with the count value of , and outputs each when the input signal of the on/off setting switch and each output of the n output terminals of the decoder are applied. a first gate circuit consisting of n gates that generates an output, and n gates that generate an output when an off signal of the on/off setting switch and each output of the n output terminals of the decoder are applied. a second gate circuit comprising: a second gate circuit, which is set to produce an output when each output from the n gates of the first gate circuit is applied; It consists of a flip-flop circuit consisting of n flip-flops that is reset when the voltage is applied, an operation pattern setting circuit that sets an operation pattern, a storage section that stores the operation pattern set by the operation pattern setting circuit, and a storage section that stores the operation pattern set by the operation pattern setting circuit. a central processing unit comprising a comparison calculation unit that generates a control signal for turning on and off the load at the corresponding time according to the time of the operation pattern set, and each output of the flip-flop circuit of the operation pattern setting circuit; , a schedule control device characterized by comprising a switch for displaying on a display device.