JPS6231302B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logic analyzer that measures a plurality of logic signals, and more particularly to a logic state analyzer that displays the logic signals under test as words.

BACKGROUND ART AND PROBLEMS Digital techniques have recently become popular in the field of measuring digital and analog signals. Digital measuring instruments such as Logic Analyzers are suitable for adjusting and troubleshooting digital devices such as computers, desk calculators, computer terminals and digital control devices. Such a logic analyzer has a digital storage circuit and a preset
Since it has a counter, it is possible to memorize and measure logic signals before or after the trigger signal. Therefore, for example, it is useful to measure the logic level (high or low) and timing relationship of multiple logic signals (digital data) at various circuit points in a digital device to analyze the state of the digital device before and after an abnormality occurs. suitable. There are two types of logic analyzers, one is a logic timing analyzer and the other is a logic state analyzer. The present invention relates to this logic state analyzer.

A conventional logic state analyzer displays the state of an input logic signal on a display means such as a cathode ray tube in a binary format, that is, in the form of a table using numbers "0" and "1". In this table, each digit in the row is a binary word corresponding to each input channel of the logic signal, and the vertical row corresponds to the passage of time. Therefore, the greater the number of input channels of logic signals, the greater the number of digits in each word.

Some conventional logic state analyzers also include at least two storage circuits for storing old or reference data and new data. Both the reference and new data are displayed on the display means to compare the new data with the reference data. In this case as well, the greater the number of input channels of the logic signal, the greater the number of digits in each word of the reference data and new data.

As mentioned above, when the number of digits of words displayed on the display increases, if you want to measure each word partially, that is, only the logic signal of a specific channel, the digits of the words that are not measured, that is, "information that does not require attention," may be displayed. ”
gets in the way. Especially when the number of digits in a word is large, it becomes difficult to measure only a specific digit. Furthermore, when comparing new data with reference data, each word of the two data must be compared for each corresponding digit, making measurement even more difficult.

OBJECTS OF THE INVENTION Therefore, it is an object of the present invention to provide a logic analyzer which blanks unnecessary digits of a word displayed on a display means (vertical blanking mode) to facilitate the measurement of necessary digits. It is in.

Summary of the Invention The logic analyzer of the present invention includes a storage means for sequentially storing logic signals of a plurality of channels, a display means, and a display range of logic signals stored in the storage means in words of a desired base. and control means for blanking desired digits of the word displayed on the display means (vertical blanking mode).

Embodiments Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a block diagram of a preferred embodiment of the invention. The sixteen probe chips 10 of the probe 12 detect logic signals from the digital device under test and apply them to the data input circuit 14. Such data input circuit 14 acts as an interface between storage circuit 16 and probe 12 and compares the logic input signal to a fixed or variable threshold voltage (e.g., a DC voltage of -12 volts to plus 12 volts) to determine a predetermined level. Convert to logical signal. The 16 channel outputs of the data input circuit 14 are the memory circuit 16.
and is added to the trigger circuit 18.

The trigger circuit 18 is further supplied with a clock signal of a desired period from a time reference circuit 20, and also controls a word recognizer having a combination trigger function and the trigger position on the display (post trigger, center trigger, and pre-trigger). Contains a programmable counter to Trigger circuit 18
The output of is applied to the storage circuit 16 and the brightness control circuit 28. The memory circuit 16 includes a time reference circuit 20.
A clock signal from the control circuit 23 and a write/read command signal from the control circuit 23 are applied to the control circuit 2.
3 is controlled (command) according to the operation of the keyboard 25
Generate a signal. When a write command signal is applied to the storage circuit 16, the storage circuit 16 is applied to the time reference circuit 2.
Data input circuit 1 with a period controlled by 0
Store data from 4. The storage circuit 16 includes, for example, 16 256-bit random access memories (hereinafter referred to as RAM) and necessary control circuits. The 16 RAMs are divided into four groups, and when the format switch (not shown) is set to 16 channels, one
512 when 256 bit data is 8 channels
When the bit data consists of 4 channels, 1024 bits of data are stored for each channel.

When a read command signal is applied to storage circuit 16, parallel data is applied to vertical axis control circuit 22 from storage circuit 16 via data bus 24. The vertical axis control circuit 22 includes a multiplexer to convert parallel data to serial data in order to sequentially display the stored data on the display means. Vertical offset voltages between display channels, such as staircase voltages, are also generated in such vertical axis control circuit 22. A clock signal from the time reference circuit 20 and a read command signal from the control circuit 23 are applied to the horizontal axis circuit 26, respectively, to generate a sweep signal (slope wave or staircase wave) and a blanking signal that is applied to the brightness control circuit 28. do. The serial output from the vertical axis control circuit 22 is connected to a selection switch 32 which is selection means.
The signal is then applied via an amplifier 34 to a vertical deflection plate of a cathode ray tube (hereinafter referred to as CRT) 30 which is a display means. The sweep signal from the horizontal axis circuit 26 is applied to the horizontal deflection plate of the CRT 30 via a selection switch 36 and an amplifier 38, and the output of the brightness control circuit 28 is
Added to the CRT30 control grid. Note that the selection switches 32 and 36 may be multiplexers.

A microprocessor or microprocessing unit (hereinafter referred to as MPU) 40 receives a clock signal from time base circuit 20 and is connected to bidirectional data bus 24 and address bus 42. Furthermore, MPU40 is manufactured by Motorola.
MC6800 is also fine. A static read-only memory (hereinafter referred to as ROM) 44 stores data.
It is connected to bus 24 and address bus 42, reads control signals corresponding to address signals from address bus 42, and transmits them via data bus 24.
Add to MPU40. The MPU 40 performs various processing on data applied via the data bus 24 in response to such control signals. Statistic RAM4
6 is connected to the data bus 24 and the address bus 42, receives write/read command signals from the MPU 40, and serves as an external storage circuit for the MPU 40. MPU40, ROM44 and RAM
46 etc. constitute a microprocessor system.

Static RAM 48 is connected to data bus 24 and address bus 42, and
Control signals from MPU 40 are applied to control write and read operations. RAM48 is MPU4
Store data in RAM 16 by instruction 0,
RAMs 16 and 48 serve as storage means. Control circuit 23 is connected to data bus 24 . Cursor circuit 50 includes a preset counter and is connected to data bus 24 to control cursor position. Data bus 24 is further connected to a buffer storage circuit 52 and a character generator 54. The character generator 54 includes a memory circuit section for storing character data and a character generating section, and generates digital X and Y character signals and a Z signal. The inside of the storage circuit 52 is divided into two parts; one side stores the high bit component and is connected to the multiplexer 56, and the other side stores the low bit component and is connected to the multiplexer 58.
It is connected to the. The X and Y digital outputs and the Z (luminance) output of character generator 54 are applied to multiplexers 56 and 58 and brightness control circuit 28.
The digital outputs of multiplexers 56 and 58 are connected to digital-to-analog converters (DACs) 60 and 62, respectively, and the analog outputs of DACs 60 and 62 are applied to selection switches 32 and 36, respectively. Selection switches 32 and 36
and multiplexers 56 and 58 are the control circuit 23.
Controlled by control signals from.

Each operation mode will be explained below. First, the logical timing display mode will be explained. When the keyboard 25 is set to the timing display mode, the control circuit 23 generates a timing display command signal. The parallel data from the RAM 16 is converted to serial data by the vertical axis control circuit 22, a different offset voltage is applied to each channel and applied to the vertical deflection plate of the CRT 30, and the sweep signal from the horizontal axis circuit 26 is applied to the horizontal deflection plate of the CRT 30. Since the data is applied to the deflection plate, the data stored in the RAM 16 is displayed on the screen of the CRT 30 as shown in FIG. The waveform displayed at the top of the screen is the logic signal of channel 0, and the waveform displayed is the logic signal of channel 0.
The waveform at the bottom is the logic signal of channel 15. Since the output of the trigger circuit 18 and the output of the cursor circuit 50 are applied to the brightness control circuit 28 via the character generator 54, the bright spot area on the left side of the screen and the bright spot area in the center (the bright spots are indicated by black circles in the figure) ) indicate the trigger point and cursor, respectively. Cursors are useful for measuring timing relationships between each channel. The characters "TRIG+96" at the top left of the screen indicate that the number of bits between the trigger point and the cursor is +96, and the characters "0101 0000 0001 0100 CUR" at the bottom left of the screen indicate the logical state of the cursor position from channel 15 to channel 0. represent. These characters are processed by MPU 40 and displayed by character generator 54. Note that the cursor can be moved left and right as desired by the cursor circuit 50.

Next, the logical state display mode will be explained. When keyboard 24 is set to binary display mode, control circuit 23 generates a binary command signal. RAM1
The information stored in the character generator 54 is transferred to the RAM 48 and applied to the character generator 54 via the memory circuit section, and the digital character signal from the character generator 54 is converted into an analog signal by the DACs 60 and 62. As shown in Figure 3, the logic state is expressed in binary notation on the CRT.
Displayed on 30 screens. The characters "0101 0000 0001 0100" on the top line of the screen indicate the logical state of the word at the cursor position, that is, channels 15 to 0, and the characters "0000 0001" on the 18th line, that is, the bottom line
0100 0001” indicates the trigger word. From line 2
The characters up to the 17th line sequentially represent the 16 words after the cursor, with the right and left columns representing the logic states of channels 0 and 15, respectively.

When the keyboard 25 is set to the exclusive OR mode, ie, the comparison mode, the control circuit 23 generates a comparison command signal. This mode allows new data to be compared to old or reference data. The data initially stored in RAM16 is
The data is stored in a part of the storage area of the RAM 48, and then transferred to another storage area of the RAM 48 under the control of the keyboard 25, and this data becomes reference data.
New data is then stored in RAM 16 via probe 12 and data input circuit 14, and
The reference and new data are stored in the new data storage area of the RAM 48, and are displayed on the right and left halves of the CRT 30, respectively, in binary notation, as shown in FIG. Since MPU 40 has an exclusive OR function, it compares the reference and new data from RAM 48 and applies a brightness signal to brightness control circuit 28 via character generator 54 when the new data differs from the reference data. The output signal from the brightness control circuit 28 modulates the brightness of the display of new data different from the reference data (bold letters in the figure). The characters "TRIG-4" at the upper left indicate the number of bits between the trigger point and the cursor point of the new data, and the characters "REF TRIG+96" at the upper right indicate the number of bits between the trigger point and the cursor point of the reference data. Incidentally, the relationships between other display words and channels are the same as in the case of FIG. 3. Characters are also displayed by the MPU 40 and character generator 54.

The fourth word from the cursor word of the new data, ie, the data displayed in the left half, is the trigger word. The brightness control circuit 28 includes an oscillator for display blinking, and also receives a trigger signal from the trigger circuit 18, so that the display of the trigger word (in the figure, a character with a thick part and a thin part) blinks and other Distinguish from the display. Furthermore, the microprocessor systems 40, 44 and 46
When the trigger position information from the trigger circuit 18 is applied once, it retains such information and applies it to the brightness control circuit 28.

When keyboard 25 is set to octal display mode, control circuit 23 generates an octal command signal.
The 16 channels of logic signals stored in the RAM 16 are stored in the RAM 48, and divided into groups of 3 bits each, that is, 3 channels each, by the MPU 40.
Converts from binary to octal. Therefore, the character generator 54 generates octal characters and displays them on the CRT 30, for example, "05 0024" and "00 0501".

When keyboard 25 is set to hexadecimal display mode, control circuit 23 generates a hexadecimal command signal.
The 16 channels of logic signals stored in the RAM 16 are stored in the RAM 48, and are divided by the MPU 40 into groups of 4 bits, that is, 4 channels each.
Base system is converted to hexadecimal system. Yotsute character generator 5
4 generates a hexadecimal signal, which is displayed on the CRT 30 as, for example, "C3E6" or "AEAA".

In the octal display mode and the hexadecimal display mode, the above-mentioned comparison mode can be selected and the same operation is performed.

Next, the vertical blanking mode functionality of the logic analyzer according to the present invention will be explained. Such a mode is particularly useful in any state table display mode. When the first vertical blanking key on keyboard 25 is pressed, control circuit 23 generates a vertical blanking command signal, so MPU 40 applies a brightness control signal to brightness control circuit 28 via character generator 54. While the first vertical blanking key is pressed, the counter function of MPU40
The reference and new data in the state table on the CRT 30 are sequentially blanked out starting from the left column, and the blanking area stops changing when the key is stopped being pressed. Therefore, unnecessary vertical rows of data are stored in the state as shown in Figure 5.
can be deleted from the table (Figure 5 shows 2
(indicates the case of decimal display mode). Erased columns are ``redundant information'' in the state table reference and new data comparison and reset functions. When the second vertical row blanking key on the keyboard 25 is pressed to reproduce the erased vertical rows, the erased vertical rows are played back sequentially from the right side.
The display shown in FIG. 5 returns to the display shown in FIG. 4.
When the state table display mode is selected, the column blanking function is useful for automatically resetting the display and comparing all columns. Blocks 23, 25, 40, 44 and 6
acts as a control means.

Although the above description describes one preferred embodiment of the present invention, it will be apparent to those skilled in the art that various modifications and changes may be made thereto. For example, the input channels may be 2, 4, 8, 16, 32... and CRT
The word of the cursor displayed at 30 is binary, octal,
Any base system such as hexadecimal is acceptable. Furthermore, the display means
In addition to CRT, you can also use an X-Y plotter.

Effects of the Invention As described above, according to the logic analyzer according to the present invention,
Displays input logic signals in table form as words in the desired base, blanking desired digits of the displayed word so that specific digits of a series of words are can be easily measured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a preferred embodiment of the logic analyzer of the invention, and FIGS. 2 to 5 show displays of the display means according to the invention. In the figure, 16 and 48 are storage means, 30 is a display means, and 23, 25, 40, 44 and 46 are control means.

Claims (1)

[Claims] 1. Storage means for sequentially storing logic signals of a plurality of channels, display means, and control means for displaying the logic signals in an arbitrary display range among the logic signals stored in the storage means as words of a desired base number. and wherein the control means blanks a desired digit of the word displayed on the display means.