JPS6231387B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides high-speed and high-performance communication by directly controlling the logical connections between the communication processes of computers that constitute nodes (network constituent units) in a computer network. The present invention relates to a communication control device (hereinafter referred to as a communication control processor in this invention) that realizes data transfer.

With the spread of data communications, there is an increasing demand for transferring large amounts of data such as file information to other computers in computer networks.
Transferring data (generally in the form of packets) on a traditional computer network using packet switching involves controlling the order and flow rate of packets (also known as flow control), dividing messages into packets, recombining them, and delivering them. To execute various communication protocols (protocols) such as confirmation using software,
It requires a considerable amount of computer calculation time (hereinafter referred to as CPU time).

The increment in data transfer time that is added due to protocol execution is hereinafter referred to as protocol overhead. Because this protocol overhead intervenes in communication between communication processes (logical entities that are the targets of communication on computers), in conventional communication methods, it is difficult to configure a network using high-speed communication lines. However, the disadvantage was that large amounts of data could not be sent in a short period of time.

A rendezvous type inter-process communication method is attracting attention as a communication method that eliminates this drawback, in which synchronization between communicating communication processes is achieved using a synchronization port (a type of communication control device) and messages are transferred. Ru. In this method, the message is directly transferred from the buffer managed by the sending communication process to the buffer managed by the receiving communication process, so there is a high degree of coupling between the communication processes, and the protocol involved in message transfer is Since the processing is performed at the synchronized port, it has the advantage of less protocol overhead.

However, in order to adopt a rendezvous-type inter-process communication method to a computer network, it is necessary to handle synchronization of a very large number of processes. Processor is not realized.

The present invention aims to realize a high-performance computer network with little protocol overhead by providing a communication control processor that can instantly control the logical connection of a large number of communication processes in a rendezvous type inter-process communication system. The purpose is to explain this using the drawings below.

Figure ₁ shows an _example of the configuration of a computer network to which the communication control processor of the present invention is applied _.
..., CCP ₃ , etc. CCP is a communication control processor, N ₁ ,
N ₂ , N ₃ etc. N is the computer CPU and communication control processor
Node or node number consisting of CCP, 1a,
..., 1c, etc. 1 is a communication line, P ₁₁ , P ₁₂ , ..., P ₃₃ , etc. P is a logical (software) entity to be communicated, that is, a communication process, 2a, ..., 2d
etc. 2 is a logical communication path (hereinafter referred to as a logical link) connecting the communication processes P.

Communication in a computer network is information exchange between the communication processes P, and is generally performed by a layered communication program that executes a communication protocol (hereinafter referred to as a protocol).

In order to reduce the communication protocol overhead, the most appropriate method is to reduce the load on the computer CPU by converting the lower layer of the communication program into hardware.

The communication control processor CCP of the present invention was created based on this idea, and as shown in FIG. 1, for example, the communication control processor CCP ₁ is a computer
The logical link 2a connecting the communication process P ₁₁ on the CPU ₁ and the communication process P ₂₁ on the computer CPU ₂ , as well as the logical link 2b and the logical link 2d, are directly controlled.

Generally, the number of communication processes P handled by a computer CPU is very large, so the communication control processor CCP
requires the ability to handle many logical links 2.
Moreover, the communication process P is generated at any time on the computer CPU, and is sent to other computer CPUs at the necessary time.
Since the communication control processor CCP has the property of exchanging information with the above communication process P and disappearing, the communication control processor CCP must be able to process all logical links in parallel and multiplexed at high speed.

In other words, the communication control processor of this invention
The CCP is a conventional communication control device [one that directly accommodates the communication line 1 and performs basic functions such as serial-to-parallel conversion of transferred data and error detection of transmission codes.
It provides both the functions possessed by the physical communication medium and the communication protocol control function executed in the lower protocol layer of the communication program.

In particular, the present invention takes into consideration the case where the communication line 1 becomes faster, and provides a communication method that processes a large number of logical links 2 at high speed under microprogram control, and a communication control processor CCP that executes this method.

Figure 2 shows the communication control processor of this invention.
In the CCP configuration example, MPC is program memory PM
LM is a local memory including a work memory WM and link control tables LCT ₁ , LCT ₂ , ..., LCT _o , 8 is a calculation register of the calculation unit ALU, and 9 is a work memory including a calculation unit ALU. Link access table in memory WM, CHX is channel interface section including channel register 7, LIA is line interface adapter including line buffer 10, TM is timer control section, DTU is data transfer section , 3 is a computer input/output interface, 6
is an input/output handler.

In order for the communication control processor CCP to directly handle the logical link 2, it establishes a communication protocol (protocol) that can be executed independently for each logical link 2 between it and other communication control processors CCP connected via the communication line 1. is executed at high speed by the microprogram control unit MPC.

The following communication sequences are defined for the logical links 2, and the microprogram control unit MPC controls them so that they have completely independent meanings for each logical link 2. FIG. 3 shows the basic operations of the link establishment phase, FIG. 4 the data transfer phase, and FIG. 5 the link termination phase. computer CPU
The command output from the communication control processor CCP to the communication control processor CCP is called an order, or the command passed between the communication control processors CCP is called a link command.

Orders include:

・CONNECT LINK Link establishment request ・ SENSE attention interrupt (ATTEN.INT) sense ・CONNECT ACCEPT Acceptance of link establishment request ・WRITE message write instruction ・READ message read instruction ・DISCONNECT LINK Link termination request ・ DISCONNECT ACCEPT Acceptance of link termination request Link commands include:

- CL link connection instruction - STS status information notification - CA link connection acceptance notification - WT message reception instruction - RD message transmission instruction - Start of INF message - End of FIN message In addition to the above orders and link commands, computer
The signals exchanged between the CPU and the communication control processor CCP include the following:

- C.DATA Control data - CSW Channel status word Communication control processor There are two types of frame formats transferred between CCPs, as shown in Figure 6.
4 is a control frame that conveys a link control message, and 5 is a message frame. In the figure, C is the command field to insert the above link command, DA is the called address, LND is the called link number, SA is the calling address, LNS is the calling link number, XC is the command extension field, ST
is the status field, LH is the transfer data length display field, TM is the timer field, I
is the field that carries C.DATA, FCS is the frame check sequence, and MSG is the message.

Also, Figure 7 shows input/output handler 6 of the computer CPU.
Channel control word CCW passed from to channel register 7 of channel interface section CHX
Indicates the format, ORD is the order, LN is the link number, FLAG is the flag to write channel program control information, TM is the order timer, DBFADR
is the data buffer address, and BYCNT is the byte count of valid data in the data buffer.

Furthermore, FIG. 8 shows a channel status word CSW used to notify the computer CPU program of interrupt information detected by the communication control processor CCP or corresponding to the channel control word CCW.
PS is the primary status, LN is the link number, SS is the secondary status, and CCWADR is the CCW indicating the first address of the channel status word CCW.
The address, BYCNT, is the byte count.

The operation of the present invention will be specifically explained in accordance with the communication sequences (FIGS. 3, 4, and 5) using FIGS. 1 to 8. Here, attention will be paid to the logical link 2a connecting the communication processes _P11 and _P21 in FIG.

(i) Link establishment phase When the communication process _P11 is activated and transmits an instruction to start message transfer to the input/output handler 6 on the computer CPU ₁ , the input/output handler 6 has a link establishment request CONNECT LINK order in the order ORD. Channel control word CCW (7th
) is created and passed to the channel register 7 of the channel interface section CHX using a method known as a channel programming method.

The channel control word CCW stored in channel register 7 is used by the microprogram control unit.
When the MPC executes a register move instruction, it is moved to the arithmetic register 8 in the arithmetic control unit ALU. Next, the arithmetic control unit ALU is ordered.
Decipher the contents of ORD. In this case (CONNECT LINK order), the microprogram control unit MPC performs random access
Local memory consisting of memory RAM
The link access table 9 in the work memory WM in the LM is checked and the number i (i=1, . . . , an arbitrary number of n) of an unused link control table LCT is extracted. For example, the link access table 9 is provided at a specific address of the work memory WM, and its bit position is made to correspond to the number of the link control table LCT, and logic "1" is defined as being used and "0" is defined as not being used. It is better to do so. This operation is indicated as "LCTi allocation" in the link establishment phase diagram of FIG.
When the link control table LCTi is allocated for a CONNECT LINK order, the corresponding bit in the link access table 9 is set to logic "1" to prevent double allocation.

The link establishment request information requested by the communication process P ₁₁ is stored in the data buffer (not shown) starting from the address on the main memory indicated by the data buffer address DBFADR of the channel control word CCW by the length of the byte count BYCNT. There is.

The microprogram control unit MPC links the control data C.DATA from the above data buffer to the control table by executing the microprogram in the program memory PM consisting of read-only memory ROM.
Import into LCTi.

Control data C.DATA contains communication process P ₁₁
The peer communication process P ₂₁ requests link establishment.
contains the node number N ₂ where the message exists and additional information to be passed to the software of the computer CPU ₂ on the destination side in order to control link establishment.

The microprogram control unit MPC creates a control frame 4 from the various information mentioned above, and sends it to the communication line 1a from the line interface adapter LIA. At this time, in control frame 4, command field C contains link
Command CL, incoming address DA is incoming node number N ₂ , outgoing address SA is outgoing node number
N ₁ , the originating link number LNS is the number i of the link control table LCT, the transfer data length display field LH is the byte length of the frame, the timer field TM is the order timer value TM of the channel control word CCW, and the information field The content of the control data C.DATA is placed in I, and the status of the communication control processor CCP ₁ is placed in the status field ST. In this control frame 4, the incoming link number LND has no meaning yet.

The control frame 4 with the link command CL is sent to the line interface adapter LIA of the communication control processor CCP ₂ on the receiving side.
received by buffer 10 and line interface adapter LIA enters command field C.
is identified, and the microprogram control unit MPC is started to process.

This activation causes the microprogram control unit to
The arithmetic unit ALU of the MPC is similar to the communication control processor CCP ₁ on the transmission side described above.
Refer to the link access table 9 in the work memory WM to acquire unused link control table LCT j (j = any number of 1, ..., n), and store the previously received control frame there. 4, originating address SA, originating link number LNS (in this case, link control table LCT number i)
Store etc. This operation is written as "LCTj allocation" in the link establishment sequence diagram of FIG.

The microprogram control unit MPC creates a control frame 4 having the link command STS in the command field C as a response to the link command CL of the previous control frame 4, and sends it back to the communication control processor CCP ₁ . At this time, the incoming address DA has the node number N ₁ and the incoming link number.
LND contains link control table LCT number i,
The originating address SA contains the node number N ₂ , the originating link number LNS contains the number j of the link control table LCT, and the extended command field XC contains the response to the previously received link command LC (generally the acceptance of control frame 4). ), the status field ST contains the status of the communication control processor CCP ₂ , such as the response reason, etc.
Finally, a frame check sequence FCS is added to check the transmission error of control frame 4 and transmitted.

On the other hand, the microprogram control unit MPC of the communication control processor CCP ₂ assigns the number j of the link control table LCT assigned above to the link number LN of the channel status word CSW in FIG. 8, indicating the attention interrupt and its cause. Set the flag to primary status PS (or secondary
status SS) and send it to the computer CPU ₂ via the channel interface CHX.
CSW stack of main memory (not shown)
Store in area and attention interrupt ATTEN.
Multiply by INT.

By starting this interrupt ATTEN.INT, the computer
The program of CPU ₂ (generally an interrupt processing routine) examines the channel status word CSW in the CSW stack area, and the program recognizes the number j of the link control table LCT corresponding to this interrupt. Next, the input/output handler 6 sends the order SENSE to the order of the channel control word CCW.
Enter the number j of the link control table LCT in the link number LN in ORD, and send it to the channel interface section CHX. The microprogram control unit MPC uses the high-speed table access method described later to convert the contents of the link control table LCTj, that is, the control data C.DATA, to the data buffer address of the channel control word CCW.
The number of words indicated by the byte count BYCNT is transferred from the main memory address indicated by DBFADR.

The above control data C.DATA is sent to the communication process P from the internal processing of the computer CPU ₂ program.
(P ₂₁ , ..., P ₂₃ ) (hereinafter referred to as the communication process management program).

Communication process management program controls data
By checking C.DATA, the communication process P ₂₁ to establish a link with the communication process P ₁₁ of the computer CPU ₁ is activated. Communication process P ₂₁ is an acceptance order of a link establishment request CONNECT
ACCEPT and link control table LCT number j
The communication control processor (strictly speaking, via input/output handler 6)
Pass to CCP ₂ . Link number LN in microprogram control section MPC of communication control processor CCP ₂
The link control table LCTj is found from the contents j of the link control table LCTj by high-speed table access, and the link command CA (link connection acceptance notification) is entered in the command field C and the incoming address DA is entered in the link control table LCTj by microprogram processing. The node number N ₁ that was
Incoming link number LND contains link control table
Create a control frame 4 in which the LCT number i is written and send it to the communication control processor as shown in Figure 3.
Send to CCP ₁ .

The communication control processor CCP ₁ uses the content i of the destination link number LND of the control frame 4 to find the link control table LCTi in the local memory LM by a high-speed table access method as described later, and executes the link control table LCTi in the local memory LM. The calculation register 8 of the internal calculation unit ALU is loaded. Based on this content, the microprogram control unit MPC sets the link control table LCT number i to the link number LN and the link command CA to the status (PS or SS).
Creates a channel status word CSW written in , and reports completion to the order CONNECT LINK that was previously issued to communication control processor CCP ₁ . This completion report allows communication process
P ₁₁ learns that the logical link 2a connecting the other process P ₂₁ has been established.

What should be noted here is that in _the present invention, logical link 2 on the computer network shown in _FIG .
is defined as the combination of node numbers N ₁ and N ₂ (N ₁ i, N ₂ j), and this combination is defined by the communication control processor
_This is recognized in the link establishment phase in CCP ₁ and CCP _{2 ,} but the communication processes P ₁₁ and P ₂₁ of the computer CPUs receive the link control table LCT number ( It is sufficient to recognize only i and j), respectively.

In the subsequent communication sequences (data transfer phase and link termination phase), the communication process
P ₁₁ uses the number i of the link control table LCT as the link number i of the logical link 2a, and the communication process P ₂₁ similarly uses the number j as the link number j of the logical link 2a.

(ii) Data Transfer Phase Once the logical link 2a between communication processes P ₁₁ and P ₂₁ is established, data transfer is performed in the following steps.

The communication process P ₁₁ of the computer CPU ₁ prepares the transmission data in a transmission data buffer (not shown), sends the message write instruction WRITE to the order ORD of the channel control word CCW, and sets the logical link number i to the link number LN. Fill in the information and activate communication control processor CCP ₁ for transmission. This transmission is started in the same way as above, and the link control table
Stored in LCTi.

The communication process P ₂₁ of the computer CPU ₂ prepares a reception buffer (not shown) and sends the message read instruction READ to the order of the channel control word CCW.
Enter the logical link number j in the link number LN in ORD, and activate the communication control processor CCP ₂ for reception. In the communication control processor CCP ₂ , when the link control table LCTj is loaded into the calculation register 8 of the calculation unit ALU of the microprogram control unit MPC according to the logical link number j, the destination node stored in the link control table LCTj is loaded. Necessary information such as the number N ₁ , the logical link number i seen from the communication control processor P ₁₁ , the originating node number N ₂ , the logical link number j, and the byte count length BYCNT of the receiving buffer is entered in the control frame 4 in FIG. and sends it to communication control processor CCP ₁ .

The communication control processor CCP ₁ that received the control frame 4 creates a link control table based on the logical link number i in the incoming link number LND.
Load the contents of LCTi into calculation register 8,
It is verified that the contents j of the originating address SA and the originating link number LNS match the values stored in this link control table LCTj in the link establishment phase (FIG. 3). Furthermore, it is confirmed that the WRITE order and READ order (this corresponds to the link command RD) of both communication processes P ₁₁ and P ₂₁ are matched (see FIG. 4).

Establishment of this matching on the communication control processor CCP ₁ means that preparations have been made to transfer data from the communication process P ₁₁ to the communication process P ₂₁ , that is, a rendezvous between the processes has been established.

Communication control processor CCP ₁ notifies communication control processor CCP ₂ of a message reception instruction using link command WT, and then
Command extension field XC and link command indicating ready to receive from CCP ₂
When control frame 4 with SUS is received, the computer sets the contents of data buffer address DBFADR of channel control word CCW as the first address.
A message of the length indicated by the byte count BYCNT is retrieved from the main memory of the CPU ₁ , inserted into the message field MSG in the format of the message frame 5 shown in FIG. 6, and sent to the communication control processor CCP ₂ . At this time, the message to be sent is divided into appropriate lengths, the link command INF is written in the command field C of message frame 5, and the link command FIN is written in the command field C of the last message frame 5. Fill out. In the communication control processor CCP ₂ on the receiving side, the received message is sent to the line interface adapter.
The main memory location indicated by the channel control word CCW containing the previously issued READ order is transferred via the LIA → data transfer unit DTU → channel interface adapter CHX, under the control of the microprogram control unit MPC. will be transferred to.

In the communication control processor CCP ₂ , events that occur during message reception are stored in the link control table LCTj, so the results are stored in the channel control word with READ order.
Corresponding to CCW, the channel status word CSW is filled in and reported to computer CPU ₂ . On the other hand, the communication control processor uses the control frame 4 having the link command STS in the command field C.
CCP ₁ is notified, which is also passed to computer CPU ₁ by channel status word CSW corresponding to channel control word CCW with WRITE order.

Even after one data transfer is completed, the logical link 2
Since a is maintained by both link control tables LCTi and LCTj, both communication processes
Message exchange can be continued between P ₁₁ and P ₂₁ at will.

(iii) Link termination phase When the message exchange is completed, the communication process _P11 executes the input/output handler 6 as shown in FIG.
A link termination request DISCONNECT LJNK order is output to the communication control processor CCP ₁ via the control frame 4 containing the link command DL, and this is transmitted to the communication process P ₂₁ of the other party by the attention interrupt ATTEN.INT.

In response, the communication process P ₂₁ outputs an acceptance of a link termination request DISCONNECT ACCEPT, which is passed to the communication control processor CCP ₁ by means of a control frame 4 with a link command DA.

In the microprogram control unit MPC of the communication control processor CCP ₁ , the primary status of the channel status word CSW corresponding to the channel control word CCW with the above DISCONNECT order is
A flag indicating that the link command DA has been accepted is set in the PS, and the flag is reported to the communication process _P11 of the computer CPU ₁ .

Also, in response to the link command DA, the communication control processor CCP ₁ issues a link command.
Send command STS to communication line 1, release link control table LCTi assigned to communication process P ₁₁ in the link establishment phase (Figure 3), and perform link access in work memory WM corresponding to this link control table LCTi.・Table 9
The relevant bit position i of the bit is returned to unused (logic "0").

Similarly, in the communication control processor CCP ₂ that received the link command STS,
Channel status word corresponding to channel control word CCW with order DISCONNECT ACCEPT
The CSW notifies the communication process P ₂₁ of the computer CPU ₂ that the link has been terminated, and also releases the link control table LCTj.

In the communication control processor CCP of the present invention, the link control table LCT plays an important role in executing the communication sequence between the communication processes P, and is referenced very frequently. For example, after establishing a link (Figure 3), executing data transfer (Figure 4) n times, and terminating the link (Figure 5), the link control table LCT is set to 2 logical links after link allocation and before link release. at least (4n+5) every
Executed times. Moreover, in the communication control processor CCP of this invention, multiple (in principle, quite a large number)
The logical links 2 are established independently, and each logical link 2 is controlled to operate completely independently. Therefore, when the data transfer traffic increases, the frequency of accessing the link control table LCT increases considerably, and the microprogram The load on the control unit MPC tends to increase.

Therefore, the present invention has means for rapidly accessing the link control table LCT corresponding to the channel control word CCW and the received control frame from among the plurality of link control tables LCT using the method shown in FIG.

Figure 9 shows the mechanism for accessing the link control table LCT, where PREG is the program memory
PM output registers, AC1, AC2, M, N, etc. are microprogram fields AC1, AC2
is an address constant field, M, N are selection constants,
LMA is the access counter of local memory LM, A ₀ ,..., A ₁₁ is the address of local memory LM, SEL is the selector gate, G1, G2, G
3 is a gate, and T is a clock.

When a link control message is received by the control frame 4 from the communication line 1 to the line buffer 10 of the line interface adapter LIA and the microprogram control unit MPC is activated, the field AC shown in FIG. 9 is sent from the program memory PM.
A microprogram including 1, M, AC2, and N is output to the output register PREG. Incoming link number LND in line buffer 10 (communication control processor CCP ₁ in the link establishment phase in Figure 3)
i in CCP 2, j in CCP ₂ ), gate G1 opens depending on the value of selection constant M, and local memory access is performed.
It is set at the upper level of counter LMA. At this time,
Address constant field AC2 by selection constant N
If you specify the incoming link number LND as the upper address A ₅ , ..., A ₁₁ of local memory LM
However, the value of the address constant field AC2 is also specified as the lower address A ₀ , . . . , A ₄ . At this time, if you allocate a local memory address so that the start address of a certain link control table (for example, LCTi) matches the incoming link number LND, the link control table specified by the incoming link number LND
The memory contents at the location specified by the address constant field AC2 in LCTi can be loaded into the arithmetic register 8 of the arithmetic unit ALU.

Similarly, when selecting the link control table LCT corresponding to the link number LN in the channel control word CCW output from the computer input/output interface 3, the gate G2 is opened by the selection constant M, and the microprogram itself LCT
When selecting, it is sufficient to open gate G3.

In this way, the contents of the incoming link number LND in the control frame 4 received from the communication line 1 and the channel control word output from the computer input/output channel 3
Depending on the contents of the CCW link number LN, the local
Directly specify the upper address A ₅ ,..., A ₁₁ of memory LM, and use the output of program memory PM (address constant field AC2) to write to local memory.
By directly specifying the lower addresses A ₀ , ..., A ₄ of the LM, the microprogram can load the contents of the link control table LCT in the local memory LM into the arithmetic register 8 with one instruction. The operating efficiency of CCP can be increased.

Note that although the computer networks connected via communication lines have been described above, in this invention, the means for connecting the communication control processors to each other is completely arbitrary, and the line can be selected depending on the means.・Interface adapter LIA
It is also possible to configure the frame format, etc. to be transferred.

Furthermore, the communication process is nothing more than the entity of communication in the computer network software to which the present invention is applied, and can be arbitrarily defined, for example, as a task, an aggregate thereof, or a communication program that handles an aggregate.

As described above, in order to directly process the logical communication links between the plurality of communication processes defined on the software of the computers constituting the network, the communication control processor according to the present invention has the following steps: (1) for each logical link; (2) in the logical link establishment phase, in response to a link establishment request, the unused link access table in the local memory LM is means for allocating the link control table LCT; (3) means for recognizing the number of the allocated link control table LCT as a link number in mutual communication control processors; and (4) means for recognizing the number of the allocated link control table LCT as the link number. means for notifying the communication process using a channel status word so that the communication process can transfer data to the corresponding communication process on the receiving side by simply specifying the link number; (5) link control; means for loading the contents of a corresponding link control table LCT in a local memory LM into an arithmetic register using this link number as an address by inserting a link number of a called side into a control frame carrying a message and transmitting the message; (6) Since it has means for releasing the link control table in response to a link termination request from the communication process, logical links between multiple communication processes can be processed independently and directly, and the communication protocol - It has the effect of configuring a computer network capable of high-performance data communication suitable for high-speed transfer of large amounts of data with little overhead.

[Brief explanation of the drawing]

FIG. 1 is a configuration example diagram of a computer network to which the communication control processor of the present invention is applied, FIG. 2 is a configuration diagram of the communication control processor, and FIGS. 3 shows the link establishment phase, FIG. 4 shows the data transfer phase, FIG. 5 shows the link termination phase, FIG. 6 shows the transfer frame format, and FIG. The figure shows the channel control word CCW
FIG. 8 is a diagram showing the channel status word CSW, and FIG. 9 is a diagram showing a mechanism for accessing the link control table. In the figure, CPU is a computer, CCP is a communication control processor, N is a node or node number, 1 is a communication line, 2 is a logical link connecting communication process P, LM
is a local memory having a link control table LCT and a work memory WM including a link access table 9, MPC is a microprogram control section, ALU is an arithmetic unit, 8 is an arithmetic register, and CHX is a channel register 7. Channel interface unit, LIA is line interface adapter including line buffer 10, DTU is data transfer unit, 4 is control frame,
5 is the message frame, LMA is the local
The memory access counter, PREG, is the output register of the program memory PM. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

Claims (1)

[Scope of Claims] 1. In a communication control processor that configures a computer network by interconnecting computers having a plurality of communication processes or programs through a coupling medium such as a communication line, the communication control processor is connected to a computer channel interface. A data transfer unit that connects the ace unit and the line interface adapter coupled to the coupling medium, a link control table allocated in correspondence with a logical link that is a logical communication path of the communication process, and the link control. It consists of a local memory having a link access table that indicates the usage status of the table, and a microprogram control unit that executes the communication rules for the logical link, and also controls the communication rules that are executed by the microprogram control unit. (i) In the link establishment phase, based on a link establishment request from any communication process, the communication control processor performs the following steps: - Allocate an arbitrary number i (arbitrary number j in the communication control processor at the other end of the logical link) of an unused link control table by referring to the access table, and assign this number i (or number j)
as the link number i (or link number j), and notify the computer where the communication process exists, and send the link number i (or link number j) to the communication control processor at the other end via a link control message. (ii) in the data transfer phase, a message sending request from one of the communication processes connected by the logical link and a message sending request from the other communication process; means for the microprogram control unit to detect matching of message reception requests by referring to the link control table, and to transfer the message after this detection; (iii) in the link termination phase, the communication process (iv) means for releasing the link control tables i and j allocated to the logical link in the link establishment phase based on a link termination request from; and (iv) the link number i (or link number j) of each other. means for inserting and forwarding the link number j (or link number i) corresponding to the communication process of the other party into the link control message exchanged after recognizing the communication process; (v) the means of (iv) above; , the link number i (or link number j) in the received link control message is used as the local address.
means for reading the contents of the link control table i (or link control table j) in memory, and the communication process specifies the link number for communication between the communication processes of the computer network. By doing so, data is transferred to the corresponding communication process via any logical communication path, and communication rules are executed independently and in parallel for these logical communication paths. communication control processor.