JPS6231440B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD This invention relates generally to logic circuits, and more particularly to logic circuits for use with apparatus for testing the functionality of a memory to generate any one of a plurality of address sequences. BACKGROUND OF THE INVENTION When large scale integrated circuit memories are installed in data processing devices and are tasked with performing certain sequences of memory functions, it is known that the memories experience intermittent malfunctions. Because this failure is application sensitive, typical memory defect modes have been studied to guide the design of test protocols that can be used economically on manufacturing lines. One such study is the IEEE
Transactions on Manufacturing Technology;
Reported in the paper “Selecting Test Patterns for 4K Rams” by Wayne E. Sohl, published on page 51 of Vol.MFT-6, No.3, September 1977. . As discussed in this paper, very large scale integration (VLSI) circuit memories are susceptible to the various defect modes described in the table, and these defect modes are subject to various failure modes designed to test for defects. Correlated with test protocols. Some of these protocols detect one or more defects. The relative magnitude of the test time for each of the test protocols is such that the test time factor is 2.
It is stated by the ratio compared to the longest test which is (2N ² +N). where N is the number of test cells. For 4K memory, the paper calculates the number of test iterations to be 67117056 cycle points. It will be readily appreciated that the number of cycle points required to test a large memory (eg, 16K memory) can be very large (1.17×10 ¹⁹ ). If the test frequency is too slow, the test time becomes prohibitively long for 100% production testing. Therefore, the test protocol must be chosen to use the minimum number of cycle points to detect potential defects;
Also, the frequency of the test equipment must be as high as possible. Apparatus for memory testing according to the protocol discussed in the above publication was published on August 7, 1973.
U.S. Patent No. granted to Thomas William Hart
Described in No. 3751649. The device is primarily controlled by a built-in program that provides great flexibility for adapting to various memory configurations and test protocols. However, as memory becomes larger,
The demand for storage capacity in memory becomes prohibitive to the point that it precludes the use of microprocessors and small computers. Additionally, the use of memory for storing instructions that must be accessed frequently and repeatedly reduces the effective frequency of the device and lengthens test times to an extent that is highly unacceptable for manufacturing purposes. Until now, the generation of address sequences was one of the key areas that needed to be accessed frequently and repeatedly to determine which cell in memory should be addressed next for testing. It is one.
However, examination of the address sequences of various protocols has revealed that the sequences follow a fixed arithmetic progression. That is, although the sequence differs between different test protocols, within one protocol it follows an arithmetic progression that follows a set rule. This suggests the use of a combination of logic elements that can be preconditioned to generate the required address sequence with minimal input and control from the memory of the controlling computer. OBJECTS OF THE INVENTION In order to accomplish the foregoing needs, the present invention provides a timing system for generating a desired numerical sequence to control the addressing of a memory that is preconditioned with predetermined data and under test. - Aims to provide a combination of digital logic circuits that act in response to patterns of pulses. Another object of the invention is to provide an address generator having a plurality of identical combinations of logic means for selectively generating address sequences to the entire matrix or to any selected region. SUMMARY OF THE INVENTION The present invention, in summary, provides a method for generating a preselected address sequence as a function of variable timing impulses and a pregiven constant to indicate a memory element to be tested of a matrix memory. a memory address sequence generator consisting of a combination of logic elements interconnected with first and second X and Y address generators;
control means controlled for selecting the first or second of the pair of X and Y addresses, each of the address generators generating a preselected sequence having an increasing or decreasing order; It is also controlled such that increments within the sequence can be set, masking can be set, and displacements from a fixed reference origin can be set. In the following, we define some terms and examine the mathematical rules governing the creation of desired address sequences before describing embodiments of the invention. The memory specifically used for testing purposes in the device of the invention is a two-dimensional matrix memory. Thus, each cell or memory location can be defined by a matrix of location coordinates. The size of the memory matrix is typically 2 ⁿ ×2 ^m . Here, n and m are integers. In this dimension, the X and Y addresses are 2 ⁿ −
It may conveniently be encoded with 1 and 2 ^m -1 binary bits. The address of a cell in a row of a matrix is 0
to 2 ⁿ -1, and the addresses of the cells within the column run from 0 to 2 ^m -1. Therefore, normally 2K,
Memory called 4K, 16K, etc. is actually different from each other.
Contains 2 ¹¹ , 2 ¹² and 2 ¹⁴ cells. These may be organized into square or rectangular matrices as long as both dimensions are integer powers of two. The fact that the memory geometry and matrix dimensions are limited to integer powers of 2 means that combinations of simple binary-valued logic elements can be used to create any desired sequence of memory addresses. It is convenient in many ways. These addresses may be increased or decreased by a desired fixed amount. These may be masked to prevent addresses from exceeding a predetermined value. The sequence of values may also be repeated up to the value of the mask, if desired. To direct the test to a memory area displaced from the origin by a constant value, the address may be offset by adding the constant value to the sequence of base addresses. The test may also be controlled by alternating between cells following one sequence and cells following a second sequence. [Decrementing] To decrease a sequence of increasing binary values, use the logical EXCLUSIVE of an all-one binary digit and each binary bit in the increasing sequence of binary values.
You simply need to take the OR. This reduces the value of the resulting series of binary digits. For example, a sequence of increasing numbers, 000 (0); 001 (1); 010
(2);……111(7) is the binary number 111 of all 1s
Sequence of numbers decreasing by taking EXCLUSIVE OR, 111(7); 110(6); 101(5); ......000
(0) occurs. If this is extrapolated to the full capacity (16 bits), the reduced address is 16
Starting from the maximum value of bits, it is decremented. However, due to the binary nature of the values, binary values obtained beyond the maximum address of memory tested during the decreasing sequence can be invalidated by masking. Masking: Masking uses a logical AND function to combine each binary bit of the desired address with the binary bit representing the binary address beyond which further addressing is to be blocked. It means that. For example, if you wish to limit addresses to no greater than 111(7), 000
Addresses from to 111 will be replicated unchanged. However, the next count 1000 is 0111
If the AND condition is taken bit by bit, the resulting address will be 000, and the sequence from 000 to 111 will be repeated for all binary values greater than 1000. [Home and Away Addresses] The next relationship used is Home and Away Addresses.
It's called an address. This is one memory
It allows a test sequence in which a cell (home cell) is repeatedly interrogated with a succession of away cells. after that,
The home cell advances to a new cell and is tested alternately with a new series of away cells. Both the home and away cell sequences may be either increasing or decreasing sequences varied by any integer amount. If the home cell is in the middle of the array, a series of away cells will sometimes contain a cell address larger than the memory capacity. By masking the away cell, the address increases to a maximum value, returns to zero, and approaches the home cell with an increasing succession of smaller addresses. For example, if 64
If we have a linear array of cells and the home cell has an address of 31, the away cell sequence runs from 32 to 63 and then from 0 to 30. Masking at 64 prevents accessing non-existent cells and returns the sequence to zero. [Offset] The last relationship is offset. This allows a series of relatively identical cells to be tested in any desired region of memory by adding constants to the X and Y addresses. The constants are the X and Y displacements of the region being tested relative to the origin of the memory matrix (X=0, Y=0). Offset also allows for alternating testing of series of cells occupying relatively similar geometric locations in two different regions of the memory. This is commonly used to test sense amplifiers that are shared by multiple memory cells. DESCRIPTION OF THE EMBODIMENTS The particular test protocol chosen for any given memory depends on the size and geometry of the memory, including the potential defects sought to be detected and the nature of the sense amplifiers. Described in terms of measurable shapes. The address generator that will be described will change the address by presetting it with the necessary parameters by constants, whether it is actually positive or negative (increase/decrease), and the starting point (basic address) for the numerical sequence. change the
Vary the selection of areas to be tested. This affects each of the X and Y addresses individually. The relative times at which addresses are changed are controlled by an external cycle counter that is also preset for the desired test. FIG. 1 shows four identical address generators A, B,
C and D are shown schematically. Each address generator has a configuration consistent with the logical element arrangement shown in FIG. Inputs to A, B, C and D units are multi-wire cables 90A,
90B, 90C and 90D, the individual wires or multi-bit cables that make up these are shown in detail in FIG. All of the logic units used in FIG. 2 are standard commercially available components, and in the preferred embodiment are obtained from Texas Instruments, Inc. Each unit is
It is illustrated by the symbol T1 plus its type number. Of course, other companies' products with the same functions may be substituted. The A and B units are first address generating means used to generate the X address, and the C and D units are the second address generating means used to generate the Y address. A and C units are one pair of address generating means for generating home addresses, and B and D units are another pair of address generating means for generating away addresses. Selection of the home or away address is carried out by the unit 50 as selection means under the control of a suitably timed potential on line 55.
(for X) and unit 60 (for Y)
controlled by the selection of Each selection unit 50 or 60 is a solid state device equivalent to a 16 pole double throw relay with the ability to select 16 bits of the home or away address in the X and Y directions. It will be intuitively appreciated that this ability allows any cell in the memory to be accessed in the desired sequence by providing the appropriate preset data and timing pulses. Units 61, 62, 63 and 64 in Figure 2
consists of four 4-bit buffer storage units that, when strobed with appropriate timing pulses, are capable of accepting and storing all 16-bit binary data.
and generates the corresponding synthesized 16-bit output. These are typically TI type SN74S175. Units 67 and 68 are TI type S.
It contains four arithmetic logic units (ALUs) such as N.74S381, cascaded to provide 16-bit capacity with carry propagation. These ALUs have three input lines (e.g. lines 69 and 7).
0) can be conditioned to any one of eight logic functions by the combination of control potentials above. In this invention, only the addition function is used. Unit 71 is a combination of four 4-bit units such as the TI type 74S86.
EXCLUSIVE OR logic circuit. Each bit rank is individually combined such that dissimilar inputs to a rank produce a "1" output for that rank, and similar inputs produce a "0" output. To implement AND logic, gate 72 is configured similar to a 16-pair input logical AND function to provide 16 outputs. This is usually 4 TI type SN74S08
It consists of The selection means 50 and 51 are 4
Consists of two TI type SN74S157. The cables 90A to 90D shown in FIG. 1 are the cables 69, 7 shown in parentheses 90 in FIG.
0, 81, 82, 83, 84 and wires 65, 66
It consists of The circled number on each cable means the number of wires in each cable. The capacity of the address generator of the preferred embodiment is 16X and 16Y address bits, which, if fully utilized, can address 2 ¹⁶ x 2 ¹⁶ bits of memory if it is square. By masking, memories with smaller capacities or non-square matrix arrangements can also be addressed. For example, an unlikely 64K (65536) with 1-bit memory would utilize the entire X capacity, but only one Y address. It should be noted in the following discussion that addresses run from 0 to 2 ^n-1 . Here, n is an integer. To avoid confusion with large numbers, a simple 8x16 memory is used in the following example. The principle can be extrapolated by increasing the memory size by a power of two. Buffer stores 63, 64 and arithmetic logic unit 67 are counting means that generate sequences of base addresses independent of memory size. Essentially it is a counter that counts integer increments, and whenever a clock timing pulse is input to strobe the buffer store 63 to accept the input, the integer increment is added to the buffer store 63 as a constant. is set. For example, if buffer store 63 is preset to a binary value of 1, ALU 67 will immediately display a binary value of 1 in the lower ranks and all 0s in the 15 higher ranks. Buffer store 63 is initially set to all ones and when added to the only one in ALU 67 produces a sum of all zeros. When the output from ALU 67 is utilized, the clock signal on line 65
The pulse strobes buffer store 64 to receive a sum of all zeros from ALU 67 and adds the constant one from buffer store 63 to the zero in buffer store 64 to produce a base address of one.
By activating buffer memory 64,
The number in ALU 67 will be increased by a constant amount stored in buffer memory 63. The increase is that the clock pulse on line 65
occurs only when the output from the buffer storage 64 is enabled. This combination of ALU 67 and buffer storage 64 is equivalent to a counter that can be preset to count in desired increments. As previously mentioned, there are four identical units of FIG. 2 interconnected as shown in FIG. Cable 90A, 90B, 90C or 90D
The timing pulses applied to the wires 65A, 65B, 65C, or 65D are such that the frequency of their occurrence is a function of the relative speed at which the X home address, the X away address, the Y home address, and the Y away address are varied. They are so different. The 16-bit output from ALU 67 is applied as one input to 16-position EXCLUSIVE OR gate 71. Gate 71, as explained in the section above entitled "Decrease",
A second 16-bit input on cable 83 is received to increase or decrease the output of gate 71. this
EXCLUSIVE OR71 constitutes a control means. The binary value incremented or decremented by the control means 71 is masked from the buffer store 62 preset by the input of the cable 82 to each of the A, B, C and D units at the AND 72.
The bits are combined together bit by bit (16 bits). Methods of masking are described in the section entitled "Masking". These buffer memory 62 and AND 72 constitute masking means. Finally, the output of AND 72 is added to the offset value stored in buffer store 61 which is preset to the desired value. ALU68 is cable 7
This addition is performed under the control of the combined potential on 0. The special combination for addition to the selected ALU is 011. These buffer memories 6
1 and ALU 68 constitute offset means. The 16 bit output from ALU 68 is an X (home/away) or Y (home/away) address used to access memory. [Usage example] [Galloping pattern
Pattern)] In this test, each consecutive cell
Become a cell. An away cell is a continuous series of cells starting with the first cell in the array and ending with the last cell in the array. The home and away cells are tested in an alternating series;
The cell is actually tested twice. That is, the first time is as a home cell, and the second time is as an away cell. This simplifies the circuit and provides the same degree of test completeness and control as the more complex home and away sequences described in the publications referenced above. The number of away cells is constant and equal to the number of cells in the array. In a simple exemplary 8x16 memory (128 cells), the first away address is the address of the first cell (X=0, Y=0). The away cell sequence is from 0 to 127. In this example, the first cell 0 is actually tested twice. Home and away ALU67A, 67B, 6
7C and 67D initially address 0-0
Preset to start from the origin. Cables 83A to 83D are all set to "0" potential so that the increase occurs. Cable 69A
to 69D and from 70A to 70D
The ALU is activated to control the addition. Mask registers 62A and 62B are
Set to a value of 0111 (maximum address of X).
Registers 62C and 62D are set to 01111 (maximum address of Y). External counters (not shown) that count X home and away cycles (X home counter and X away counter) are preset to 0111. Counters (not shown) that count Y home and away (Y home counter and Y away counter) are preset to 01111. At each interrogation cycle, Y
The away counter is decremented by one count. When this is recycled from 0 to the preset value of 15, it decrements the X-away counter by one count. This advances the interrogation down the column, towards the bottom, and then steps forward until the bottom of the last column is reached, when both the X and Y away counters have been decremented to a value of zero. Step within each successive column. This coincidence (both the X and Y away counters being zero) means that the Y home
Decrease the counter by 1 count. The X and Y away counters return to zero to begin tracking the next interrogation cycle for the new home cell. Each time the X and Y home or away counters are decremented, the corresponding
ALU67 is increased. When the Y home counter completes its cycle from 15 to 0, it decrements the X home counter in the same way that the Y away counter steps the X away counter. The preset values in the mask register allow output addresses even if the X home and away ALU and the Y home and away ALU are stepped several times and represent individual values beyond the possible addresses. prevent the address from exceeding the specified address value. These X/Y home counters and X/Y away counters simply provide the frequency division to produce column stepping and cycle point counting, allowing lines 55, 65A,
Used to generate timing pulses applied on 65B, 65C, and 65D. In fact, in the example chosen, each of the 128 cells will be a home cell. Each home cell is
128 equivalent away points for 16384 steps
cells and perform 1024 repetitive cycles of 16 counts each. Therefore, the X away counter is
Decreased 1024 times. That is, 128 repeat cycles are experienced. Therefore, Y away ALU67D is 16384 (2 ¹⁴ )
While counting the maximum value of , the output from ALU68D never exceeds 15 (01111). The Y away counter advances and steps the X away counter, and both jointly step the Y home counter at (0-0);
This time it also steps the X home counter and when both the Y home and X home counters decrease to zero, the end of test signal is generated. At this point, the maximum address of X=7, Y=15 is reached. [Diagonal Pattern] Another example of a memory address sequence is a diagonal pattern. All diagonals are 45 degree diagonals and the number of cells in one diagonal sequence is the same for any one memory. Cells on the diagonal are aligned like the main diagonal of a square, or
Or arranged on two parallel diagonal lines. Again, using 8x16 memory for illustration, the number of diagonals is equal to the greater of the two dimensions (16), and the number of cells on each diagonal is equal to the lesser of the two dimensions (8). equal. There are nine consecutive diagonals and seven discontinuous diagonals. The sum of the numbers of cells on two discontinuous diagonals is eight. Initially, the X and Y address generators are set at zero offset and then incremented by a constant of one. The mask for the X address will be set to a binary value of 7 and the mask for Y will be set to a binary value of 15. Both address generators are incremented by one count at the same time. This gives consecutive addresses along a 45° diagonal. Due to masking of the X address, even if the basic address created by the ALU 67A and buffer memory 64A starts from 0
Even if we proceed to 127, the X address will repeat the sequence from 0 to 7 16 times. Masking is 7
It is prohibited to use addresses exceeding . The Y address generator is connected to line 65C at the same time as the X generator.
is cycled upward from zero by a clock pulse applied to However, to prevent the Y address from being repeated along the same diagonal, it is necessary to add an additional count to the Y address after every 16 counts to precess the diagonal one matrix position. This need is illustrated in the following sequential table of matrix positions.

[TABLE] If the successive values of the X and Y cycle counters that are preset and decremented to 7 and 15, respectively, were described in the form of a similar table, they would appear as follows: .

It will be appreciated that in the example chosen, both counters count to zero at the end of each diagonal, or eight times, simultaneously. This event (both counters are 0)
simultaneously) causes an additional count to be placed in the Y-ALU to precess the diagonal to the Y position. One of the remaining timing functions is to detect the end of the test. This can be done in various ways, either by counting the number of accesses or by counting the number of diagonals. In the former case, the counter
Preset and reduced to 127. When reduced to zero, it signals the end of the test. The latter presets the counter to 7 and is decremented each time the X and Y counters reach zero simultaneously. The cycle ends when this counter receives the last decrement pulse by the last pair of zeros and is cycled to the preset value of seven. The above example, considering the rules governing the number of diagonals and the number of cells on the diagonals,
By adjusting the parameters appropriately, it may also be extrapolated to larger memories. Also, isolated small areas of a large memory may be tested by adding offsets to the X and Y addresses and using the same addressing principles and sequences. Knowledge of the matrix geometry allows the preset data set in the address generator and cycle counter to be adjusted to define the area of memory to be tested and the test pattern. The home and away features need not be limited to sequences of individual cells, but may also be used to test corresponding regions of memory that share sense amplifiers. Home and away addresses have the same increment value, just different offsets,
A similar sequence with masking and cycle counting control is followed. Alternating home and away addressing will test for a series of cells occupying the same relative position with respect to two different geometric regions of the memory. As described for the previous example, logic elements interconnected as described above provide a wide variety of memory address sequences without requiring large external memories to supply the sequences. . External memory is only needed to provide input data to the address generator and cycle counter. The address generator then continues its function to generate address sequences without further reference to external memory. In addition to using small external memory, hard-wired address generators allow for faster testing by eliminating the constants needed to receive further instructions from external memory. It has the effect of being able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a memory address sequence generator according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a portion of FIG. 1 in detail. A, C...first address generation means, B, D...
2nd address generation means, 50, 60... selection means, 63, 67, 64... counting means, 71... control means, 62, 72... masking means, 61,
68...Offset means.

Claims (1)

Claims: 1. In an apparatus for testing the operation of a multidimensional data storage memory, one selected from among a large number of numerical sequences representing a series of memory elements to be tested.
a memory address sequence generator for generating a memory address sequence generator, responsive to a predetermined numerical value and a first timing pulse, first and second memory address sequence generators for generating a numerical sequence representing each of the memory elements to be tested; a plurality of address generation means pairs including address generation means A, B, C, and D; and a plurality of address generation means connected to outputs of the plurality of address generation means pairs, and generating the plurality of addresses in response to a second timing pulse. selecting means 50, 60 for selecting the output of the pair of means, each of said first and second address generating means being responsive to said predetermined value and said first timing pulse; counting means 63, 64, 67 for generating numerical sequences that differ by said predetermined numerical value;
and control means 71 for increasing or decreasing the numerical sequence generated by the counting means in response to a predetermined control, and in response to a constant value, the value of the numerical sequence output by the control means increases or decreases in response to the constant value. masking means 62, 72 for repeating when a value is reached; offset means 61, 68 connected to the output of said masking means for adding a constant to each of the values of the numerical sequence; A pair of address generating means generates a unique sequence of memory addresses, and said other pair of address generating means generates a unique sequence of memory addresses.
A memory address sequence generator, characterized in that it generates other unique sequences of addresses, and said selection means is capable of making a selection between said one and other unique sequences.