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JPS6231483B2 - - Google Patents
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JPS6231483B2 - - Google Patents

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Publication number
JPS6231483B2
JPS6231483B2 JP53140073A JP14007378A JPS6231483B2 JP S6231483 B2 JPS6231483 B2 JP S6231483B2 JP 53140073 A JP53140073 A JP 53140073A JP 14007378 A JP14007378 A JP 14007378A JP S6231483 B2 JPS6231483 B2 JP S6231483B2
Authority
JP
Japan
Prior art keywords
electrodes
internal electrodes
external terminal
internal
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53140073A
Other languages
Japanese (ja)
Other versions
JPS5565420A (en
Inventor
Rokuro Ashida
Ryoichi Yamashina
Kazuhiro Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichicon Corp
Original Assignee
Nichicon Capacitor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichicon Capacitor Ltd filed Critical Nichicon Capacitor Ltd
Priority to JP14007378A priority Critical patent/JPS5565420A/en
Publication of JPS5565420A publication Critical patent/JPS5565420A/en
Publication of JPS6231483B2 publication Critical patent/JPS6231483B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は改良された積層型磁器コンデンサの製
造方法に関するものである。 従来、積層型磁器コンデンサは主として第1図
に示すようにドクターブレード法、スプレー法、
印刷法などにより約25μ厚の誘電体層1を形成
し、さらに印刷法により両側面に約0.3mmの電極
マージン2を有するようにパラジウムあるいはパ
ラジウム系内部電極3を形成し、それぞれ交互に
積層したのち焼成し、さらに外部端子電極4を焼
付けて製造されている。また第2図に示すように
内部電極3の両側面に電極マージン2を有しない
構造も試みられ検討されている。 しかしながら、前者においては両側面部に電極
マージン2を有するために単位体積当りの取得静
電容量が制限され、また内部電極の印刷時におけ
るパターンずれ、にじみなどにより静電容量がば
らつく欠点がある。そして後者においては内部電
極パターンずれがなく、従つて静電容量精度は良
いが、誘電体層が約25μ厚と薄く、両側面の切断
加工時に内部電極の側面誘電体への部分的なまわ
りが生じ、そのために両側面の対向電極間で短絡
あるいは縁面放電を生じ、コンデンサとしての信
頼性に乏しい欠点があつた。 本発明は上述の欠点を改善し、単位体積当りの
取得静電容量が大きく、静電容量バラツキが小さ
く、しかも信頼性の高い積層型磁器コンデンサの
製造方法を提供するものである。 すなわち、誘電体と内部電極とを交互に積層し
て焼成したのち、該焼成体の対向する内部電極露
出部分に外部端子電極を塗布、焼成し、その後該
焼成体を外部端子電極と直角に複数個に切断して
積層チツプ素子を得る工程において、該積層チツ
プ素子の切断した両側面部が外部に露出するよう
に板状あるいは棒状に整列させてワツクス、樹脂
などで固着した状態で、該両側面部に沿つて化学
的に内部電極および外部端子電極の一部を溶解除
去し、該両側面部に内部電極マージンを形成させ
るもので、またさらに信頼性を高めるために必要
に応じて該側面部を絶縁性ガラスあるいは絶縁性
樹脂にて被覆することを特徴とするものである。 以下、本発明を第3図〜第7図に示す実施例に
ついて説明する。 第5図に示すようにドクターブレード法により
得られた誘電体シート5に一端部を除いて片面全
面にパラジウム電極ペーストをスクリーン印刷し
て内部電極6を設けたのち、該誘電体シート5を
交互に所定枚数積み重ねて熱プレスにより熱圧着
して一体化する。次に所定温度で誘電体シート5
および内部電極6を同時焼結させ、その後第6図
に示すように銀パラジウム電極を塗布、焼付けし
て外部端子電極7を形成する。その後外部端子電
極7と直角にa―a′方向に複数個にダイヤモンド
カツターにて切断した積層チツプ素子を第7図に
示すように両側面を上下にして整列させたのち、
マイクロクリスタルワツクス8で棒状に固着させ
る。次に積層チツプ素子の両側面に付着した上記
ワツクス8を平面ラツプ盤にて研削除去したの
ち、表に示す希酸溶液中に5分間、10分間、15分
間、30分間それぞれ浸漬し、水で充分洗浄して最
後にワツクスをトリクロンエチレンで洗浄、除去
して第3図に示す積層型磁器コンデンサを得た。
さらにコンデンサの信頼性を高めるために第3図
に示す積層型磁器コンデンサの両側面部9に硼珪
酸鉛ガラス粉末よりなるペーストを薄く塗布した
のち、600℃にて熱処理して硼珪酸鉛ガラス粉未
を融解させて両側面を被覆し、第4図に示す積層
型磁器コンデンサを得た。第4図において10は
被覆材としての硼珪酸鉛ガラスを示す。 積層型コンゴンサ素子の側面より内部電極を溶
解させ、それによつて形成される内部電極マージ
ン11は溶液の濃度、温度および侵漬時間によつ
て異なるもので、その結果は第8図に示すように
浸漬時間または溶液濃度により電極マージンの程
度を設定することができる。
The present invention relates to an improved method of manufacturing a multilayer ceramic capacitor. Conventionally, multilayer porcelain capacitors have mainly been produced using the doctor blade method, spray method, or
A dielectric layer 1 with a thickness of approximately 25 μm was formed by a printing method, and palladium or palladium-based internal electrodes 3 were further formed by a printing method so as to have an electrode margin 2 of approximately 0.3 mm on both sides, and these were laminated alternately. After that, it is fired, and then the external terminal electrodes 4 are baked. Furthermore, as shown in FIG. 2, a structure in which the internal electrode 3 does not have electrode margins 2 on both sides has also been tried and studied. However, the former has electrode margins 2 on both side surfaces, which limits the capacitance that can be obtained per unit volume, and also has the drawback that the capacitance varies due to pattern misalignment, bleeding, etc. during printing of internal electrodes. In the latter case, there is no misalignment of the internal electrode pattern, and therefore the capacitance accuracy is good, but the dielectric layer is thin, about 25μ thick, and when cutting both sides, the inner electrode is partially surrounded by the side dielectric. As a result, short circuits or edge discharges occur between opposing electrodes on both sides, resulting in poor reliability as a capacitor. The present invention improves the above-mentioned drawbacks and provides a method for manufacturing a multilayer ceramic capacitor that has a large acquired capacitance per unit volume, small variations in capacitance, and is highly reliable. That is, after dielectrics and internal electrodes are alternately laminated and fired, external terminal electrodes are applied to the exposed portions of the internal electrodes facing each other on the fired body, and fired, and then the fired body is laminated in multiple layers at right angles to the external terminal electrodes. In the process of cutting the laminated chip elements into pieces to obtain laminated chip elements, the laminated chip elements are arranged in a plate or rod shape so that both cut side parts are exposed to the outside, and are fixed with wax, resin, etc. This method chemically dissolves and removes a portion of the internal electrode and external terminal electrode to form an internal electrode margin on both side surfaces, and insulates the side surface as necessary to further improve reliability. It is characterized by being coated with synthetic glass or insulating resin. The present invention will be described below with reference to embodiments shown in FIGS. 3 to 7. As shown in FIG. 5, palladium electrode paste is screen printed on the entire surface of one side of the dielectric sheet 5 obtained by the doctor blade method except for one end to provide internal electrodes 6, and then the dielectric sheet 5 is alternately A predetermined number of sheets are stacked on top of each other and integrated by heat-pressing. Next, the dielectric sheet 5 is heated at a predetermined temperature.
Then, as shown in FIG. 6, silver-palladium electrodes are coated and baked to form external terminal electrodes 7. Thereafter, the laminated chip elements were cut into multiple pieces with a diamond cutter in the a-a' direction at right angles to the external terminal electrodes 7, and then arranged with both sides up and down as shown in FIG.
Fix it in a rod shape with Micro Crystal Wax 8. Next, the wax 8 adhering to both sides of the laminated chip element was removed by polishing with a flat lapping machine, and then immersed in the dilute acid solution shown in the table for 5 minutes, 10 minutes, 15 minutes, and 30 minutes, and washed with water. After thorough cleaning, the wax was finally removed by washing with triclon ethylene to obtain the multilayer ceramic capacitor shown in FIG.
Furthermore, in order to improve the reliability of the capacitor, a paste made of lead borosilicate glass powder was applied thinly to both side surfaces 9 of the multilayer ceramic capacitor shown in Fig. 3, and then heat treated at 600°C to remove the lead borosilicate glass powder. was melted to coat both side surfaces to obtain a multilayer ceramic capacitor shown in FIG. In FIG. 4, numeral 10 indicates lead borosilicate glass as a covering material. The internal electrode margin 11 formed by melting the internal electrode from the side surface of the laminated congonser element varies depending on the concentration of the solution, temperature, and immersion time, and the result is as shown in FIG. The degree of electrode margin can be set by the immersion time or solution concentration.

【表】 上記実施例において、積層チツプ素子の両側面
のワツクスを完全に除去したのちに希酸溶液中に
浸漬しているが、研削後において余剰のワツクス
または機械油などをアルコール、アセトン、トリ
クロールエチレンなどの溶剤で洗浄したのちに希
酸溶液中に浸漬すると、溶液が汚れたりしないの
で内部電極の溶解力の向上、溶解能力の持続性向
上につながる。 また上記実施例においては誘電体シートをドク
ターブレード法により製作し、これを熱圧着する
ことにより積層体を得ているが、他のスクリーン
印刷、スプレーなどの方法により積層体を得る場
合も同様であり、また内部電極も一端部を除いて
片面全面に設けたものに限らず複数列に配置して
もよく、材料としてパラジウム以外のパラジウム
銀を用いる場合も同様であり、また希酸溶液とし
て塩酸、硫酸あるいは塩化鉄溶液でも同様の効果
が得られる。さらに積層チツプ素子の両側面の被
覆用材料としては、硼珪酸鉛ガラス以外に外部端
子電極の焼付温度である800℃以下の低融点ガラ
ス絶縁材料、エポキシ、フエノール、ポリエステ
ルなどの有機絶縁樹脂を用いても同様であり、以
上全ての点において本発明の意図から逸脱するも
のではない。 以上述べた本発明の手法により側面の電極マー
ジンを少くし、単位体積当りの取得静電容量が大
きく、小型大容量のコンデンサが得られる。内部
電極パターンのずれ、にじみなどによる容量バラ
ツキが少なくなる。静電容量の調整が可能とな
り、製造時の静電容量歩留が向上する。信頼性が
高い積層型磁器コンデンサが得られるなど多くの
効果を有し、工業上ならびに実用上有益なもので
ある。
[Table] In the above example, the wax on both sides of the laminated chip element was completely removed and then immersed in a dilute acid solution. If the electrode is washed with a solvent such as chlorethylene and then immersed in a dilute acid solution, the solution will not become contaminated, leading to improved dissolving power and sustainability of the dissolving power of the internal electrode. Furthermore, in the above example, the dielectric sheet was produced by the doctor blade method, and the laminate was obtained by thermocompression bonding, but the laminate may be obtained by other methods such as screen printing or spraying. In addition, the internal electrodes are not limited to those provided on the entire surface of one side except for one end, but may be arranged in multiple rows, and the same applies when palladium silver other than palladium is used as the material. Similar effects can be obtained with , sulfuric acid or iron chloride solutions. In addition to borosilicate lead glass, the materials used to cover both sides of the laminated chip element include low-melting glass insulating materials with a temperature below 800°C, which is the baking temperature for external terminal electrodes, and organic insulating resins such as epoxy, phenol, and polyester. The same applies to the invention, and all of the above do not deviate from the spirit of the present invention. By the method of the present invention described above, it is possible to reduce the side electrode margin, obtain a large capacitance per unit volume, and obtain a small and large capacitor. Capacity variations due to internal electrode pattern misalignment, bleeding, etc. are reduced. Capacitance can be adjusted, improving capacitance yield during manufacturing. It has many effects such as the ability to obtain a highly reliable multilayer ceramic capacitor, and is useful industrially and practically.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はそれぞれ従来の積層型磁
器コンデンサの要部破断斜視図、第3図は本発明
の積層型磁器コンデンサの一実施例、第4図は本
発明の積層型磁器コンデンサの他の実施例を示
し、イは積層型磁器コンデンサの要部破断斜視
図、ロはイのb―cにおける断面図、第5図、第
6図、第7図は本発明の積層型磁器コンデンサの
製造過程例を示す斜視図、第8図は希酸溶液の種
類、濃度、浸漬時間および内部電極溶解深さとの
相関図である。 2,11:内部電極マージン、3,6…内部電
極、4,7…外部端子電極、5…誘電体シート、
9…側面部、10…硼珪酸鉛ガラス。
FIGS. 1 and 2 are perspective views of main parts of a conventional multilayer ceramic capacitor, FIG. 3 is an embodiment of the multilayer ceramic capacitor of the present invention, and FIG. 4 is a cross-sectional view of a multilayer ceramic capacitor of the present invention. Other embodiments are shown in which A is a cutaway perspective view of essential parts of a multilayer ceramic capacitor, B is a sectional view taken along b-c of A, and FIGS. 5, 6, and 7 are multilayer ceramic capacitors of the present invention. FIG. 8 is a perspective view showing an example of the manufacturing process, and FIG. 8 is a correlation diagram between the type of dilute acid solution, concentration, immersion time, and internal electrode dissolution depth. 2, 11: internal electrode margin, 3, 6... internal electrode, 4, 7... external terminal electrode, 5... dielectric sheet,
9... Side part, 10... Lead borosilicate glass.

Claims (1)

【特許請求の範囲】 1 誘電体と内部電極とを交互に積層して焼成し
たのち、該焼成体の対向する内部電極露出部分に
外部端子電極を塗布、焼付し、外部端子電極とほ
ぼ直角に該焼成体を切断し、内部電極を露出せし
めて積層チツプ素子を得る工程において、該積層
チツプ素子の切断した内部電極部が外部に露出す
るように板状あるいは棒状に整列させてワツク
ス、樹脂などで固着した状態で、該両側面部に沿
つて化学的に内部電極の一部を溶解除去し、該両
側面部に内部電極マージンを形成したのち、ワツ
クス、樹脂などを除去し、個々の積層型磁器コン
デンサを得たことを特徴とする積層型磁器コンデ
ンサの製造方法。 2 上記積層チツプ素子の内部電極マージンを形
成した両側面部を絶縁性ガラスあるいは絶縁性樹
脂にて被覆することを特徴とする特許請求の範囲
第1項記載の積層型磁器コンデンサの製造方法。
[Claims] 1. After alternately laminating dielectrics and internal electrodes and firing them, external terminal electrodes are coated and baked on the exposed parts of the internal electrodes facing each other in the fired body, and the external terminal electrodes are formed almost at right angles to the external terminal electrodes. In the step of cutting the fired body to expose the internal electrodes to obtain a laminated chip element, the laminated chip elements are arranged in a plate or rod shape so that the cut internal electrodes are exposed to the outside, and wax, resin, etc. While the internal electrodes are fixed in place, a part of the internal electrodes is chemically dissolved and removed along both side surfaces to form internal electrode margins on both side surfaces, wax, resin, etc. are removed, and individual laminated porcelains are formed. A method for manufacturing a multilayer ceramic capacitor, characterized in that the capacitor is obtained. 2. The method of manufacturing a multilayer ceramic capacitor according to claim 1, characterized in that both side surfaces of the multilayer chip element on which internal electrode margins are formed are coated with insulating glass or insulating resin.
JP14007378A 1978-11-13 1978-11-13 Method of manufacturing laminated porcelain capacitor Granted JPS5565420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14007378A JPS5565420A (en) 1978-11-13 1978-11-13 Method of manufacturing laminated porcelain capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14007378A JPS5565420A (en) 1978-11-13 1978-11-13 Method of manufacturing laminated porcelain capacitor

Publications (2)

Publication Number Publication Date
JPS5565420A JPS5565420A (en) 1980-05-16
JPS6231483B2 true JPS6231483B2 (en) 1987-07-08

Family

ID=15260331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14007378A Granted JPS5565420A (en) 1978-11-13 1978-11-13 Method of manufacturing laminated porcelain capacitor

Country Status (1)

Country Link
JP (1) JPS5565420A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4347650A (en) * 1980-09-22 1982-09-07 Avx Corporation Method of making marginless multi-layer ceramic capacitors
US5144527A (en) * 1989-08-24 1992-09-01 Murata Manufacturing Co., Ltd. Multilayer capacitor and method of fabricating the same
JP6346910B2 (en) * 2015-05-29 2018-06-20 太陽誘電株式会社 Multilayer ceramic capacitor and manufacturing method thereof
KR101854519B1 (en) 2015-05-29 2018-05-03 다이요 유덴 가부시키가이샤 Multilayer ceramic capacitor and method for manufacturing the same

Also Published As

Publication number Publication date
JPS5565420A (en) 1980-05-16

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