JPS6232630B2 - - Google Patents
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- Publication number
- JPS6232630B2 JPS6232630B2 JP53063119A JP6311978A JPS6232630B2 JP S6232630 B2 JPS6232630 B2 JP S6232630B2 JP 53063119 A JP53063119 A JP 53063119A JP 6311978 A JP6311978 A JP 6311978A JP S6232630 B2 JPS6232630 B2 JP S6232630B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- base layer
- semiconductor device
- junction
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明は順方向耐圧を改善した半導体装置、特
にサイリスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with improved forward breakdown voltage, and particularly to a thyristor.
従来技術を第１図に従つて説明する。図におい
て、１はＮエミツタ層、２はＰベース層、３はＮ
ベース層、４はＰエミツタ層、５はＮ型不純物拡
散層、１３はカソード電極、１４はゲート電極、
１５はアノード電極である。逆導通サイリスタは
サイリスタとダイオードを同一半導体基体内に逆
並列に形成した素子であり、素子に順方向の電圧
を印加したときには、J2接合が逆バイアスとなつ
て阻止状態となるが、逆方向の電圧を印加したと
きには、ダイオード領域が導電状態になる。すな
わち、順方向耐圧はJ2接合に依存している。従来
例によれば、J2接合の耐圧をもたせるため、第１
図の様なベベル構造とし、J2接合に対し正ベベル
構造となるようにしている。J2接合の耐圧を高く
するためには、J2接合の表面電界強度を小さくす
る必要がある。ベベル角度を一定にして考える
と、表面電界強度はＮベース層３の比抵抗に依存
しており、比抵抗が大きい程表面電界強度は小さ
くなる。したがつて、Ｎベース層の比抵抗を大き
くすれば表面電界強度を小さくでき、高耐圧が得
られる。しかし、Ｎベース層３の比抵抗を大きく
すると、J2接合の空乏層のＮベース層３側への伸
びが大きくなるので、Ｎベース層３の厚みを大き
くする必要がある。この場合には、Ｎベース層３
の比抵抗および厚みが共に大きくなることからベ
ース層３における順電圧降下が大きなり、また熱
抵抗も大きくなる欠点がある。 The prior art will be explained with reference to FIG. In the figure, 1 is an N emitter layer, 2 is a P base layer, and 3 is an N emitter layer.
a base layer, 4 a P emitter layer, 5 an N-type impurity diffusion layer, 13 a cathode electrode, 14 a gate electrode,
15 is an anode electrode. A reverse conduction thyristor is an element in which a thyristor and a diode are formed in antiparallel in the same semiconductor substrate. When a forward voltage is applied to the element, the J 2 junction becomes reverse biased and enters a blocking state. When a voltage of 1 is applied, the diode region becomes conductive. In other words, the forward breakdown voltage depends on the J2 junction. According to the conventional example, in order to provide the J2 junction withstand voltage, the first
It has a bevel structure as shown in the figure, and has a positive bevel structure for the J2 junction. In order to increase the withstand voltage of the J 2 junction, it is necessary to reduce the surface electric field strength of the J 2 junction. Considering that the bevel angle is constant, the surface electric field strength depends on the resistivity of the N base layer 3, and the higher the resistivity, the lower the surface electric field strength. Therefore, by increasing the specific resistance of the N base layer, the surface electric field strength can be decreased and a high breakdown voltage can be obtained. However, if the specific resistance of the N base layer 3 is increased, the extension of the depletion layer of the J 2 junction toward the N base layer 3 side increases, so it is necessary to increase the thickness of the N base layer 3. In this case, the N base layer 3
Since both the specific resistance and thickness of the base layer 3 become large, the forward voltage drop in the base layer 3 becomes large, and the thermal resistance also becomes large.
本発明の目的は、順電圧降下が小さく、かつ順
方向の大きい半導体装置、特にサイリスタを提供
することにある。 An object of the present invention is to provide a semiconductor device, particularly a thyristor, which has a small forward voltage drop and a large forward voltage drop.
本発明の背景を第２図に従つて説明する。第２
図のサイリスタはペレツトの周囲に突抜拡散部６
を有しており、突抜拡散部６とＰベース層２の間
に環状溝７が設けられ、環状溝７にはガラス８が
充填されている。このような構造のサイリスタに
おいては、順方向電圧を阻止するJ2接合は負ベベ
ルとなるので、順方向の耐圧より逆方向の耐圧の
方が、４割程度大きなり、その現象はベベル角、
不純物濃度、溝７の深さなどを変えても不変であ
ることが、実験の結果確認された。この場合順方
向の耐圧はJ2接合の耐圧であり、逆方向の耐圧は
J1接合の耐圧である。この様な構造によりJ1接合
の耐圧をJ2接合の耐圧より高くすることができる
という事実を、サイリスタの順方向耐圧改善に適
用したのが本発明である。 The background of the present invention will be explained with reference to FIG. Second
The thyristor shown in the figure has a protruding diffusion part 6 around the pellet.
An annular groove 7 is provided between the punched diffusion portion 6 and the P base layer 2, and the annular groove 7 is filled with glass 8. In a thyristor with such a structure, the J2 junction that blocks forward voltage has a negative bevel, so the reverse breakdown voltage is about 40% larger than the forward breakdown voltage, and this phenomenon is caused by the bevel angle and
As a result of experiments, it was confirmed that this remained unchanged even if the impurity concentration, the depth of the groove 7, etc. were changed. In this case, the forward breakdown voltage is that of the J2 junction, and the reverse breakdown voltage is
This is the withstand voltage of J1 junction. The present invention applies the fact that such a structure allows the breakdown voltage of the J 1 junction to be higher than that of the J 2 junction to improve the forward breakdown voltage of a thyristor.
本発明の実施例を第３図の断面図、第４図の上
面図、第５図の下面図に従つて説明する。本発明
のペレツト２０の周囲にはその一主面２０１から
他方の主面２０２まで貫通する突抜拡散部６が設
けられ、この突抜拡散部６は、ペレツト２０の一
対の主面２０１，２０２から選択的にＰ型不純物
を拡散して形成される。アノード電極１４側の主
面２０２には、突抜拡散部６とＰエミツタ層４の
間に環状溝７が形成され、その中にパツシベーシ
ヨン層としてガラス８が充填されている。また第
５図に示す様にペレツト２０のアノード側主面中
央部にはＮ型不純物拡散層５があり、逆導通ダイ
オード領域を形成している。J2接合は、第２図の
J1接合と同様にペレツト２０の周辺では突抜拡散
部６とＮベース層３の境界となつており、J2接合
の端部は環状溝７に露出し、接合の露出端部はガ
ラス８でおおわれている。 An embodiment of the present invention will be described with reference to a sectional view in FIG. 3, a top view in FIG. 4, and a bottom view in FIG. A punching diffusion part 6 is provided around the pellet 20 of the present invention, penetrating from one main surface 201 to the other main surface 202, and the punching diffusion part 6 is made of a material selected from the pair of main surfaces 201 and 202 of the pellet 20. It is formed by diffusing P-type impurities. An annular groove 7 is formed in the main surface 202 on the anode electrode 14 side between the punched diffusion part 6 and the P emitter layer 4, and is filled with glass 8 as a passivation layer. Further, as shown in FIG. 5, there is an N-type impurity diffusion layer 5 at the center of the main surface on the anode side of the pellet 20, forming a reverse conduction diode region. The J2 junction is shown in Figure 2.
Similar to the J1 junction, the area around the pellet 20 forms a boundary between the punched diffusion part 6 and the N base layer 3, the edge of the J2 junction is exposed to the annular groove 7, and the exposed edge of the junction is covered with glass 8. It's covered.
周知のようにＰベース層２とＰエミツタ層４と
の不純物濃度は等しいので、突抜部６とＮベース
層３間の接合についての不純物濃度、ベベルなど
の関係は第２図における突抜部６とＮベース層３
間の接合の場合と同じになる。すなわち、第３図
におけるJ2接合は正ベベルとなるので、その耐圧
は従来のベベル構造の耐圧より約４割程度大きく
なる。このように本発明によれば、従来例と比較
してJ2接合の耐圧が高くなり、従来例の様に表面
電界強度を小さくするためにＮベース層３の比抵
抗を大きくする必要がなくなる。その結果とし
て、Ｎベース層３の比抵抗を従来より小さくで
き、かつその比抵抗で順方向に電圧を印加したと
きにＮベース層３内に伸びる空乏層がＰエミツタ
４に到達するというパンチスルー現象が生じない
程度までＮベース３の厚みを小さくすることがで
きる。Ｎベース層３の厚みが小さくなることから
順電圧降下が小さくなり、かつ順電圧を印加した
ときの損失も小となる。特に逆導通サイリスタに
おいては、その特性改善のために、金などのライ
フタイムキラーを拡散することがあり、そのよう
な場合には順電圧降下が大きくなりがちである
が、本発明を適用すれば、Ｎベース層３の厚みを
小さくできるので、順電圧降下の増大を相殺する
ことができる。逆にＮベース層幅を従来と同一に
して考えると、耐圧は約４割大きくなり、高耐圧
の素子を得ることができる。 As is well known, since the impurity concentrations of the P base layer 2 and the P emitter layer 4 are equal, the relationship between the impurity concentration, bevel, etc. of the junction between the protrusion 6 and the N base layer 3 is the same as that of the protrusion 6 in FIG. N base layer 3
It is the same as for the joint between. That is, since the J 2 junction in FIG. 3 has a positive bevel, its breakdown voltage is approximately 40% higher than that of the conventional bevel structure. As described above, according to the present invention, the withstand voltage of the J 2 junction is higher than that of the conventional example, and there is no need to increase the specific resistance of the N base layer 3 in order to reduce the surface electric field strength as in the conventional example. . As a result, the specific resistance of the N base layer 3 can be made smaller than before, and when a voltage is applied in the forward direction with this specific resistance, the depletion layer extending inside the N base layer 3 reaches the P emitter 4, which is a punch-through. The thickness of the N base 3 can be reduced to such an extent that this phenomenon does not occur. Since the thickness of the N base layer 3 is reduced, the forward voltage drop is reduced, and the loss when a forward voltage is applied is also reduced. In particular, in reverse conduction thyristors, lifetime killers such as gold are sometimes diffused to improve their characteristics, and in such cases the forward voltage drop tends to increase, but by applying the present invention, , since the thickness of the N base layer 3 can be reduced, an increase in forward voltage drop can be offset. On the other hand, if the width of the N base layer is kept the same as the conventional one, the breakdown voltage will be increased by about 40%, making it possible to obtain a high breakdown voltage element.
本発明の効果を確認するために比抵抗50Ωcmの
前板を用い、Ｎエミツタ、Ｐベース、Ｎベース及
びＰエミツタの厚みをそれぞれ30μｍ、40μｍ、
320μｍ、30μｍとし、順電圧降下が同一になる
ようにして第１図の従来例と第３図の本発明実施
例とを比較したところ、順方向耐圧は従来例で約
1100V、本発明実施例で約1500Vであつた。 In order to confirm the effect of the present invention, a front plate with a specific resistance of 50 Ωcm was used, and the thicknesses of the N emitter, P base, N base, and P emitter were set to 30 μm, 40 μm, respectively.
320 μm and 30 μm, and the conventional example shown in FIG. 1 was compared with the embodiment of the present invention shown in FIG. 3 by making the forward voltage drop the same, the forward breakdown voltage was approximately
It was 1100V, and about 1500V in the example of the present invention.
第６図は本発明の他の実施例であり、Ｐベース
層２とＮベース層３との間にＩ層１６を介在させ
た逆導通サイリスタに本発明を適用したものであ
る。この場合も順方向耐圧が改善されることは、
以上の説明から明らかであろう。 FIG. 6 shows another embodiment of the present invention, in which the present invention is applied to a reverse conduction thyristor in which an I layer 16 is interposed between a P base layer 2 and an N base layer 3. In this case as well, the forward breakdown voltage is improved.
This should be clear from the above explanation.
第７図は本発明をゲートターンオフサイリスタ
（GTO）に適用したさらに他の実施例である。
DC電流をDCパルスに変換する手段としてGTO
を用いるような場合は逆耐圧は余り要求されず、
順方向耐圧が重要になるので、逆導通サイリスタ
の場合と同様に、本発明を適用して順方向耐圧を
向上することは有用である。 FIG. 7 shows still another embodiment in which the present invention is applied to a gate turn-off thyristor (GTO).
GTO as a means of converting DC current to DC pulses
When using
Since the forward breakdown voltage is important, it is useful to apply the present invention to improve the forward breakdown voltage, as in the case of reverse conduction thyristors.
なお、以上の各実施例において、環状溝７に露
出する２つの接合間のパンチスルーを防止するた
めには、その間隔を前記両接合間の半導体層（例
えば第３，７図のＮベース層）の厚みより大きく
しなければならない。また、溝７に充填する材料
としては、ガラス８の代りに樹脂を用いることも
できる。さらに、半導体装置の各部の導電型を反
対にしても全く同様の作用効果が得られることは
もちろんである。 In each of the embodiments described above, in order to prevent punch-through between the two junctions exposed in the annular groove 7, the distance between the two junctions must be adjusted by adjusting the distance between the semiconductor layers (for example, the N base layer in FIGS. 3 and 7). ) must be larger than the thickness of the Further, as the material to be filled in the groove 7, a resin can be used instead of the glass 8. Furthermore, it goes without saying that even if the conductivity types of each part of the semiconductor device are reversed, exactly the same effects can be obtained.
第１図は従来の逆導通サイリスタの断面図、第
２図は本発明の背景を説明するためのサイリスタ
の断面図、第３図は本発明の１実施例の断面図、
第４図は第３図のカソード側平面図、第５図はア
ノード側平面図、第６，７図はそれぞれ本発明の
他の実施例の断面図である。
１……Ｎエミツタ層、２……Ｐベース層、３…
…Ｎベース層、４……Ｐエミツタ層、６……突抜
拡散部、７……環状溝、８……ガラス。
FIG. 1 is a sectional view of a conventional reverse conduction thyristor, FIG. 2 is a sectional view of a thyristor for explaining the background of the present invention, and FIG. 3 is a sectional view of an embodiment of the present invention.
4 is a plan view of the cathode side of FIG. 3, FIG. 5 is a plan view of the anode side, and FIGS. 6 and 7 are sectional views of other embodiments of the present invention. 1...N emitter layer, 2...P base layer, 3...
...N base layer, 4...P emitter layer, 6... punched out diffusion section, 7... annular groove, 8... glass.
Claims (1)
に、互いに隣接し、それぞれの間に接合を形成す
る１導電型エミツタ層、反対導電型ベース層、１
導電型ベース層および反対導電型エミツタ層を有
し、１導電型のベース層が、上記半導体基体の周
辺部を囲んで、一対の主面間を連絡する１導電型
の半導体領域に連続している半導体装置であつ
て、 １導電型エミツタ側の主面に、１導電型エミツ
タ層および反対導電型ベース層間に形成される第
１接合と、１導電型ベース層および反対導電型ベ
ース層間に形成される第２接合とが露出する環状
溝を形成され、 前記第２接合が正ベベルであり、また 前記環状溝に露出する第１、第２接合の間隔が
反対導電型ベース層の厚みよりも大であることを
特徴とする半導体装置。 ２ 半導体基体の周辺部を囲む半導体領域は、各
主面側からの拡散によつて形成された突抜拡散部
であることを特徴とする前記特許請求の範囲第１
項記載の半導体装置。 ３ 半導体装置が逆導通型サイリスタであること
を特徴とする前記特許請求の範囲第１項または第
２項記載の半導体装置。 ４ 半導体装置がゲートターンオフサイリスタで
あることを特徴とする前記特許請求の範囲第１項
または第２項記載の半導体装置。 ５ 前記１導電型エミツタ層あるいは反対導電型
エミツタ層の少なくともいずれかがシヨートエミ
ツタ構造を有することを特徴とする前記特許請求
の範囲第１項ないし第４項のいずれかに記載の半
導体装置。[Scope of Claims] 1. In a semiconductor substrate having a pair of opposing main surfaces, 1 conductivity type emitter layer and opposite conductivity type base layer, 1 which are adjacent to each other and form a junction therebetween;
The base layer has a conductivity type base layer and an opposite conductivity type emitter layer, and the base layer of one conductivity type surrounds the peripheral portion of the semiconductor substrate and is continuous with the semiconductor region of one conductivity type that communicates between the pair of main surfaces. A semiconductor device comprising: a first junction formed between the first conductivity type emitter layer and the opposite conductivity type base layer; and a first junction formed between the first conductivity type base layer and the opposite conductivity type base layer on the main surface on the first conductivity type emitter side. an annular groove is formed in which a second junction is exposed, and the second junction has a positive bevel, and the distance between the first and second junctions exposed in the annular groove is greater than the thickness of the opposite conductivity type base layer. A semiconductor device characterized by being large. 2. The semiconductor region surrounding the peripheral portion of the semiconductor substrate is a punched-out diffusion portion formed by diffusion from each main surface side.
1. Semiconductor device described in Section 1. 3. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a reverse conduction type thyristor. 4. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a gate turn-off thyristor. 5. The semiconductor device according to claim 1, wherein at least one of the one conductivity type emitter layer and the opposite conductivity type emitter layer has a short emitter structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6311978A JPS54154285A (en) | 1978-05-26 | 1978-05-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6311978A JPS54154285A (en) | 1978-05-26 | 1978-05-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54154285A JPS54154285A (en) | 1979-12-05 |
| JPS6232630B2 true JPS6232630B2 (en) | 1987-07-15 |
Family
ID=13220072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6311978A Granted JPS54154285A (en) | 1978-05-26 | 1978-05-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54154285A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5936430B2 (en) * | 1980-01-17 | 1984-09-04 | 株式会社東芝 | semiconductor equipment |
| JPS57202779A (en) * | 1981-06-08 | 1982-12-11 | Toshiba Corp | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5621266B2 (en) * | 1973-10-05 | 1981-05-18 |
-
1978
- 1978-05-26 JP JP6311978A patent/JPS54154285A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54154285A (en) | 1979-12-05 |
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