JPS6233622B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing apparatus characterized by an automatic system restart method for establishing a normal system in the event of a system failure in an online system such as an electronic switching system.

Conventionally, online systems operate with duplex systems, and when a system failure occurs, a normal system is established and then a program is loaded from the system backup file to restore the system to online status. . However, in this case, the reliability of the system backup file becomes an issue, and if the program cannot be read normally from the backup file, the system will go down, and if it is a public online system, it will cause great social confusion. I will have to do it.

Furthermore, when performing the above-mentioned return, the program is loaded from the backup file to the main memory and then online processing is started, but this takes a considerable amount of time depending on the characteristics of the backup file, and the system service is interrupted. This is leading to a decline in sexuality.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data processing device capable of high-speed processing while maintaining high system reliability in the above-mentioned online system.

In order to achieve the above object, the present invention loads a program from a backup file when a processing device returns online after a failure occurs;
The functions processed by that program are directly processed by a more reliable microprogram within the central control unit.

According to the present invention, a system having a main memory device, a channel device, an external file memory, and a central control device that includes an emergency processing register and a control micromemory and uses a microprogram control method is configured by duplicating the system. Furthermore, an emergent engine including a means for specifying reconfiguration of the other system when one system fails, a timing generating means for initializing the redundant system, and a counter circuit for indicating the number of activations of the emergent system. In the data processing device, the counter circuit in the front emergence circuit is configured to emit a plurality of signals depending on the number of activations, and the emergence circuit is provided with means for generating a plurality of microprogram selection signals respectively corresponding to the plurality of signals using a timing signal emitted by the timing generation means and a system designation signal emitted by the means for specifying reconfiguration. A data processing device characterized in that the address of the control micromemory of the central control unit is separately set by the plurality of microprogram selection signals, and control is passed to the set address. is obtained.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of a duplex data processing device to which the present invention can be applied. As is clear from FIG. 1, it has a complete duplex configuration. That is, the main storage device 10 of the 0 system and the main storage device 1 of the 1 system
1, 0 system central control device 20 and 1 system central control device 21, 0 system channel device 30 and 1 system channel device 31, 0 system external file memory control device 40 and 1 system external file memory control device 41,
It is completely duplicated into a 0-system external file memory 50 and a 1-system external file memory 51. An emergency circuit 60 is provided between the central control devices 20 and 21 of both systems.

FIG. 2 is a diagram showing in detail the configuration of the emergence circuit shown in FIG. 1 above. The explanation will be given below with reference to FIGS. 1 and 2. For example, if there is a failure in the 0-system data processing device, that is, the main memory - central control unit - channel device - external file memory control device - external file memory device system, the Emergent Emergency activation is applied to the sea circuit 60 via a signal line 600a, and the emergency circuit 60 is activated via a signal line 610 to both central control units.
a, 611a, 612a, and 613a (details will be explained later), and in this case, the system is reconfigured on the first system side depending on the state of the emergence state 607. When the system is reconfigured, the emergence counter 6
Emergency processing that varies depending on the value of 06 is directly executed by the microprogram.

In the above case, conventionally, the selected 1-system data processing device accesses the external file memory control device 41 and loads approximately 1K steps of the emergency processing program from the external file memory 51 to a specific address in the main storage device 11. , the emergency processing program was executed from a specific address in the main memory and the process was shifted to online processing.

Therefore, the operation from the start of the emergence briefly described above until the output of a selection signal for a different microprogram will be described in detail with particular reference to FIG.

First, the emergency activation signals 600a and 600b from the 0 and 1 systems are sent to the emergency circuit 60.
When the data is entered, OR circuits 601 and 602 perform a logical sum, and a holding flip-flop 603 is set. This holding type flip-flop outputs an emergency signal 603a, which is connected to an emergency operation timing generation circuit 604, and together with a 4 ms period clock signal 604e, initial setting timing signals 604a, 604b, 6
04c and 604d are generated. Further, the during-emergency signal 603a is connected to a counter circuit 606 that indicates the number of times the emergency is activated through a differentiating circuit 605, and when the emergency is activated, the
Do 1. Also, the output 605a of the differentiating circuit 605 is 0.
It is connected to an emergence state circuit 607 that specifies whether to configure the system with data processing devices of one system or one of data processing devices of one system, and updates the state when starting up the emergence. According to the 0-system and 1-system instruction signals 607a, the output of the emergence circuit is distributed to the 0-system and 1-system and output.

The emergency circuit is reset by a reset signal 600e from the console, an emergency counter reset signal 600d from the program, and an emergency reset signal 600c from the microprogram indicating that the system reconfiguration has been successfully completed. They are each reset by Furthermore, if the system reconfiguration does not end normally, the emergency reset signal 600c is not sent out, so the timing generation circuit 604 for the emergency operation overflows, and the emergency is activated again using the timing signal 604d.

When a failure occurs in the system, flip-flop 603 is set during emergency operation, and initialization signals are generated one after another by timing generation circuit 604. That is, first, a signal 604a is issued to put both data processing devices into a system reset state (various controls are reset, registers are cleared, and the microprogram is stopped), and the system designation signal 607a and AND circuits 610 and 611 are output. and sends a system reset signal 6 to the 0-system or 1-system data processing device.
10a, 611a. At the next timing, a signal 604b for initializing the data processing devices of both systems is output, and in the same manner, the AND circuit 61
At 2,613, it is ANDed with the system designation signal 607a,
Initial setting signals 612a and 612a to both data processing devices, respectively
613a.

The emergency counter circuit 606 is incremented by +1 by the differential signal 605a of the emergency operating signal 603 when the emergency is activated.
If this counter circuit 606 is smaller than a certain value, e.g. 4, an output signal 606a is sent out; if it is smaller than another value, e.g. 8, another output signal 606b is sent; and if it is smaller than another value, e.g. Another output signal 606c is output and logic gates 616, 617, 618, 61
Sent to 9,620,621. On the other hand, these gates have emergency states 607 to 0.
System, 1 system designation signal 607a is being sent,
If this signal 607a instructs system 0 system reconfiguration, 61
Microprogram selection signals 6a, 618a, and 620a are sent to the 0 system, and the signal 607a is
If it instructs system reconfiguration of the system, 617,
Microprogram selection signals 619a and 621a are sent to the 1st system. Also, at the same time, a timing signal 604c is sent from the timing circuit 604 and sent to the 0 system or 1 system together.

Next, a detailed explanation will be given of how each central control unit 20, 21 executes a different microprogram in response to this microprogram selection signal.

FIG. 3 is a diagram showing the configuration of the central control unit in the apparatus of FIG. 1 which is an embodiment of the present invention, particularly the peripheral portion of the control memory. Note that in the figure, thick lines indicate data lines, and thin lines indicate control lines. In FIG. 3, it is designated by a micro address register (hereinafter referred to as MAR) 202. Control memory (hereinafter referred to as CM)
) 203 is read out to a microinstruction register (hereinafter referred to as MIR) 204, which controls each resource of the central control unit 20, such as registers, and controls memory access. At the same time, the address of the next CM 203 is determined. That is, there are three types of microprogram addressing.
The first method is to sequentially increase +1, and in this case, the output 202 of MAR202
a is increased by +1 in +1 circuit 205 and sent to sequencer 2
01, and the control line 204a of the MIR 204 is input to the sequencer 201 as a selection signal. The second method is for jump, in which case MIR20
4 has the jump destination address, the address data 204c similarly enters the sequencer 201, and at this time the selection signal 204b is simultaneously
It goes into the sequencer from MIR204. Furthermore, the third method is to set the contents of a certain register to CM2.
The address may be 03. At this time, for example, the contents of the emergency processing register 200 are entered into the sequencer 201, but the selection signal at this time is the timing signal 614a output from the emergency circuit 60, which is entered into the sequencer 201 (from the right side of the figure). .

When the emergency is activated, the initialization signal 6 is first output from the emergency circuit 60 of FIG.
10a is output and sent to the central control unit 20 side to control stop flip-flop 206.
is set. When this control stop flip-flop 206 is set, the function of the +1 circuit 205 changes to a through function, and the same address is set to MAR 202 every time, and when viewed from the outside, it appears as if the microprogram has stopped. I can see it.

Next, when the emergence count progresses and it is time to transfer control to the microprogram, the micro selection signals 616a, 618a, 620a from the emergence circuit 60 are set to 1, 0, 620a, respectively, depending on the value of the emergent counter at that time. 0
is sent to the central controller 20 along with the timing signal 614a, and is sent to the emergency processing register 200.
The lower 3 bits are set to 1, 0, 0 (the upper 13
bit is a fixed value), selection signal 61
The address selected by 4a and whose lower three bits are 1, 0, 0 is set in MAR202. At the same time, the control stop flip-flop 206 is reset, and the addresses of the microprograms are sequentially updated. Similarly, when the micro selection signals 616a, 618a, and 620a are 0, 1, 0 or 0, 0, 1, the lower 3 bits of the address are 010 or 0, 0, 1, respectively.
001 and is set to MAR20.

That is, by using the above method, the start address of the microprogram is changed to the lower 3 bits of 100, 010,
001 and the value of the emergency counter 606 of the emergency circuit 60.

Next, we will explain how emergency processing, which was conventionally executed by a program, can be converted into formware by a microprogram by providing the above-mentioned hardware.

FIG. 4 is a diagram showing the processing content flow of an emergency processing program by a conventional device shown for comparison.

FIG. 5 is a diagram showing the processing content flow of emergency processing of the microprogram according to the present invention.

Conventionally, referring to FIG. 4 together with FIG. 1, an emergency processing program is loaded from the external file memory 50 or 51 to a specific address in the main storage device 10 or 11, and then control is transferred to the specific address to perform emergency processing. is executed. That is, first a read/write check of the main memory is performed, and then it is checked for what reason this emergency process was activated, and if it is a normal emergency activation, the counter is incremented by 1. In the case of an emergency test using a command, a message to the effect that emergence has been activated is prepared, and in the case of file replacement, a message to that effect is prepared.

Next, the program reads the value of the counter 606 and sets phases 1 to 3. Only in the case of phase 3, initial program loading (IPL) of all programs from the external file memory 50 or 51 to the main storage device 10 or 11 is performed. Load it with In the case of phase 1 and phase 2, the contents of the main memory are trusted. Finally, the logical address to physical address conversion table is initialized and control is passed to the next restart processing program. Therefore, the processing time is long, and the serviceability of the system is not sufficient, and the reliability of the online system is not necessarily sufficient.

In the data processing device according to the present invention, the fifth
Referring to the figures in conjunction with figures 1, 2 and 3,
The emergency processing function is executed by a microprogram. That is, the entrance of the microprogram is divided into three, emergency processing program 1, emergency program 2, and emergency processing program 3, and the microaddress also has the lower three bits set to 100,010,001, and the emergency circuit 60 has its value set by the counter value of the emergence,
The emergency processing program 1, emergency processing program 2, and emergency processing program 3 start processing according to the set values. The processing contents are the same as in the conventional emergency processing program shown in FIG. In the above embodiment, the microprogram is divided into three parts, but it goes without saying that the number may be two, or four or more.

As explained above, according to the present invention, different microprograms can be directly activated depending on the number of emergency activations, so high reliability of the online system can be obtained, and the loading time from a backup file can be omitted. Furthermore, high-speed processing using microprograms can shorten processing time, speed up the system's online return time, and improve system serviceability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a duplex data processing device to which the present invention can be applied;
The figure shows an example of an emergency circuit according to an embodiment of the present invention, FIG. 3 shows an example of a central control configuration, especially the peripheral part of the control memory, and FIG. 4 shows an example of a conventional device. FIG. 5 is a diagram showing the processing content flow of the emergency processing program, and FIG. 5 is a diagram showing the processing content of the emergency processing of the microprogram in the present invention. Explanation of symbols: 10 is the main memory of the 0 system, 11 is the main memory of the 1 system, 20 is the central control unit of the 0 system,
21 is the central control device of system 1, 30 is a channel device of system 0, 31 is a channel device of system 1, 40 is an external file memory control device of system 0, 41 is an external file memory control device of system 1, and 50 is an external file memory control device of system 0. system external file memory; 51 is the 1 system external file memory; 60 is an emergency circuit; 200 is an emergency processing register; 201 is a sequencer; 202
is a micro address register, 203 is a control micro memory, 204 is a micro instruction register, 205 is a +1 circuit, 206 is a control stop flip-flop, 603 is a holding type flip-flop, 604 is a timing generation circuit, 605
606 is a differentiation circuit, 606 is an emergence counter circuit, 604c is a timing output signal, 606
A to 606c represent three output signals determined by the count number of the counter circuit 606, 607a represents a system designation signal, and 616a to 621a represent microprogram selection signals, respectively.

Claims (1)

[Claims] 1. A main storage device, a channel device, an external file memory, and a central control device that includes an emergency processing register and a control micromemory and uses a microprogram control method, is configured in duplicate, and furthermore, one means for specifying reconfiguration of the other system when one system fails, timing generation means for initializing the duplicated system, and an emergency circuit including a counter circuit that indicates the number of times the emergency is started. In the data processing device, the counter circuit in the emergency circuit is configured to emit a plurality of signals depending on the number of activations, and the emergence circuit includes the plurality of signals. Means is provided for generating a plurality of microprogram selection signals respectively corresponding to the plurality of signals using a timing signal emitted by the timing generation means and a system designation signal emitted by the means for specifying reconfiguration. A data processing device characterized in that the address of a control micromemory of a central control unit is separately set by a plurality of microprogram selection signals, and control is passed to the set address.