JPS6233673B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides means for maintaining the level of a node that may be charged and kept floating.
Regarding MOS integrated circuit devices.

Because MOS transistors have low leakage current and can be driven by electric fields, they are often used in MOS integrated circuits with nodes in a floating state. In this case, the floating node can maintain a predetermined level for a short time. However, for example, during the only refresh operation or pause operation of MOS dynamic RAM, the output node of the clock source remains in a floating state for a relatively long time, and in such cases, the level of the output node cannot be maintained at a predetermined value. .

To solve this problem, a signal level maintaining circuit shown in FIG. 1, disclosed in US Pat. No. 3,986,044, has been commonly used. In the figure, 1 is a load MOS transistor and 2 is a switch.
The transistors are MOS transistors, and first and second control signals φ ₁ and φ ₂ are applied to their gates, respectively, thereby charging and discharging the first node N ₁ . 3 is a MOS for maintaining the level of the first node _N1
a transistor whose gate is a second node
Connected to _N2 . The second node _N2 is for charging with its drain and gate commonly connected to the power supply V _DD
It is charged by a MOS transistor 4 and energized via a capacitor 5 by an energizing signal _φ3 . In this case, the transistor is
All are n channels. According to this circuit, the first
When node _N1 is charged to a high level (“1”) and kept floating, that level is maintained as follows. In other words, the second node _N2 is a charging MOS
Transistor 4 causes approximately V _DD −V _TH (V _TH is
It is constantly charged to the threshold voltage of MOS transistor 4). By repeatedly applying the energizing signal φ ₃ to this, the second node N ₂ is boosted to a voltage higher than V _DD every time the energizing signal φ ₃ is applied. In this way, the charging MOS transistor 3 is repeatedly driven in the triode operation region by the energizing signal φ ₃ , and each time the first node N ₁ is charged to approximately V _DD , so that the “1” level is maintained. It turns out.

However, this circuit has major drawbacks. Now, when the second control signal _φ2 becomes "1", the switch MOS transistor 2 is turned on, and the first node _N1 is discharged to the ground potential _Vss . At this time, since the second node N ₂ is charged to V _DD -V _TH as described above, the charging MOS transistor 3 is turned on. As a result, a steady DC current path of V _DD →MOS transistor 3 →MOS transistor 2 →V _SS is formed. Such a state often occurs when the MOS dynamic RAM is in a standby state, which increases the power consumption of the RAM and seriously affects the performance of the RAM.

In view of the above-mentioned points, the present invention provides a MOS integrated circuit device equipped with a level maintenance circuit that reduces power consumption by preventing the formation of a direct current path.

In this invention, the level maintenance circuit is configured to turn off the level maintenance MOS transistor of a node that is in a floating state without forming any direct current path when that node is brought to the ground potential. FIG. 2 shows an equivalent circuit of an embodiment of the present invention. Load MOS transistor 11 and switch MOS transistor 1 are connected to the first node _N1 .
2 are connected, and the first and second control signals φ ₁ , φ ₂
MOS transistor ₁ for maintaining the level of the first node _N1 is connected between the first node _N1 and the power supply _VDD .
3 is the same as before. The gate of the level maintenance MOS transistor 13 is the second node
Connected to _N2 . And this second node N ₂
is connected to the first node with the drain and gate in common.
It is charged through the first node N ₁ by a charging MOS transistor 14 connected to N ₁ , and is energized via a capacitor 15 by an energizing signal φ ₃ . Second node N ₂ and ground potential V _ss
A discharge MOS transistor 16 at the second node _N2 is provided between the two, and a third control signal _φ4 having the same phase as the second control signal _φ2 is applied to its gate.

The operation of this circuit will now be explained using the timing chart of FIG. All MOS transistors are n-channel. The first control signal _φ1 becomes "1" and the first node _N1 is charged via the load MOS transistor 11, and then the first node _N1 is maintained in a floating state for a predetermined period T. do. For example, in a MOS dynamic RAM, this period T is an only refresh period as described above. When this first node _N1 is charged, at the same time the charging MOS transistor 1
4, the second node _N2 is also charged. The charge level of the second node N ₂ is higher than that of the first node N ₁
This value is lower by the threshold voltage V _TH of the MOS transistor 14 . When charging of the second node _N2 is completed, the charging MOS transistor 14 is automatically turned off, and even if the potential of the first node _N1 decreases for some reason afterwards, the level of the second node _N2 will not decrease. do not have. During the period T during which the first node _N1 is charged and kept in a floating state, the energizing signal _φ3 is applied at a predetermined repetition period. As a result, the second node _N2 is pushed up to a voltage higher than the power supply _VDD every time the energizing signal _φ3 becomes "1", and is used to maintain the level.
As a result of the MOS transistor 13 being driven in the triode operating region, the first node _N1 is maintained at this level.
It is maintained at the level of power supply _VDD via MOS transistor 13.

Next, when the period T elapses and the second control signal _φ2 becomes "1", the switch MOS transistor 12
turns on and the first node _N1 is discharged to the ground potential _Vss . _At this time, _the discharge MOS
Transistor 16 is also turned on and the second node N ₂
is also discharged to the ground potential _Vss . Therefore, the level maintenance MOS transistor 13 is turned off. In this way, no direct current path is formed even during the period when the first node _N1 is maintained at the ground potential _Vss .

In the circuit of FIG. 1 as well, if a discharging MOS transistor is provided between the second node N ₂ and the ground potential V _ss as in FIG. 2, when the first node N ₁ is discharged, the level maintenance MOS transistor It is possible to turn off the transistor 3. However, if the discharging MOS transistor is simply provided in the circuit of FIG. 1 in this way, a DC current path will be formed from the charging MOS transistor 4 through the discharging MOS transistor. In the embodiment of FIG. 2, this problem is avoided by connecting the drain and gate of the charging MOS transistor to the first node _N1 rather than to the power supply _VDD .

Thus, according to this embodiment, not only can the level of the first node _N1 , which is charged and kept in a floating state, be maintained at a sufficiently high level, but also the level of the first node N1, which is charged and kept in a floating state, can be maintained at a sufficiently high level.
The power consumption of the level maintenance circuit can be reduced by preventing the formation of a DC current path when the node _N1 becomes the ground potential. In particular, by incorporating such a level maintenance circuit into the clock source of MOS dynamic RAM, the MOS dynamic
It is expected to have a significant effect on reducing the power consumption and improving the performance of RAM.

Equivalent circuits of other embodiments of this invention are shown in FIGS. 4 to 6. In these figures, parts corresponding to those in FIG. 2 are designated by the same reference numerals as in FIG. 2.

FIG. 4 shows an example in which the source of the discharge MOS transistor 16 is connected to the first node _N1 instead of the ground potential _Vss . According to this embodiment, reliability in maintaining the level of the second node _N2 is improved compared to the previous embodiment. That is, when the second node _N2 is in an activated state, the third control signal _φ4 is "0";
In other words, it is at the ground potential _Vss , but if the gate potential of the discharge MOS transistor 16 becomes higher than _VTH due to some noise, the circuit of FIG.
The MOS transistor 16 is turned on and the second node _N2 is discharged. In the circuit configuration shown in FIG. 4, the source of the discharging MOS transistor 16 is charged to the level of the first node _N1 , so even if its gate rises slightly due to noise, it remains in the pinch-off state, and therefore the second node N1 remains in the pinch-off state. Node _N2 will no longer be discharged.

In FIG. 5, instead of applying the third control signal _φ4 to the gate of the discharge MOS transistor 16, the second control signal _φ2 applied to the gate of the switch MOS transistor 12 is used as is. This has the advantage that one control signal can be saved and the circuit system can be simplified accordingly.

FIG. 6 shows the circuit of FIG. 3 in which the modifications described in FIGS. 4 and 5 are applied simultaneously. This embodiment allows more reliable signal level maintenance with a simpler circuit system.

As described above, according to the present invention, a MOS dynamic circuit has a level maintenance circuit that prevents the formation of a DC current path and reduces power consumption.
A useful MOS integrated circuit device can be provided by application to RAM, etc.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a level maintenance circuit in a conventional MOS integrated circuit, FIG. 2 is a diagram showing a level maintenance circuit according to an embodiment of the present invention, FIG. 3 is a timing chart for explaining its operation, and FIG. 4 to 6 are diagrams showing level maintenance circuits according to other embodiments of the present invention. 11...Load MOS transistor, 12...Switch MOS transistor, 13...Level maintenance MOS transistor, 14...Charging MOS transistor, 15...Capacitor, 16...Discharging
MOS transistor, N ₁ ... first node, N ₂ ...
2nd node, V _DD ... power supply, V _ss ... ground potential,
_φ1 ...first control signal, _φ2 ...second control signal, _φ3 ...energizing signal, _φ4 ...third control signal.

Claims (1)

[Claims] 1 A load MOS transistor provided between a first node and a power supply and having a gate applied with a first control signal, and a load MOS transistor provided between the first node and a ground potential and having a gate applied with a second control signal. a switch MOS transistor provided between the first node and the power supply and whose gate is connected to the second node, and a MOS transistor for maintaining the level of the first node, whose one end is connected to the second node; a capacitor to which an energizing signal is applied; a charging MOS transistor at the second node whose drain and gate are commonly connected to the first node and whose source is connected to the second node; and the second node. and the ground potential or the first node, and the second control signal or the third control signal in phase with this is applied to the gate.
for discharging the second node to which a control signal of
MOS transistor, when the first node is in a floating state in a charged state, the first node
Characterized by maintaining the level of nodes
MOS integrated circuit device.