JPS6233677B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scanning circuit that operates at high speed and has large driving capability.

Scanning circuits, or shift registers therefor (hereinafter referred to as shift registers), are used in a wide variety of applications in integrated circuits and are extremely important. As a device that can perform high-speed operation, N. Koike's “MOS Aria Sensor: Part 1
Design Consideration and Performance of an npn Structures 484×384 Elements Color MOS
Imager”, iTriple E Transaction on Electron Device ED
-Vol. 27, No. 8, pp. 1676-1681, August 1980 (N.
Koike et al. “MOS Area Sensor: Part 1
Design Consideration and Performance of an
n-p-n Structures 484×384 Elements
Color MOS Imager”, IEEE Trans.Electron
Devices, Vol.ED―27, No.8, pp.1676-1681,
There is a shift register proposed in Aug.1980.

Figure 1 shows its circuit configuration and time chart. This shift register has two registers called φ ₁ and φ ₂ .
One bit is composed of a phase clock and eight insulated gate transistors (MOS transistors) _Tr1 to _Tr8 . Furthermore, by inserting a bootstrap capacitor C _B , the drop in threshold voltage is compensated for. C _N is stray capacitance. When input pulse P _S and clock pulse φ ₁ enter at the same time, R ₁
The potential of R 2 is kept at a high level and the potential of R ₂ is kept at a low level. At this time, the capacitor C _B1 will be charged. Next, when clock pulse φ ₂ is applied, R ₂ goes to a high level through Tr ₃ . At this time, Tr ₄ is in the OFF state. The potential of C _B1 is pushed up according to the amount that the level of R ₂ rises, and the gate potential of Tr ₃ increases, which can compensate for the drop in the potential of R ₂ due to the threshold voltage of Tr ₃ . . Through a similar operation, the clock pulse _φ1 is outputted to _O1 as a _Po1 pulse through _Tr7 . Further, the charges stored in C _B1 and C _B2 are discharged by turning on Tr ₂ and Tr ₆ through the feedback line, respectively. Input pulse P
Pulse Po ₁ delayed by 1 bit with respect to _S can be extracted. This shift register operates at high speed and has the advantage of extremely low power consumption because the MOS transistors connected in series do not become conductive at the same time. Furthermore, it has the characteristic that there is no overlap between the pulses that are shifted.

The circuit configuration shown in FIG. 1 has the above features and exhibits excellent characteristics, but since the circuit has a feedback line from the circuit one bit later,
It also has disadvantages such as the stray capacitance C _N tends to increase and the final stage processing is difficult. To overcome these drawbacks, a shift register with the circuit configuration shown in Figure 2 has been proposed (Japanese Patent Laid-Open Publication No.
No. 52-95961 "Solid State Scanning Circuits"). This shift register is operated by clock pulses φ ₁ and φ ₂ and power supply V _DD as in the case of FIG. 1.
1 bit 10 MOS transistors (Tr ₉ ,...,
Tr ₁₈ ), and bootstrap capacitors C _B5 and C _B6 are provided. Since the gates of Tr ₁₁ and Tr ₁₆ are connected to the power supply V _DD , they are always in an ON state. That is, the pairs of Tr ₁₀ , Tr ₁₁ and Tr ₁₅ , Tr ₁₆ etc. are inverters having an E/D configuration.
When Tr ₁₃ and Tr ₁₈ are in the ON state, the potentials of O ₁ and O ₂ are at a low level. The threshold values of all MOS transistors are assumed to be V _th for simplicity. When clock _φ2 and start pulse P _S are input at the same time, Tr ₁₉
becomes ON state, and if the pulse voltage of P _S is V _DD , D ₁ becomes (V _DD - V _th ),
Tr ₁₀ and Tr ₁₂ are in the ON state, Tr ₁₃ is in the OFF state,
The bootstrap capacitor C _B5 is (V _DD −V _t
h ) is charged. In this state, when the clock _φ1 is applied, the clock pulse _φ1 appears as it is at _O1 due to the action of the bootstrap capacitor C _B5 . That is, if the pulse voltages of φ ₁ and φ ₂ are V _DD , a pulse with a pulse voltage of V _DD appears at O ₁ . By repeating similar operations, the pulses shift. The operating waveforms are shown in FIG. 2b. In the shift register of FIG. 2, when D ₁ is in a charging state, that is, when D ₁ is at a high level, Tr ₁₀ ,
Since both Tr ₁₁ are conductive, current flows from the power supply.
Therefore, power consumption is slightly larger than that of the circuit configuration shown in FIG. However, like the one in Figure 1, (1) power consumption does not increase even if the number of stages increases; (2)
It has the following characteristics: (3) high-speed operation can be performed; the shifting pulses can be made to have no overlap; and (3) high-speed operation can be performed.

However, in both cases, the output pulse is the clock pulse itself, so if a large number of external loads are connected, the driving capability of the clock pulse itself must be increased. Furthermore, a MOS transistor that supplies clock pulses externally,
In Figure 1, Tr ₃ and Tr 7; in Figure 2, Tr ₃ and Tr 7
This has the drawback that the driving capacity of Tr ₁₂ and Tr ₁₇ must be increased, and MOS transistors must have a large area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shift register in which pulses to be supplied externally are supplied from a power supply, while eliminating the above-mentioned drawbacks and making full use of the advantages.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3a shows a circuit configuration of a shift register according to an embodiment of the present invention.

This shift register consists of Tr ₁ to Tr ₈ , Tr ₁₀₁ ,
One bit is constituted by 10 MOS transistors of Tr ₁₀₂ and bootstrap capacitors C _B1 and C _B2 . R ₁ to R ₇ represent the potential at each point, and S
denotes the input terminal of the start pulse, and O denotes the output terminal of one stage of this shift register.

The operation of this shift register will be briefly described with reference to FIGS. 3a and 3b.

FIG. 3b schematically shows the operating waveforms of this shift register. Initial start pulse P _S
When is at a low level, the potential of each part R ₁ ~ _{R 7}
is at a low level. When the start pulse φ _S becomes high level at the same time as the clock pulse φ ₁ , C
_B1 is charged by the power supply voltage V _DD and R ₁ goes to a high level. Here, for simplicity, the clock pulse φ
₁ , φ ₂ and the start pulse P _S are V _DD , and the threshold values of all MOS transistors are V _th . At this time, Tr ₂ is turned OFF because R ₅ is at a low level.
state, Tr ₄ is in the ON state due to φ ₁ . Therefore, the potential of R ₁ is (V _DD -V _th ) and R ₂ is kept at a low level. After clock pulse _φ1 and start pulse P _S go low, clock pulse _φ2 goes high, causing _R2 to go high through _Tr3 . At this time, Tr ₄ is in the OFF state. In accordance with the amount that the potential of R ₂ rises, the potential of R ₁ also rises further due to the action of the bootstrap capacitor C _B1 , making it possible to compensate for the drop in the potential of R ₂ due to the threshold voltage of Tr ₃ . . Therefore R ₂ will be at a high level.

Since Tr ₆ is in the OFF state since R ₇ is at a low level, when R ₂ becomes a high level, R ₃ becomes (V _DD - V _th ) through Tr ₅ . At this time, Tr ₈ is φ
₂ , it is in the ON state, and R ₄ is at a low level. When φ ₂ goes to a low level and φ ₁ goes to a high level again, R ₄ goes to a high level through Tr ₇ . At this time, Tr ₈ is in the OFF state.
By the function of bootstrap capacitor C _B2
As before, the drop in the potential of R ₄ due to the threshold voltage of Tr ₇ is compensated for. At this time, as Tr ₄ is turned on, the potential of R ₂ becomes a low level again, and as will be described later, the potential of R ₅ also becomes a high level, so that the potential of R ₁ also becomes a low level.

The operation when _R4 goes high at the same time as _φ1 is the same as the operation of the shift register when the start pulse _φS goes high at the same time as _φ1 . Therefore, R ₅ will be at a high level at the same time as R ₄ ,
_R7 reaches a high level half a bit behind _R4 .
At this time, Tr ₆ is turned on, and the potential of R ₃ becomes a low level.

When _R4 reaches a high level, assuming that Tr ₁₀₂ is a depletion mode MOS transistor that has a different conductivity type from other enhancement mode MOS transistors, Tr ₁₀₁ turns ON and Tr ₁₀₂ turns OFF.
state, and the potential of O ₁ becomes (V _DD −V _th ).

When φ ₂ becomes a high level after φ ₁ becomes a low level, Tr ₈ becomes ON and R ₄ becomes a low level.

When R ₄ reaches a low level, Tr ₁₀₁ becomes
It becomes OFF state and Tr ₁₀₂ becomes ON state.
The potential of O ₁ is again at a low level. In this way, the pulse Po ₁ delayed by 1 bit with respect to the input pulse P _S is output.

Tr ₁₀₂ is not necessarily necessary as long as the external circuit includes a function of returning the level to a low level once it has reached a high level. Tr ₁₀₂ is shown in Figure 3.
Although shown as a MOS transistor, it may also be a junction field effect transistor or a static induction transistor. This shift register has high speed, low power consumption, and no overlapping of shifting pulses. Furthermore, since the output pulse is obtained from the power supply, it has a large driving capacity.

If transistors corresponding to Tr ₁₀₁ and Tr ₁₀₂ are connected to R ₂ , a shift register with a 1/2 bit delay will be created. The output pulse is delayed by half a clock cycle, but this does not pose any problem to the external circuit.

FIG. 4 shows the circuit configuration. The shift register shown in FIG. 4 has low power consumption, high speed, and high integration, and can have a large driving capacity. 1 bit is Tr ₁ to Tr ₄ , Tr ₁₁₁ ,
It consists of 6 transistors of Tr ₁₁₂ . Third
Tr ₁₀₁ in the figure and Tr ₁₁₁ in FIG. 4 are completely independent of the part that shifts the pulse and can be designed separately.

In other words, if you want to have a large driving capacity,
Transistor that supplies pulses to external circuits
Tr ₁₀₁ and Tr ₁₁₁ may be transistors with large conversion conductance, that is, large area. The transistors Tr ₁ to Tr ₄ that shift pulses and the transistors Tr ₁₀₁ and Tr ₁₁₁ that drive the external circuit are as follows:
They can be designed almost independently. That is,
Tr ₁₀₁ and Tr ₁₁₁ may be designed according to the driving capacity of the external circuit, and Tr ₁ to _{Tr 4} may be designed so that pulse shifting can be performed in the most desired state.
Tr ₁₀₂ , Tr ₁₁₂ are other enhancement modes
MOS transistors are depletion mode MOS transistors with different conductivity types. Fourth
FIG. 4b shows operating waveforms of the shift register in FIG. 4a.

FIG. 5 shows a shift register, which is one embodiment of the present invention, which does not have a feedback line as shown in FIGS. 3 and 4 and can operate at higher speed. In the circuit configuration of Fig. 2, Tr ₁₂₁ , Tr ₁₂₂ ,
Tr ₁₂₃ and Tr ₁₂₄ are connected. The gate of Tr ₁₂₂ is connected to the clock _φ2 , and the clock pulse _φ2
It turns ON every time it enters, grounding _O1 . The gate of Tr ₁₂₁ is connected to S ₁ .
One end of Tr ₁₂₁ is connected to the power supply, the other end is connected to one end of Tr ₁₂₂ , and this point becomes the output terminal, connected to the output line for driving an external circuit, and the other end of Tr ₁₂₂ is grounded. There is. The operating waveforms are shown in FIG. 5b. The pulse shifts every clock φ ₁ and φ ₂ . In the circuit of Figure 5, all transistors are
These are enhancement MOS transistors of the same conductivity type. When the start pulse P _S enters at the same time as the clock pulse _φ2 , Tr ₉ turns ON, and the start pulse P _S charges the bootstrap capacitor C _B to a high level, and D ₁ becomes a high level, which It was in the OFF state until
Tr ₁₀ and Tr ₁₂ are in the ON state, and Tr ₁₃ is in the OFF state. For simplicity, the threshold voltage of all transistors is assumed to be V _th . If the start pulse P _S is the same pulse voltage V _DD as the power supply, then C _B is (V _DD −V _t
h ), and _D1 is also charged to the same voltage.
When D ₁ is at a high level and clock φ ₁ is turned on, the voltage of D ₁ becomes higher due to the action of C _B.
The clock pulse voltage (eg, V _DD ) appears as is at the pulse shift terminal. The output terminal _O1 is at a low level because the Tr ₁₂₂ is turned on and grounded every time the clock _φ2 is input. When S ₁ becomes a high level, Tr ₁₂₁ turns on and the output terminal O ₁ becomes a high level. When S ₁ is at a high level, Tr ₁₄ is in the ON state at the same time, so D ₂
will be at a high level. At this time, the potential of D ₂ is D ₁
Similarly, it becomes (V _DD −V _th ). Tr ₁₄ ～
In the next stage composed of Tr ₁₈ , Tr ₁₂₃ and Tr ₁₂₄ , the roles of the clock pulses φ ₁ and φ ₂ are reversed from those in the previous stage. The output pulse voltage appearing at O ₁ and O ₂ is (V _DD −V _th ). If the load connected to the output terminal is only a capacitor and does not include a discharge function, the voltage waveforms at the output terminals O ₁ and O ₂ will result as shown in FIG. 6. S ₁ becomes high level, Tr ₁₂₁ turns ON, and the output terminal
When the voltage at O ₁ is charged to (V _DD - V _th ), even if S ₁ returns to a low level, the voltage at output terminal O ₁ remains at (V _DD - V _th ) and the clock φ
It will remain as _{it is until Tr 122 enters} the ON state. As a result, the shifted output pulses Po ₁ and Po ₂ overlap. If such overlapping of pulses is inconvenient, depletion mode transistors of different conductivity types are used as shown in FIGS. 3 and 4. An example of this is shown in FIG. 7 for one bit. These are Tr ₁₃₁ and Tr ₁₃₂ . S ₁ is
Connected to the gates of Tr ₁₃₁ and Tr ₁₃₂ . Tr ₁₃₁
One end of is connected to the power supply V _DD and the other end is
It is connected to one end of Tr ₁₃₂ , and this point becomes the output terminal. Tr ₁₃₂ is a depletion mode MOS transistor having a different conductivity type from other transistors. In this example, a MOS transistor is used, but a junction field effect transistor or a static induction transistor may be used. In this circuit, even if the load connected to the output terminal is a capacitor, the fifth
As shown in Figure b, pulse shifts without overlapping can be performed.

As shown in Figures 3, 4, and 7, if it is inconvenient to introduce a transistor that is different from other transistors for easy loading because it increases the number of steps in the circuit manufacturing process, The depreciation mode MOS transistor of the type is Tr ₁₃₃ in Figure 8.
You can introduce it like this. Tr ₁₃₃ is a depreciation mode MOS transistor. The gate is grounded. When Tr ₁₃₁ is in the OFF state,
Output terminal O ₁ is grounded by Tr ₁₃₃ . When S ₁ becomes high level, Tr ₁₃₁ becomes conductive and output terminal O ₁
A voltage of approximately (V _DD −V _th ) appears at . At this time,
The area is made different so that the resistance of Tr ₁₃₃ is sufficiently larger than that of Tr ₁₃₁ . In other words, Tr ₁₃₁ is a sufficiently large transistor (for example, at least 10 times more) than Tr ₁₃₃ , and is in the ON state.
The resistance of Tr ₁₃₁ is designed to be at least 1/10 or less than that of Tr ₁₃₃ . With the circuit configuration of FIG. 8, a shift register without overlapping pulse shifts as shown in FIG. 5b can be obtained even if the external circuit is a capacitive load. When considering driving a large number of pixels at the same time as in an image sensor, the Tr ₁₃₁ requires a large driving capacity.
Tr ₁₃₁ is designed larger than other transistors.

Next, the conditions for the bootstrap capacitor C _B will be described using an example in which a shift register is constructed using MOS transistors. If we extract the parts related to the role of the bootstrap capacitor C _B from the embodiments shown in Figures 3, 4, 5, 7, and 8, they are basically written as shown in Figure 9. be able to. It is composed of MOS transistors Q ₁ , Q ₂ , Q ₃ and capacitors _CN and _CB . The capacitor C _N is the sum of all capacitances that the point _A1 has with respect to the ground point, power line, etc., such as line stray capacitance. C _B is a capacitor provided between the gate of the transistor Q ₂ and one end (A ₂ ) of the main electrode corresponding to the source or drain. C _B may be formed by enlarging the diffusion region that becomes the main electrode region formed by diffusion or ion implantation, and facing the gate electrodes with a thin insulating film such as SiO ₂ or Si ₃ N ₄ interposed therebetween. However, a three-layer structure including a diffusion region, an insulating film, and low-resistance polysilicon may be formed separately.

The clock pulse voltage is assumed to be equal to the power supply _VDD . When pulse P and clock _φ2 enter at the same time,
When MOS transistor _Q1 conducts, the point
A ₁ is charged to (V _DD −V _th ). V _th is the threshold voltage of the MOS transistor. At this time point A ₂
is at a low level. Therefore, in this state, capacitors C _N and C _B are charged to (V _DD -V _th ). The charges accumulated in C _N and C _B are respectively C _N
(V _DD -V _th ), C _B (V _DD -V _th ). _Q1 ,
If Q ₂ and Q ₃ are n-channel MOS transistors, V _DD and V _th are positive. Therefore, positive charges are accumulated on the _A1 point side. In this state, Q ₂ is ON, Q ₃
is in the OFF state. In this state, clock pulse _φ1 is applied. The pulse voltage is _VDD . At this time, unless the voltage at point _A2 becomes _VDD , the pulse will decrease as it shifts, and normal operation will not be realized. Let the voltage at point _A2 be V _A2 . In this state, the voltage at point _A1 is changed from V _A1 , C _B to C
If the charge transferred to _N is ΔQ, then V _DD −V _th +ΔQ/C _N =V _A1 (1) V _DD −V _th −ΔQ/ _CB = V _A1 −V _A2 (2). In order for the shift register to operate normally, V _A2 = V _DD must be satisfied, so Equation (1),
From (2), ΔQ=C _N C _B / C _N + C _B V _DD ... (3) V _A1 = V _DD - V _th + C _B / C _N + C _B V _DD ... (4). The third term on the right side of equation (4) is the increase in voltage at point _A1 due to the input of clock _φ1 . By the way, when the gate voltage of Q ₂ is V _A1 , in order for the voltage V _DD to appear at point A ₂ , it must be V _A1 - V _DD V _th ... (5), therefore, C _N /C _B V _DD /2V _th −1 ...(6). Therefore, the threshold voltage of the MOS transistor used in the shift register of the present invention must be V _th <V _DD /2 (7). That is, V _th must be smaller than half the power supply voltage. Equation (6) is also For example, V _DD =10V, V _th
= 1V, then C _B /C _N 0.25. _CB is C
It can be reduced to about 1/4 of _N. Of course,
In an actual integrated circuit, the threshold voltage V _th of a MOS transistor is not kept completely constant, but has some variation.
C _B must be larger than the critical value given by the right-hand side of equation (8). The larger C _B is than the critical value, the more stable the shift register can operate even if the threshold voltages of the MOS transistors vary widely. If C _B is increased, a large area is required to form the bootstrap capacitor, resulting in the disadvantage that the area per stage of the shift register cannot be reduced. Even when half the clock pulse period is used as a 1-bit delay, as in the shift register of the present invention, in a circuit that requires at least five transistors per stage, it is desirable that the area required for the capacitor C _B be as small as possible. In particular, when using a shift register in the peripheral circuit of an image sensor, for example,
An extremely multi-stage shift register such as 512 x 768 pixels is required. The smaller the area per stage, the more desirable. As is clear from equation (6) or equation (8), since C _B C _N /(V _DD /2V _th −1),
The larger V _DD /V _th and the smaller C _N is, the smaller C _B can be. Compared to the ones in Figures 3 and 4, the
7 and 8, C _N can be made smaller due to the lack of a feedback line. That is,
_CB can be made smaller.

As is clear from equations (4) and (8), C _B /C _N must be larger than a certain value. The larger this value is, the higher the gate voltage of transistor _Q2 becomes.
Ample movement is achieved. However, if C _B becomes too large, ₍ C _B
+C _N ) is not charged to near (V _DD -V _th ),
Since it is only charged to a low voltage, the effect of the bootstrap capacitor when the next clock _φ1 is turned on will leave no room for operation even if the voltage increases by C _B / C _B + C _N V _DD . .

C _B of the shift register described so far,
The charging process of C _N will be described. A circuit for explaining the charging process of C _B and C _N can be written as shown in Figure 10a. MOS transistor Q and capacitor C
This is a circuit in which (C=C _B +C _N ) are connected in series. For simplicity, it is assumed that V _g and V _d are added in the form of a unit function as shown in FIG. 10b.

The current-voltage characteristics of MOS FET are usually I _d = β {(V _g - V _th ) V _d - V _d ² /2} ...(9) V _d <V _g - V _th ... (10) I _d = β/2(V _g −V _th ) ² V _d V _g −V _th However, β=με _px W/t _px L (11) is given. However, I _d : drain current, V
_d : drain voltage, V _g : gate voltage, t _px : gate insulating film thickness, ε _px : gate insulating film dielectric constant, μ: carrier mobility, L: channel length, W: channel width. Both V _g and V _d are unit functions as shown in Figure 10b, and at the moment t=O, the voltage becomes V _DD
shall increase to. MOS transistor Q
voltage V ₂ applied to capacitor C, voltage V ₁ applied to capacitor C
(However, if V _DD =V ₁ +V ₂ ), then the gate-source voltage of the MOS transistor is also equal to V ₂ . Therefore, the current flowing through the MOS transistor Q in the circuit of FIG. 10a is given by equation (10). Let i be the current flowing through the circuit of FIG. 10a, and let Q be the charge accumulated in the capacitor C. however,
Q(O)=O.

i=β/2(V ₂ -V _th ) ² ...(12) -CdV ₂ /d+=i ...(13) From equations (12) and (13), dV ₂ /(V ₂ -V _th ) ² =-β/2C (14) Integrate equation (14) from t=O to t. However, V ₂ (O)=V _DD .

Therefore, the voltage V ₁ (t) applied to the capacitor C
is, V ₁ (t)=V _DD −V ₂ V ₁ (t)=(V _DD −V _th )・t/t+to……(16) However, to=2C/β(V _DD −V _th )… …(17). FIG. 11 shows how V ₁ (t) increases with time. When the width of the clock pulse is T, for example, when the clock pulse is input and the MOS transistor Q is in the _ON state,
In order for T/to to be charged to 90% of the final charging voltage (V _DD −V _th ), T/to>10 (18) must be satisfied. From equations (17) and (18), C _B T/20β (V _DD - V _th ) - C _N ...(19) As the clock pulse width T becomes shorter, C _B must be made smaller. Equation (19)
Let us briefly consider the right-hand side of

Right side = T/20 με _px W/t _px L(V _DD −V _th
)−C _N …(2 0) Here, C _g =ε _px LW/t _px is the gate capacitance,
If C _N = nC _g , then right side = C _N {T/20 _o・μ/L ² (V _DD −V _th ) −
1}...(2 1) However, n is a numerical coefficient such as 2 or 3. Equation (21) shows that when T becomes short, the channel length L must be shortened.

Equations (8) and (19) give the range of values for bootstrap capacitor C _B . C _B must be a value that satisfies both of these inequalities.

If C _B is too small, the bootstrap capacitor will not work well and the operation will not be stable, resulting in C _B
If C is too large, it will take too much time to charge (C _B +C _N ) and sufficient operation will not be obtained, as shown below. This study has been carried out on the shift registers (scanning circuits) shown in FIGS. 5 and 7 without an output transistor.

In the scanning circuit configurations of FIGS. 5 and 7 examined, only the bootstrap capacitor C _B was changed, and all other circuit elements were kept under the same conditions. C in Figures 12, 13, and 14.
This shows the output waveform when _B is changed. FIG. 12 shows the case where C _N /C _B =0.5. The waveforms shown in FIG. 12 are clockφ ₁ , _φ2 waveform, start
pulse waveform, P _D1 waveform, P _D2 waveform, P ₂ waveform, P _D3
The waveform shows how the _P3 waveform shifts sequentially from the start pulse waveform. The last four waveforms are enlarged versions of the above waveforms clockφ ₁ , _φ2 waveform, P _D2 waveform, and P ₂ waveform. From this waveform, as mentioned above, if there is too much _CB , it takes too long to charge ( _CB + _CN ) and sufficient operation cannot be obtained, and the output waveform becomes dull compared to the clock waveform. It's getting old. FIG. 13 shows the case where C _N /C _B =4.0. The waveforms shown in Fig. 13 are clockφ
₂ waveforms, start pulse waveform, P _D1 waveform, P ₁ waveform,
It shows how the P _D2 waveform, P ₂ waveform, P _D3 waveform, and P ₃ waveform are sequentially shifted. These waveforms also show that, as already mentioned, C _B is too small and the bootstrap capacitor does not work well, so the output waveform is dull compared to the clock pulse waveform. What was revealed through this experiment was that
The shift register will not operate normally whether the bootstrap capacitor C _B is large or small; the bootstrap capacitance C _B for normal operation must be within a certain limited range. . The range of bootstrap capacitor C _B values obtained from the experimental results is determined from 0.7C _N /C _B 3.0. More preferably, it is 0.8C _N /C _B 2.0.

For example, if the parasitic capacitance C _N =0.12pF,
It is determined as 0.6PFC _B 1.5pF. FIG. 13 shows the output waveform when C _N /C _B = 2.0. This output waveform is
The waveform is almost the same as that of the clock pulse _φ1 or _φ2 , indicating that the shift register is operating normally.

The shift register of the present invention is characterized by low power consumption, high-speed operation, large external circuit drive capability, and the ability to prevent shifting pulses from overlapping. When used in a scanning circuit of an image sensor of a semiconductor integrated circuit, this characteristic that the shifting pulses do not overlap is extremely effective. That is, the outputs of the pixels of each line whose output voltages are sequentially read out can be completely separated without being mixed together. moreover,
After reading one line, the voltage on the pixel output line can be discharged to completely return to 0 before reading out the next line of pixels.

It can be used for many purposes and has high industrial value.

[Brief explanation of the drawing]

1 and 2 are shift registers, a is the circuit configuration, b is the operating waveform, and FIGS. 3 to 5 are shift registers of the present invention, a is the circuit configuration, b is the operating waveform, and FIG. 6 is the output. The operating waveform when the line is a capacitive load, Figures 7 and 8 are the shift register of the present invention, Figure 9 is a circuit explaining the role of the bootstrap capacitor, and Figure 10 is the charging of C _B and C _N. A circuit explaining the process, Fig. 11 shows the time change of V ₁ , Fig. 12 shows the output waveform of C _N /C _B = 0.5, and the first
Figure 3 shows the output waveform when C _N /C _B = 4.0, the 14th
The figure shows the output waveform when C _N /C _B =2.0.

Claims (1)

[Scope of Claims] 1. In a scanning circuit, the scanning pulse of a circuit that generates a scanning pulse for each stage is provided in each stage separately from the circuit that generates the scanning pulse, and one end of the main electrode is connected to a power source. A scanning circuit characterized in that the other main electrode of the insulated gate transistor is used as an output terminal of the scanning circuit. 2. The scanning circuit according to claim 1, further comprising an insulated gate transistor connected between the output terminal and the ground point.