JPS6233791B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the demodulation of a synchronous detection method, by digitizing its carrier regeneration circuit, and by performing phase matching on the period measurement of the input signal (for phase synchronization, a carrier wave transmission portion in a long period and a portion in a short period are used). By performing this step during the procedure in which the non-signal portion is repeatedly sent, the frequency of the oscillator used for measurement is lowered, thereby providing a carrier wave creation method that makes it easier to integrate into LSI.

Generally, vestigial sideband transmission is performed for communication over a transmission path with a limited band, such as a telephone line. In this case, to completely reproduce the original signal on the receiving side,
The carrier wave must be regenerated to perform synchronous detection.

Conventionally, when regenerating a carrier wave on the receiving side, the carrier wave component is extracted from the received signal, and a phase comparator compares it with the output of a voltage controlled oscillator. A difference signal voltage corresponding to the phase difference is output, and a low-pass filter This is a PLL (phase-locked loop) that removes high-frequency components and noise, amplifies it with a DC amplifier, inputs it to a voltage-controlled oscillator, controls it in a direction to eliminate the phase difference with the received signal, and outputs it to regenerate the carrier wave. It consists of a locked loop) circuit. This circuit is an analog circuit, and when integrated into an IC, each phase comparator, voltage controlled oscillator, etc. are integrated into an IC, but external components inevitably remain, and the lock range of the PLL circuit is determined by the loop gain. Therefore, the method of determining the loop gain is delicate, and there are disadvantages in that it may go out of lock, and it is technically difficult to integrate it into an IC because of the adjustment points and analog signal processing.
It required a lot of consideration.

In view of the above-mentioned prior art, the present invention provides a new carrier wave generation method in which the carrier wave regeneration circuit can be configured with a digital circuit.

Embodiments of the present invention will be described below with reference to the drawings.
When sending a document in a facsimile machine, phase matching is first performed, and after the phase matching is completed, an image signal is sent out. In FIG. 1, A is a transmission signal during phase matching, and a long section of continuous carrier wave transmission part and a short section of no signal part are repeatedly sent out every period a of the scanning frequency. B is a signal in the image signal and consists of a phase signal portion of b and an image signal portion of b'.
In FIGS. 2 and 3, 1 is an input signal terminal, and the waveform shown in FIG. 1A is received during phase matching, and the waveform shown in FIG. 1B is received during the image signal. 2 is a zero-crossing point detection circuit that detects the zero-crossing point of input signal A and converts it into the rectangular wave shown in B, and then detects the rising and falling edges of the rectangular wave B to create a rectangular wave C with twice the frequency. .

During phase matching, the control circuit 4 uses the phase matching wave extraction signal D indicating the section from the input terminal 3 during phase matching and the carrier wave is being sent out, and the output signal C of the zero cross point detection circuit 2 to perform a gate operation. Determines the rise of signal E. While the signal H is at H level, the counter 8 operates and starts counting the number of clock pulses of the fixed oscillator 7. At the same time, the gate 5 connects the points X and Z when the gate signal E is at H level, and applies the signal C from the zero-cross point detection circuit 2 to the counter 6. The counter 6 sends a carry signal to the control circuit 4 after counting n+1 output signals C from the zero crossing point detection circuit 2. The control circuit 4 determines the fall of the gate signal E based on the carry signal from the counter 6. Due to this fall, the counter 8 stops its operation and holds its contents. Gate signal E is a signal that is at H level for a period of n waves of signal C, which has twice the frequency of input signal A, and the fixed oscillator 7
Measure the number of pulses. This operation only needs to be performed once during phase matching, for example, when a long section carrier wave is first sent out. 9 is a divider which divides the number of pulses of the fixed oscillator 7 measured by the counter 8 into m
Then, after the measurement is completed, the divider 9 divides m by the wave number n of the signal C during the period during which the number of pulses of the fixed oscillator 7 is measured, and this result is retained with the quotient as k and the remainder as l. put. The wave number n of the signal C during the above measurement period is held as a fixed value in the counter 6 and the divider 9. In the example shown in FIGS. 3C, 3E, and 3E, n=8, m=83, k=10, and l=3. On the other hand, the counter 10 operates during the L level period of the gate signal H and counts the number of clock pulses of the fixed oscillator 7. 11 is a comparison circuit which outputs a pulse when the quotient k of the divider 9 and the contents of the counter 10 match. 12 is a delay circuit, and 13 is a remainder correction circuit. The delay circuit 12 delays the output of the comparator circuit 11 by one clock of the fixed oscillator 7 when the output of the remainder correction circuit 13 is at a binary level and is L. At this time, the output of the comparator circuit 11 is output as is. At the same time, during the period when the gate signal E is at L level, the points Y and Z of the gate 5 are connected, and the output signal of the delay circuit 12 is applied to the counter 6. Counter 6 calculates it from 0 to (n
-1). Remainder correction circuit 13
changes the output signal every time the counter 6 counts according to the contents of the counter 6 and the remainder l,
For l times out of n times, the signal is H at a binary level and the rest (n
-l) times, the delay circuit 12 is controlled by outputting an L signal.

18 is an input terminal for the phase signal extraction signal G;
4 is a phase signal extraction circuit. During phase matching, the signal G is at H level in the section where the carrier wave is sent out, and during the image signal, the phase signal, that is, the section where the carrier wave is sent out (b in FIG. 1B) is at H level. The phase signal extraction circuit 14 uses the signal G to extract one wave of the signal C from the first zero cross point detection circuit 2 after the signal G becomes H level. That is, one wave of a signal having a frequency twice that of the carrier wave component of input signal A is extracted. Furthermore, the phase signal extraction circuit 14 uses the signal CH to extract one clock of the first fixed oscillator 7 after the signal CH becomes H level. 1 is a signal for one clock of the fixed oscillator 7 extracted using the signal chi.

Gate 15 is an OR gate that adds the output signal from delay circuit 12 and the output signal from phase signal extraction circuit 14. is the output signal from the gate 15, and d in the signal is the phase signal extraction circuit 14.
The signals from the delay circuit 12, that is, the signals li and e, are the signals from the delay circuit 12. A signal from gate 15 clears counter 10 and causes fixed oscillator 7 to start counting again. After the measurement, by repeating the above operation, the signal divides the clock of the fixed oscillator 7 by k out of n times (n-l),
The remaining l times correspond to a signal that is frequency-divided by (k+1) and newly set every period a. In the example shown in Fig. 3, m = 83, n = 8, k = 10, l = 3, so the frequency division ratio is set to, for example, 10, 11, 10, 11,
It is set as 10, 10, 11, 10 and is used repeatedly. A frequency divider circuit consisting of 16 flip-flops divides the frequency of the gate 15 signal in half. 17 is an output terminal. By the above operation, output terminal 1
7, it is possible to obtain a continuous wave signal having almost the same frequency and phase as the carrier wave on the transmitting side. When measuring, if the wave number n of the signal C during the measurement period is an exponential number of 2, and n = 2 ⁱ (i is a positive integer), the lower i bit of the contents of the counter 8 in binary representation is the remainder, The remaining high-order digits become the quotient, and the divider 9 becomes unnecessary.

As described above, since the present invention is constructed of purely digital circuits except for the zero-crossing point detection circuit, it can be easily implemented as an LSI. For example, in the above embodiment, the frequency of the fixed oscillator 7 is 500 KHz (period: 2 μs), and the repetition frequency of the carrier wave sending part and the no-signal part during phase matching shown in FIG. 1 is 9 Hz, that is, 1/a= When the frequency of the carrier wave is 9Hz and the frequency of the carrier wave is 2.1KHz, 256 waves of a signal with twice the frequency of the carrier wave are extracted during phase matching, and the pulses of the fixed oscillator are counted during the phase matching. When digitized measurements are made using pulses, a measurement error of up to one pulse occurs as an error. Therefore,
There is a maximum count error of one pulse with respect to the value obtained by extracting and counting 256 waves. If measurement results are used repeatedly, measurement errors will accumulate in the reproduced carrier wave, but in this example, phase correction is performed using the phase signal in the image signal (from which the carrier wave is transmitted), and 1/a = 9 Hz. Therefore, the phase is corrected every 9 Hz. The number of 4.2KHz waves in 9Hz is approximately 467
(1/9/1/4.2×10 ³ ≒467), and the carrier wave reproduced using the count result of 256 waves is a maximum of about 2 (467/256≒2) with respect to the original carrier wave. Clock swings, ie, swings of up to 4 μs, occur. Converting this into degrees is approximately 3° ((4×10 ^-6 /1/2.1×10 ³
) x 360° = 3.024°). Further, the measurement is performed during phase matching, and correction is only made for each phase signal in the image signal. Therefore, it is possible to take advantage of the long carrier wave delivery part during phase matching and to lengthen the measurement period (by taking out a sufficiently large number of input signals) to count the pulses of the fixed oscillator. The measurement error is a maximum of one pulse during the measurement period, and if this measurement result is used repeatedly to reproduce the carrier wave, the error will accumulate, but since the correction is made using the carrier wave of the phase signal part of the image signal, it is difficult to use a fixed oscillator. It is possible to lower the frequency. Furthermore, in a signal that is transmitted over a carrier circuit many times, such as on a telephone line, there is a frequency shift due to modulation and demodulation during the carrier, and the carrier wave frequency at the time of transmission and the carrier wave frequency at the time of reception are usually different. be. In conventional PLL circuits, etc., the pull-in range is large and the circuit is complicated to achieve stable operation, and the adjustment is delicate and requires a lot of effort.However, in the present invention, the fixed oscillator on the receiver side Since the output is divided, the frequency stability is that of a fixed oscillator.If you use a stable oscillator such as a crystal oscillator, you can easily obtain a stability of about 10 ^-5 , and the lower limit of the pull-in range is , is limited by the number of bits of counter 8, for example, in the previous example (fixed oscillator frequency 500KHz, measurement period is 2
If the counter 8 is 16 bits, the frequency xHz that is twice the carrier wave that the counter 8 can measure without overflowing is calculated using the equation (500×10 ³ /x )256=2 ¹⁶
-1, and x≈1953Hz. The upper limit is determined by determining the maximum phase error. For example, if the maximum phase error is 6°, the frequency yHz, which is twice the carrier wave, is determined by the equation 1/500×10 ³
It is obtained by solving ×y/9/256=1/y/2×6/360, and y≈6196Hz. 2100 for the original carrier 2100Hz
-1123.5Hz~2100+998Hz (1953/2~6196/2
Hz) range.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an input signal entering the receiving side, FIG. 2 is a block diagram of a carrier wave generation system according to an embodiment of the present invention, and FIG. 3 is a timing chart for explaining the operation of FIG. 1, 18... Input terminal, 2... Zero cross point detection circuit, 4... Control circuit, 5, 15...
Gate, 6...Counter, 7...Fixed oscillator,
8, 10... Counter, 9... Divider, 11...
Comparison circuit, 12... Delay circuit, 13... Remainder correction circuit, 14... Phase signal extraction circuit, 16... Frequency dividing circuit, 17... Output terminal.

Claims (1)

[Claims] 1. Means for creating a signal with a frequency twice the frequency of the carrier wave during a period when a continuous carrier wave of a long period is transmitted, and a built-in fixed oscillator clock during the period of n waves of the double frequency signal. means for counting a number; means for dividing the counted result by the n to obtain a quotient k and a remainder l; A frequency divider divides the frequency by k times, and divides the frequency by (k+1) for the remaining l times.After receiving the continuous carrier wave of the long section, a phase signal is extracted from the image signal to create a signal that determines the phase. means for resetting the frequency divider based on a signal that determines the frequency divider, and means for dividing the output signal of the frequency divider by two, so as to generate a continuous wave having the same frequency and the same phase as the transmitted carrier wave. A carrier wave creation method characterized by creating a carrier wave.