JPS623499B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic card writing/reading device.

Conventionally, the writing mechanism in this type of device requires high precision, for example, a precision error of ±4% or less between written bits. To achieve this, highly accurate mechanical parts are driven by highly accurate servo control mechanisms and complex control circuits. That is,
These considerations make the device expensive.

The accuracy mentioned above is based on the specifications of the magnetic card itself, such as ABA (American Bankers Association specifications) in the United States, JBA (Japan Bankers Association specifications) in Japan, and standards of other related companies. JBA−
NTT (Nippon Telegraph and Telephone Public Corporation specifications) is much stricter. In other words, these conditions prevent the development of industries including the manufacture of magnetic cards themselves, the manufacture of magnetic card-related devices, industries that use magnetic cards, and local communities.

Furthermore, devices that only have the function of reading magnetic cards are relatively inexpensive, but they are not suitable for systems and terminals used in supermarkets such as cash dispensers, cashless terminals, and POS devices that use bank cards. In addition to preventing unauthorized use, a write function is also required, which inevitably results in an expensive product.

Furthermore, in terms of operation, the format on the magnetic card must be controlled by a central machine or controller.

Furthermore, crimes due to theft and unauthorized use have also occurred, which has become a social problem.

Note that the above-mentioned requirement for high accuracy in writing means that the magnetic card (medium) itself is touched by human hands and is susceptible to dirt, deformation of the card due to direct sunlight, and external mechanical force. , etc., it is a very difficult problem to realize this.

A writing device with universal writing characteristics under such various conditions has not been realized.

In addition, current magnetic card devices are used with different specifications depending on their field of use and form, and therefore the drive system and writing circuit of the magnetic card device are also different, which slows down the development of the industry. This is a contributing factor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a magnetic card device that eliminates the above-mentioned drawbacks.

In other words, as mentioned above, the physical specifications of magnetic cards in Japan are stricter than in the United States, but
It is an object of the present invention to provide a magnetic card device that satisfies this requirement using a simple method.

Other purposes are to assist in checking information formats and constructing data formats, to simplify connection specifications to information processing devices, etc. to which magnetic card devices are connected, and to simplify connection control devices.

Furthermore, in order to prevent social crimes related to magnetic cards, it is desirable to provide a magnetic card device that makes it difficult to forge magnetic cards and falsify data written on magnetic cards. In this respect, the present invention provides significant advantages to system operators such as banks and users of magnetic cards.

Another object of the present invention is to improve the compatibility of magnetic cards in the mutual transfer of information between banks or between banks and cashless communities, including supermarkets, etc., which is currently a problem. The present invention provides a magnetic card device that is easy to establish.

In principle, the present invention can be used as a universal magnetic card writing device, and by replacing the standard magnetic stripe, it is possible to operate magnetic cards of any specification, and in that case, there is no need to change the drive system, or It only takes a very small amount.

The first feature of the present invention is that the magnetic card writing device has a standard magnetic stripe, which simplifies the complicated drive control system and writing circuit system that required high precision in conventional devices, and allows writing to be performed more easily than before. The key lies in achieving precision.

Furthermore, a second feature of the present invention is that information for controlling the data format on the magnetic strip of the magnetic card in a prescribed manner is stored on the standard magnetic strip, and format checking and data format construction are performed. It's there to do.

In short, the present invention is characterized in that data is written onto the magnetic card to be written in synchronization with a signal on a standard magnetic stripe that has been written with high precision in advance.

Examples of the present invention will be described below.

Figure 1 is a mechanical diagram of the standard magnetic stripe, magnetic card, and head assembly;
The figure is a block diagram of portions of the read and write circuits.

In the figure, reference numbers 1 and 2 are pulleys for moving the head assembly 3, 4 is a standard magnetic stripe board, and 5 is an operated magnetic card. Reference numeral 6 indicates a clock read head for reading signals from the standard magnetic stripe 18; reference numeral 7 indicates a clock read head for reading signals from the standard magnetic stripe 18;
This is a read/write head for reading data from the head. Reference number 8 is read/write selection relay 9
This is the point of contact. Reference number 10 is a read amplifier and 11 is a write amplifier. Reference number 12 is a driver for the read/write selection relay 9. Reference number 13 is a control section. Reference number 15
is the head drive motor. Reference numeral 16 is a bias resistor for providing a theoretical electrical level. Reference number 17 is a part that converts signals with the control part, such as a front panel or an electronic computer, and is an external control part. Reference number 34 is a wire string for transmitting the power of the motor 15 transmitted to the pulley 2 to the head assembly 3. Reference numeral 35 is a head guide for uniforming the movement of the head assembly moved by the wire string 34.

First, the write operation will be explained.

When a command to start writing is sent from the external control section 17 to the control section 13 via the signal line 32, the control section 13 sends a drive signal to the signal line 31 to start the motor 15 and start the head assembly 3. Move to the writing start point. Next, the control unit 13 outputs the signal RWC to the signal line 30, drives the relay driver 12, outputs a relay drive output to the signal line 29, drives the read/write selection relay 9, and sets the relay contact 8 to the Set it to the bottom in Figure 2. The output of clock read head 6 is then routed to signal lines 20, 22,
23 to read amplifier 10. The output signal RS is sent to the control unit 13 via the signal line 24.
given to. At the same time, the signal line 25 is connected to the relay contact 8
grounded through. The control unit confirms that the signal line 25 is grounded and starts the write operation.

In this way, the signal from the standard magnetic stripe 18 is given to the control unit 13 via the signal line 24, and the control unit 13 transfers the write data sent from the external control unit 17 to the clock reading head 6.
A write signal WS is applied to the write amplifier 11 via the signal line 28 in synchronization with the write amplifier 11 . The output of the write amplifier 11 is connected to the signal lines 26, 27 and the relay contact 8.
is applied to the write head 7 via the signal line 21 to write data on the magnetic stripe 19 on the magnetic card 5.

Next, the reading operation will be explained.

When a command to start reading is sent from the external control unit 17 to the control unit 13 via the signal line 32, or under the control of the control unit itself, the control unit 13
Send a drive signal to head 1, drive motor 15 to move head assembly 3, and move head assembly 3 to head 6 and 7.
so that it is at the reading start position. Next, if the control unit 13 is outputting the signal RWC to the signal line 30, it cuts it off and relay driver 12
Stops driving. Then, the signal to the signal line 29 is cut off, and the read/write selection relay 9 stops driving. That is, the relay contacts 8 are the same as shown in FIG. The output of the read/write head 7 is then connected to the read amplifier 10 via the signal line 21, the relay contact 8, and the signal lines 22, 23. The outputs of the clock read head 6 and the write amplifier 11 are now open, +5V is applied to the signal line 25 via the resistor 16, and a signal RWS indicating this state is sent to the control section. Control part 1
3 confirms that +5V bias is applied to the signal line 25 and starts the read operation. That is, the motor 15 is continuously driven. Then, the signal from the information stripe 19 read from the read/write head 7 is applied to the read amplifier 10, and the amplified signal RS is applied to the control section 13. The control unit 13 performs necessary processing on the read signal and sends it to the external control device 1 via the signal line 32.
Send to 7.

FIG. 3 is a block diagram showing the configuration of the control section 13. Reference number 13-1 is a programmable clock generator (PCG) which outputs a clock output (CK). Reference number 13-2 is a read shift register (RSR). Reference number 13-3 is an inverting amplifier I, and reference numbers 13-4 and 13-5 are two-input AND circuits G ₁ and G ₂ whose outputs are a read clock (RC) and a write clock (WC). Reference number 13-6 is a write shift register whose output is WD. Reference number 13-7 is a delay circuit (DLY) consisting of a single shot.
outputs the write control clock (WCC).
Reference number 13-8 is an exclusive OR circuit with an inverted output, and when two inputs are equal, the output becomes true. Reference number 13-9 is a JK flip-flop which outputs a write signal WS. Reference numbers 13-10 and 13
-11 is a negative AND circuit, and 13-12 is a negative OR circuit. In addition, in Figure 3, RSR13
-2 circuit to extract data from outside and WSR1
The circuit for setting data to 3-6 is omitted.

Now, FIG. 4 is a block diagram showing an example of the configuration of the PCG 13-1 in FIG. 3. In FIG. 4, reference number 311 is a logic differential circuit LD,
When the signal RS changes in the positive direction, a pulse of PSDP is output, and when the signal RS changes in the negative direction, a pulse of NSDP is output. Reference number 312 is an OR circuit. Reference numeral 313 is a single shot that is triggered when the input changes in the negative direction. Reference number 314 is an AND circuit.

FIG. 5 is a block diagram showing the configuration of LD 311 in FIG. 4. Reference numbers 411 and 412 are inverting amplifiers, and reference numbers 413 and 414 are AND circuits. However, reference number 413 is an AND circuit that operates with false input. That is, when both the input signal and RS-D are false, the output PSDP is obtained from the AND circuit because they are inverted and input. Reference number 415 is a resistor, and reference number 416 is a capacitor, which is used to create a delay.

In the following description, in order to facilitate understanding, it is assumed that there is no delay in logic circuits, amplifiers, etc.

Now, in the circuit shown in FIG. 2, when a read operation starts, the signal obtained from the read/write head 7 is applied to the control section 13 from the signal line 24 via the read amplifier 10 as the signal RS. .
Note that here, in order to make it easier to understand the gist of the present invention, an example using phase modulation will be described.

FIG. 6 is a timing chart for explaining the logic differentiator circuit LD311, and FIG. 7 is a timing chart for explaining the read operation.

Assume that the signal RS is input from the signal line 24 as shown in FIG. The signal input at this time is “1010011
...”. First, the signal RS is sent to the circuit shown in Fig. 4. Here, the logic differentiator circuit
In the circuit of the LD311 shown in FIG. 5, output pulses PSDP and NPDP are obtained as shown in FIG. That is,
As shown in FIG. 6, the signal RS is inverted by an inverting circuit 411. This output is the resistor 415
and is integrated by the capacitor 416, resulting in -D. When this is input to the inverting amplifier 412,
An output like RS-D is obtained. Therefore, the AND circuit 4 of the inverted input of and the inverted input of RS-D
13 provides the logical differential output PSDP when the signal RS changes in the positive direction. Similarly,
By adding RS-D to the positive AND circuit 414, a logical differential output NSDP when RS24 changes in the negative direction can be obtained. In other words, from the above input signal sequence "1010011...", as shown in Figure 7, PSDP
and NSDP are obtained. Therefore, as shown in Fig. 4, the logical sum of PSDP and NSDP is taken by the logical sum circuit 312, and when the output changes in the negative direction, if the single shot (DLY1) 313 is not operating. , AND circuit 314 is satisfied, outputs CK and triggers (DLY1) 313. The delay time of (DLY1) 313 is
If the distance from information to information is t, it is set to 3/4t from the information position of signal RS. Then, for example, in Figure 7, the 4th and 5th information “00”
PSDP is output in the middle of , but since (DLY1) 313 is operating at this time, AND circuit 314 is not satisfied. If the information is "11" consecutively, NSDP appearing in the middle can be prohibited for the same reason.

Now, the clock output CK obtained in this way is
The output RWS obtained by the above-mentioned read/write selection relay 9 being on the reading side satisfies the AND circuits G ₁ and 13-4, and the output RC is obtained. When this RC goes negative, that is, when the clock output CK goes negative, the signal RS is read and shifted into the shift register RSR13-2.

Now, the write operation will be explained next.

In FIG. 2, as previously mentioned, when a write operation occurs, the read/write relay 9 is activated, connecting the relay contacts 8 in the opposite direction as shown in FIG.
The clock read head 6 is then connected to the read amplifier 10. The output of write amplifier 11 is also connected to read/write head 7. That is, the read/write head 7 is used for writing. Then, when a write operation begins, the clock signal obtained from the clock read head 6 is outputted as the clock output CK, as shown in FIG. 8, in the same manner as during the previous read operation. In Fig. 3, since the signal RWS is false, the output of the inverting amplifier 13-3 which receives it as an input becomes true, so it is the same as the clock output CK via the AND circuit G ₂ and 13-5. At the same time, we get the signal WC. Since the clock output CK is input to single shot 13-7, DLY 13-7 is triggered when CK changes in the positive direction and provides output WCC. Here, the output WCC is assumed to be t/2.

Assume that write information is initially set in write shift register WSR13-6. Let that data be “1100101…”. Then, WSR13
The first output of the output signal WD from -6 is “1”
It is becoming. Therefore, assuming that the JK flip-flop 13-9 has been reset, when the WC signal comes, the NAND circuit 13-10 is satisfied, and at the rising edge of the signal WC, the JK flip-flop 13-9 is reset. Set. That is, the output signal
WS changes as shown in Figure 8. Next, the WSR information is shifted by one at the point where WC changes negatively. However, since the second information written is also "1", the signal WD remains "1". At this time,
Since the output of the JK flip-flop and WD are equal, the output of the negative exclusive OR 13-18 is true. After 1/2t time has elapsed from the beginning of clock output CK, single shot DLY13-7
Since the output WCC of the JK flip-flop 13-9 changes to negative, the output signal of the JK flip-flop 13-9 changes according to the above conditions.
WS is reversed. That is, the result is as shown in FIG. Next time the signal CK is generated, the signal WD is true, so the NAND circuit 13-
10 is satisfied, JK flip-flop 13-
Set 9. Next, WSR is shifted when WC changes to negative, so signal WD becomes false. Next, even if WCC changes to negative, the output of JK flip-flop 13-9 and WD are different, so
The negative exclusive OR 13-8 is not satisfied and therefore the JK flip-flop does not invert as shown in FIG. Next, when the signal CK is generated, the output signal WD is false, that is, is true, so it satisfies the NAND circuit 13-11, therefore satisfies the NOR circuit 13-12, and the JK flip Flop 13-9 is reset. Thereafter, when WC becomes negative, WSR 13-6 is shifted. However, at this time, since the information is "0", the output signal WD remains false and does not change. However, since the JK flip-flop 13-9 is also false, the output of the negative exclusive OR 13-8 is true. Therefore, after a time period of 1/2t has passed since the beginning of the signal WC, when WCC changes to negative, the JK flip-flop 13-9 is inverted as shown in FIG. Similarly, as shown in Figure 8, the signal WS is
The information is then sent to the write amplifier 11 shown in FIG.

In addition, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7
The above embodiments using FIG. 8 and FIG. 8 explain the gist of the invention in an easy-to-understand manner. We have omitted the processing to be performed when the data has been lost, and have described the timing of reading and writing information, which are important in the present invention.

Next, an embodiment in which a clock pattern is programmed will be described. This is the third
Programmable clock generator PCG in figure
The portion 13-1 is shaped as shown in FIG.

In FIG. 9, reference numeral 311 is the logic differentiator circuit as described previously, and when the input signal RS from the signal line 24 changes in the positive direction, it outputs a PSDF pulse and the signal RS becomes negative. When changing direction,
Outputs NSDF pulse. These two types of pulses are mixed in an OR circuit 312. Reference number 50
0 is an AND circuit, reference number 502 is an OR circuit,
Reference number 501 is a counting circuit that counts when the input changes to negative, reference number 503 is a single shot (SS1) that is triggered when the input changes to positive, reference number 504 is an inverting amplifier, reference numbers 505 and 506 are , a negative AND circuit, reference number 507 is an AND circuit, reference number 508 is an OR circuit that produces a negative output with a negative input, reference number 50 is a resistor for biasing the J input of the JK flip-flop 510 to +5V. , reference number 511 is a counting circuit CTR2 that counts the clock when the input changes positively, reference number 51
2 is a single shot (SS3) that is triggered when the input changes negative, reference number 513 is a single shot SS2 that is triggered when the input changes positive, and reference number 514 is an AND circuit that outputs CK. do. Also, reference numeral 515 is a single shot (SS4) that is triggered when the input changes from positive to negative.

Now, the read operation will be explained using the timing chart shown in FIG.

First, the signal “110001…” is sent to the signal RS on the signal line 24.
“…”.However, suppose that the interval between the 4th number and the 5th number is twice that of the other numbers.This is LD31
According to 1, they are PSDF and NSDF, and OR circuit 3
12. Therefore, when the first signal "1" () arrives, the JK flip-flop 510 is off, so the AND circuit 500 is satisfied and outputs a signal as shown in FIG. Then, when the pulse output of AND circuit 500 changes to positive, SS1 503 is triggered. In addition, SS1
The delay time of 503 is 3/4t. Next, when the pulse output of AND circuit 500 changes to negative, CTRI 501 is counted.

At the same time, the JK flip-flop 510
side input is biased true by resistor 509,
Since the K side input is grounded, it is set.
At this time, assuming that the output of CTR1 501 is not "4", the signal (=4) is false, so the input of AND circuit 507 is negated, and therefore CRT2 511
is not counted, and its output (=2) is false, so the output of the inverting amplifier 504 is true, and the AND circuit 5
The input of 06 is negated. Therefore, SS1 503
satisfies the AND circuit 505 when it times out a delay of 3/4t. This output passes through OR circuit 508 and clears JK flip-flop 510. During this time, SS2 513 first
Assuming that it is triggered during the processing of the last bit, such as the preamble and start code processing before the timing chart shown in Figure 1 (*1), the logical AND Both the output of the circuit 500 and the output REDW of the (SS2) 513 satisfy the AND circuit 514 and output the output CK. Repeat the same thing below,
(CTR1) Count 501. Therefore, the first
Assume that you have reached the point in Figure 0. Then, first, at the rising edge of the output pulse of the AND circuit 500, (SS1) 503 is triggered via the OR circuit 502. Next, at the falling edge of the output pulse, (CTR1) 501 counts and becomes "4". Then, the AND circuit 505 is negated. At the same time, since the AND circuit 507 is satisfied, (CTR2) 511
is counted. Then, when SS1 503 times out, (SS3) 512 is triggered and 1/4t
later times out. When (SS3) 512 goes negative, single shot (SS4) 505 is triggered which produces an output with a pulse width sufficient to trigger (SS1) 503. This results in
(SS1) 503 is retriggered via the OR circuit 502. At this time, (CTR2) 551 is counted at the rising edge of (SS1) 503. Then, its output (=2) becomes true, and the output of the inverting amplifier 504 becomes false. Next, when (SS1) 503 times out after 3/4t, AND circuit 506 is satisfied and clears JK flip-flop 510. Then, (SS2) 513 is triggered and t/
Outputs the REDW signal during 2. Next, when there is an output pulse from the AND circuit 500, at its rising edge or at the output of (SS4) 515, (SS1) 50
3 is triggered. Next, (CTR1) 501 is counted at the falling edge of the output pulse of the AND circuit 500. That is, the AND circuit 507 is negated. Thereafter, the output (CK) of the AND circuit 514 is output in the same manner as described above.

By appropriately selecting the respective outputs of CTR1 and CTR2, the reading format can be programmed as desired.

Next, the write operation will be explained.

Programmable clock generator in Figure 3
PCG13-1 is shown in FIG. 9 as described above.
Also, the write information is "110010...". Since this is a write operation, the signal RS arriving at the signal line 24 is a clock signal, and the circuit shown in FIG. 9 outputs the signal CK as shown in FIG. 11 in the same manner as described above. Ru. signal at this time
Suppose that CK is twice as large before as compared to other cases. Then, as already explained,
In the circuit shown in FIG. 3, the single shot DLY13-7 is triggered by the rise of the signal CK, and its output WCC is output for a period of t/2. Similarly, CK passes through AND circuit 13-5 and becomes its output WC, and since the output WD of WSR 13-6 is true, it sets JK flip-flop 13-9 via AND circuit 13-10. That is, the output of WS is shifted as shown in FIG. 11, and then the information of WSR 13-6 is shifted at the falling edge of CK. Next, after t/2 from the rise of CK, the single
Shot DLY13-7 times out and makes its output WCC false. At this time, the output of the negative exclusive OR circuit 13-8 is true, so
Invert JK flip-flop 13-9. Next, when the signal CK arrives, WCC is triggered at its rising edge in the same way as above. Also, since WD is “1”, JK is passed through the AND circuit 13-10.
Set flip-flop. This is the 11th
This is the location shown in the figure. Next, when the write shift register WSR13-6 is shifted at the falling edge of CK, its output WD becomes "0". Next, single shot DLY13-7 times out and even though WCC becomes false, the output of the negative exclusive OR is false, so JK flip-flop 13-9
does not operate, and its output WS is as shown in FIG. Next time CK arrives, at its rising edge
DLY13-7 is triggered and AND circuit 13
-11 is satisfied, the JK flip-flop 13-9 is reset via the OR circuit 13-12. Next, at the falling edge of CK, WSR13-6 is shifted. Next, when DLY13-7 times out, WD is "0" at this time and the output of the negative exclusive OR circuit 13-8 is true, so
JK flip-flop 13-9 is inverted or set and its output signal WS is as shown in FIG. When the next CK arrives, at its rising edge, the JK flip-flop 13-9 is reset in the same manner as described above, and at its next falling edge, the write shift register WSR 13-6 is shifted, and its output WD becomes “1”. Next DLY13
Even if -7 times out, the output of the negative exclusive OR circuit 13-8 is false, so the JK flip-flop 13-9 does not operate. Then after some time here 2t, when CK comes, DLY again
13-7 is triggered at the rising edge, and at the same time,
Since WD is "1", JK flip-flop 13-9 is set. Next, at the falling edge of CK, WSR13-6 is shifted. Then DLY
When 13-7 times out, JK flip-flop 13-9 does not change because the output of the NOR is false.

Thereafter, similar operations are repeated to obtain the output WS, which is amplified by the write amplifier 11 and then transferred to the magnetic head 7.
Write information to the magnetic stripe via.

FIG. 12 is a block diagram showing an example of error detection in information read from a magnetic card. In Figure 12, 600 is JK flip-flop 60
This is a resistor for truly biasing the J side of 2.
Let the output of JK flip-flop 602 be ECF. 603 is a NAND circuit, and 604 is a JK flip-flop whose output is ERF. 605 is a negative OR circuit. The inputs in FIG. 12 each come from FIG. The operation of the circuit in Fig. 12 is as follows:
The timing chart shown in FIG. 10 explains this. That is, in FIG. 10, the JK flip-flop 602 is set by the fall of the signal DLF and outputs the ECF signal. Then the signal
If the output of the AND circuit 500 comes while REDW is true, the JK flip-flop 602 is reset via the NAND circuit 603 and the NOR circuit 605. That is, the signal ECR is made false. Then even if signal REDW becomes false, signal ECF
Since is false, JK flip-flop 604 is not set, so the error output ERF remains false. For example, if the signal #1 in FIG. 10 is not obtained as an output to the AND circuit,
JK flip-flop 602 is not reset. Therefore, signal ECF biases the J side of JK flip-flop 604 so that the next signal
JK flip flop 60 where REDW falls
4 is set and issues an error output ERF. Furthermore,
As for the portions with different pre-programmed intervals, such as between and in FIG.
Since DLF is made false, the output ECF of JK flip-flop 602 becomes true at this time. Next, if the output #2 of the AND circuit 500 is obtained while the signal REDW is true, the JK flip-flop 60
2 resets the JK flip-flop 602 via the NAND circuit 603 and the NOR circuit 605, making the output ECF false. Then, the next time the signal REDW (*2) falls, the signal
Since ECF is false, JK flip-flop 6
04 is not set and the error signal ERF is not output. However, the output #2 of the AND circuit 500
If not obtained, JK flip-flop 602
remains set, so the signal
Since ECF is being output, when signal REDW falls, JK flip-flop 604 is set and error signal ERF is output. The control unit 13 receiving the signal ERF performs processing corresponding to the error in the read information.

In this embodiment of error detection, if the output of the AND circuit 500 is not obtained while the signal REDW is true, it is detected as an error. Furthermore, even if the intervals between the signals are different between the signals programmed in the middle, the time is measured and processed. Further, as can be understood from the above explanation, if information is included in the standard magnetic stripe, it can be used for various types of control.

In the above description of the embodiment, the delay of each amplifier and logic circuit was ignored. However, in reality, a delay occurs in the amplification and logic circuits, so it can be corrected by physically shifting the position of the magnetic card 5 by the amount of the delay, as shown in FIG. 1st
In Figure 3, α ₀ is the physical deviation. X
is the physical distance from the beginning of the standard magnetic stripe substrate 4 to the first information of the standard stripe 18. Normally, dummy pulses are also recorded during this time. a indicates the interval of the clock signal.
m is the length of the standard stripe board 4, m' is the length of the magnetic card 5, and m and m' are errors within the standard (m≈m'). n is the position where information of the standard stripe 18 is written. Y is the physical distance from the last piece of information to the end of the standard stripe 18, and is determined by the standard. FIG. 14 is an enlarged view of the circular portion of FIG. 13. Now, when writing begins, the first clock signal is read at point b ₁ and, shifted by the amplifier and logic delay α ₁ , the first information is written at point b ₁ '. Similarly, b _{2 ′} is written with a deviation of α ₂ from b 2 , and b ₃ ′ is written with a deviation of α ₃ from b ₃ , and the same process is repeated until the end. Here, the initially physically set deviation α ₀
and the delay α ₁ caused by the amplification and logic circuit are almost equal, and each delay α ₁ , α ₂ , α ₃ , . . .
…Assuming that α _o is almost equal, (α ₁ ≒ α ₂ ≒ α ₃
≒...≒α _o ) The above X becomes almost equal to X' of the information stripe 19 newly written on the magnetic card 5 (X≒X') and n becomes almost equal to n' (n≒
n'), Y becomes approximately equal to Y'(Y=Y'). Here, since the above-mentioned m is almost equal to m', the difference α ₀ at the beginning edge of the standard magnetic stripe board 4 and the magnetic card 5 and the difference α _o+1 at the end edge are almost equal (α ₀
≒α _o+1 ). Here, it is also possible to program the above-mentioned clock signal interval appropriately in the X and Y parts (the part where the dummy pulses are recorded), and this can be detected during playback and the fraudulent card can be extracted. It is effective for

In addition, in FIG. 13, the magnetic card 5 is
Instead of shifting by ₀ , it is also possible to set X to X-α ₀ in advance, or even to shift heads 6 and 7 in advance.

FIG. 15 is a diagram showing writing control. Here, two tracks of the previously mentioned standard stripes are provided, (S1, S2) S1 is used for clock (write control), and S2 is used for format control. In Figure 15, _S2 has a start code (ST) and an end code (END), and an operation control key code.
OCK1(A), OCK2(B), ..., OCKM(M),
OCKN (N) is provided, and an operation control key corresponding to this operation control key code is also provided, and each time the operation control key is pressed, the S2 operation control key code is The above operation controls corresponding to the keys
Write data corresponding to the key code is recorded on the magnetic card 5. In the phase modulation method described above, as can be understood from the above explanation, the clock S1 and the format control information S2 can be recorded on the same track.

As can be understood from the above explanation, the conventional magnetic card device of the type in which the clock or information interval and the interval can be freely selected has to use a servo system in its mechanism, making it extremely complicated. Moreover, it required high-precision control, was expensive, had problems with maintainability, and required a sophisticated equipment environment in terms of operation. However, by defining a programmable range to a certain extent and providing standard stripes, by significantly simplifying the drive mechanism, and by removing the servo system from the previous one, the present invention is less expensive and has a higher write operation than the previous one. It is possible to provide a device that can accurately detect errors in reading and prevent counterfeiting and unauthorized use of magnetic cards. Additionally, the read shift register (RSR) and write shift register (WSR) can also be implemented in LSI or MSI.
It can be understood that the control section can be easily created using a , and the number of other parts is small, so the control section can be implemented at a low cost.

[Brief explanation of the drawing]

The drawings show a typical embodiment of the present invention, and FIG. 1 is a mechanical diagram showing the general mechanism of the present invention, FIG. 2 is a block diagram for explaining the read and write circuit, and FIG. This figure is a block diagram showing the configuration of the control section 13 in FIG. 2, FIG. 4 is a block diagram showing the configuration of the programmable clock generator 13-1 in FIG. 3, and FIG. 5 is a block diagram showing the configuration of the programmable clock generator 13-1 in FIG. 311
FIG. 6 is a timing chart for explaining the logic differentiation circuit 311.
FIG. 7 is a timing chart for explaining a read operation, FIG. 8 is a timing chart for explaining a write operation, and FIG. 9 is a block diagram showing yet another example of the programmable clock generator 13-1. , FIG. 10 is a timing chart for explaining a read operation according to the embodiment of the block diagram of FIG. 9, and FIG. 11 is a timing chart for explaining a write operation according to the embodiment of the block diagram of FIG. 12 is a block diagram showing an error detection circuit for read information, FIG. 13 is a partially omitted diagram to explain the misalignment between the standard magnetic stripe board 4 and the magnetic card 5, and FIG. 14 The figure is number 13
FIG. 15, which is a partially enlarged view of the circled part of the figure, is a diagram showing format control. Reference numbers in the figure: 4...Standard magnetic stripe board, 5...Magnetic card, 6...Clock read head, 7...Read/write head, 8...Relay contact, 9...Read/write selection relay, 10... …
Read amplifier, 11...Write amplifier, 12...
Relay driver, 13...control unit, 13-1...
...Programmable clock generator, 18...Standard magnetic stripe, 19...Information stripe, 31
1... Indicates a logic differential circuit.

Claims (1)

[Scope of Claims] 1. In a magnetic card device having a standard magnetic stripe fixedly disposed therein and storing a clock signal, a portion of the standard magnetic stripe in which adjacent clock signal intervals are different from other areas. At the same time, the control circuit is programmed and stored in advance in consideration of the different parts of the clock signal, reads the clock signal, and in synchronization with the read clock signal, detects the magnetic card inserted from the outside. When writing the necessary write information to the magnetic stripe and reading it, the information is read out according to the program, and when the information is read at an interval different from the programmed interval, the information is determined to be error information, and the information is read out according to the program. A magnetic card device characterized in that a head for reading signals and a head for exchanging information with the magnetic card are configured to move integrally. 2. A patent further characterized in that the deviation of the writing location on the magnetic card caused by delay in an amplifier or logic circuit is corrected by shifting the physical position of the magnetic card. A magnetic card device according to claim 1. 3. In a magnetic card device having a standard magnetic stripe fixedly disposed therein for storing clock signals, the standard magnetic stripe is provided with a portion where the interval between adjacent clock signals is different from other areas, and a control circuit is provided. The different parts of the clock signal are programmed and stored in advance in consideration of the different parts of the clock signal, and the clock signal is read and, in synchronization with the read clock signal, necessary writing is written on the magnetic stripe of the magnetic card inserted from the outside. When writing and reading the programmed information, the information is read out according to the program, and when information is read out at an interval different from the programmed interval, the information is determined to be error information, and the clock signal is further read out. The head and the head for exchanging information with the magnetic card are arranged to move together, and in addition to the standard magnetic stripe for storing the clock signal, a stripe for format control information is provided. 1. A magnetic card device, wherein writing of information on a magnetic stripe of a magnetic card is controlled in accordance with the format control information. 4. In a magnetic card device having a standard magnetic stripe fixedly disposed therein for storing clock signals, the standard magnetic stripe is provided with a portion where the interval between adjacent clock signals is different from other areas, and a control circuit is provided. The different parts of the clock signal are programmed and stored in advance in consideration of the different parts of the clock signal, and the clock signal is read and, in synchronization with the read clock signal, necessary writing is written on the magnetic stripe of the magnetic card inserted from the outside. When writing and reading the programmed information, the information is read out according to the program, and when information is read out at an interval different from the programmed interval, the information is determined to be error information, and the clock signal is further read out. The head and the head for transmitting and receiving information to and from the magnetic card are arranged to move together, and furthermore, a self-clocking clock such as phase modulation is provided on the standard magnetic stripe for storing clock information. The magnetic recording medium is characterized in that the clock signal and format control information are written in advance using a writing method that allows the clock signal and format control information to be obtained from one standard magnetic stripe. card device.