JPS623505B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device that performs address control.

In a storage device having a memory module made up of a plurality of memory cards, the memory capacity of the memory card may change. For example, 32 16K bit memory elements are used and arranged in 4 columns x 8 rows.
In storage devices that used up to four 64K-byte (1 byte = 8 bits) memory cards, 32 64K-bit memory elements were used to increase memory capacity by 4 columns x 8 rows. arranged in
For example, when using up to four 256K byte memory cards. In such cases, conventional methods have the following problems. That is, if the memory address data sent to the storage device by a host device such as a central processing unit to specify a memory address is arranged in the storage device taking into account changes in the memory capacity of the memory card, there may be surplus data. In other words, in the above example, considering the case where the maximum memory capacity per memory card is 256K bytes, for example
16 bits for address selection within a 64K bit memory element, 2 bits for selection of memory element rows within a memory card
Assuming that 2 bits are allocated and arranged consecutively for memory card selection, if a memory card with a memory capacity of 64K bytes is used, 16K
Since only 14 bits are needed to select an address within a bit memory element, two middle bits within the memory address data bits are left over. Therefore, the host device uses memory address data corresponding to the memory capacity of the storage device to select an address within a memory element, a memory element column, and a memory card based on the memory address data. There is a problem in that it cannot be performed continuously in bit order.

An object of the present invention is for a host device to select an address within a memory element, a memory element column, and a memory card by using memory address data corresponding to the memory capacity of a storage device. The object of the present invention is to provide a storage device that allows data to be stored continuously in bit order.

The device of the present invention includes: a plurality of storage card means forming a storage module; a storage capacity identification signal generating means for generating a storage capacity identification signal indicating the storage capacity of the storage card; and address switching means for switching the arrangement of address signals in the memory module based on the address switching means.

A feature of the present invention is that by switching the arrangement of memory address data according to changes in the memory capacity of the memory card of the storage device, the host device can use the memory address data according to the memory capacity of the storage device to The purpose of the present invention is to operate so that address selection within an element, selection of a memory element column, and selection of a memory card can be performed continuously in the bit order of the memory address data.

Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, reference number 1 is a central processing unit;
Reference number 2 is a storage device, reference number 36 is comprised of memory cards 37 to 40 (minimum 1 card to maximum 4 cards)
The memory module section is shown. Here, the memory card has a memory capacity of 64K bytes with 16K bit memory elements arranged in 4 columns x 8 rows, and a 256K memory card with 64K bit memory elements arranged in 4 columns x 8 rows.
Two types are used, assuming that they are not mixed with those of bytes. Memory addresses MAD1 to MAD20 sent from the central processing unit 1 for specifying one address of the memory module are connected to an AND circuit 1.
The signal is applied to an address circuit 4 comprising an address buffer circuit 18 comprising AND circuits 6 to 13 and a selection circuit 5 comprising OR circuits 14 to 17. Memory addresses MAD7 to MAD20 are connected to the AND circuit 21 of the address buffer circuit 18.
34 input terminals, respectively, and memory addresses MAD5 and MAD6 are respectively supplied to input terminals of AND circuits 19 and 20 of the address buffer circuit 18 and one input terminal of AND circuits 11 and 13 of the selection circuit 5. The memory address MAD4 is connected to the AND circuits 9 and 1 of the selection circuit 5.
The memory address 3 is applied to one input terminal of the AND circuits 7 and 10 of the selection circuit 5, and the memory address 3 is applied to one input terminal of the AND circuits 7 and 10 of the selection circuit 5.
MAD1 and MAD2 are applied to one input terminal of AND circuits 6 and 8 of the selection circuit 5, respectively. Also, the memory capacity of the memory card used in the memory module 36 is 64K bytes.
A memory capacity signal SELS representing 256 Kbytes is applied to one input terminal of the AND circuits 7, 9, 11 and 13 of the selection circuit 5 and to the input terminal of the NAND circuit 3. The output signal of the NAND circuit 3 is applied to one input terminal of AND circuits 6, 8, 10 and 12 of the selection circuit 5. The output signals of the AND circuits 19 to 34 of the address buffer circuit 18 are sent to the memory card 37 of the memory module 36 as signals CAD1 to CAD16 for selecting addresses in memory elements arranged in the memory card.
~40. Further, the output signals of the OR circuits 16 and 17 of the selection circuit 5 are signals WS1 and WS2 for selecting the memory element rows of the memory card.
The data is sent to the memory cards 37 to 40 of the memory module 46 as the data. The output signals of the OR circuits 14 and 15 of the selection circuit 5 are applied to a decoding circuit 35, and the decoding result of the decoding circuit 35 is used as a signal CS1 to select a memory card of the memory module.
It is sent to the memory cards 37 to 40 of the memory module 36 as CS4.

Next, the operation of this embodiment shown in FIG. 1 will be explained. First, memory card 3 of memory module 36
7 to 40 are arrayed with 16K bit memory elements.
Use one with a memory capacity of 64K bytes. The memory addresses MAD7 to MAD20 sent by the central processing unit 1 to the address buffer circuit 18 are signals for selecting addresses within the memory element via the AND circuits 21 to 34 of the address buffer circuit 18.
One address within the 16K bit memory element of the memory modules 37-40 is selected as CAD3-CAD16. In addition, the memory capacity signal SELS, which indicates that the memory capacity of the memory card is 64K bytes, is positive logic "1" in this case, and the output of the NAND circuit 3 which receives the memory capacity signal SELS as input is logic "0". becomes. As a result, among the memory addresses MAD1 to MAD6 that the central processing unit 1 sends to the selection circuit 5, the output signals of the OR circuits 14, 15, 16, and 17 of the selection circuit 5 are the memory addresses MAD3, MAD, respectively.
4, MAD5 and MAD6 are selected by the selection circuit 5. Of these, memory address MAD5 and
MAD6 selects one of the four memory element columns of the memory modules 37 to 40 as memory element column selection signals WS1 and WS2 for selecting and specifying memory element columns. Also memory address MAD
3 and MAD4 are decoded by the decoding circuit 35, and the decoding result is a signal for selecting a memory card.
One of the memory cards 37-40 of the memory module 36 is selected as CS1-CS4. In this way, the storage device 2 is connected to the central processing unit 1.
selects 1 byte of data at 1 address in the memory module 36 specified by .

Next, the memory card 37 of the memory module 36
~40 arrayed 64K bit memory elements
Use one with a memory capacity of 256K bytes. The memory addresses MAD5 to MAD20 that the central processing unit 1 sends to the address buffer circuit 18 are the AND circuits 19 to 34 of the address buffer circuit 18.
Address selection signal CAD1 in the memory element via
~As CAD16, the memory card 37~4
Select one address within the zero 64K bit memory element. Also, the memory capacity of the memory card is
In this case, the memory capacity signal SELS representing 256K bytes is positive logic and becomes logic “0”.
NAND circuit 3 with memory capacity signal SELS as input
The output becomes logic "1". As a result, among the memory addresses MAD1 to MAD6 that the central processing unit 1 sends to the selection circuit 5, the memory addresses MAD1, MAD2,
MAD3 and MAD4 are selected by the selection circuit 5. Then, in the same way as explained above when using a memory card with a memory capacity of 64K bytes, the memory addresses MAD3 and MAD4 are set to
40 memory element columns, select 1 column out of 4 columns,
Memory addresses MAD1 and MAD2 select one of the memory cards 37 to 40 of the memory module 36. In this way, storage device 2
selects one byte of data at one address in the memory module 36 specified by the central processing unit 1 even when a memory card with a memory capacity of 256 Kbytes is used.

The characteristic operation of the storage device 2, which is an embodiment shown in FIG. Memory addresses MAD7 to MAD20 are selected as addresses within the memory element, memory addresses MAD5,
MAD6 is the memory element row selection, memory address
Arrange MAD3 and MAD4 for memory card selection, and when using a memory card with a memory capacity of 256K bytes, select memory addresses MAD5 to MAD20 in bit order to select addresses within the memory element, and memory address MAD3.
The purpose is to convert the arrangement of memory address data in accordance with changes in the memory capacity of the memory card, such as arranging MAD4 for selecting a memory element column and arranging memory addresses MAD1 and MAD2 for selecting a memory card.

FIGS. 2A and 2B and FIG. 3 show specific means for outputting the memory capacity signal shown in FIG.

In Figure 2 A and B, reference number 101 is a memory card with a memory capacity of 64K bytes, reference number 105
indicates a memory card with a memory capacity of 256K bytes. Reference number 102 indicates an output pin in the reference number 101, reference number 103 indicates an input pin, reference number 106 indicates an output pin in the memory card 105, and reference number 107 indicates an input pin. The output pins 102 and 106 and the input pins 103 and 107 are at exactly the same pin position. Further, the input pin 102 and the output pin 103 in the memory card 101 are short-circuited, and the output pin 106 and the input pin 107 in the memory card 105 are in an open state. Reference number 10
8 indicates a backboard implemented within the storage device, and reference numerals 109 and 110 are output and input pins on the backboard 108.
Next, when the memory card 101 or 105 is mounted on the backboard 108, the output pin 102 or 106 is connected to the output pin 109 and the input pin 103 or 107 is connected to the input pin 110. The output pin 109 is connected to the input terminal of a NAND circuit 111, and the output of the NAND circuit 111 becomes the memory capacity signal SELS. Further, the input pin 110 is connected to ground.

By doing the above, when the 64K byte memory card 101 is mounted on the back board 108, the input terminal of the NAND circuit 111 becomes logic "0" with positive logic, and the memory capacity signal SELS is inverted because of the NAND circuit 111. The logic becomes "1".
Furthermore, when the 256 Kbyte memory card 105 is mounted on the backboard 108, the input terminal of the NAND circuit is a positive logic and becomes logic "1", and the memory capacity signal SELS is inverted by the NAND circuit 111 and becomes logic "0". That is, by using the means shown in FIGS. 2A and 2B, it is possible to output a memory capacity signal representing the memory capacity of the memory card.

Further, as shown in FIG. 3, the switch 112 and the input terminal of the NAND circuit 113 are connected, and the
Let the output signal of No. 13 be the memory capacity signal SELS.
Then, when a memory card with a memory capacity of 64K bytes is installed, the switch is grounded, and when a memory card with a memory capacity of 256K bytes is installed, the switch is left open.
Since the operation is the same as in FIGS. 2A and 2B described above, it can be used as a means for outputting a memory capacity signal representing the memory capacity of the memory card.

Here, we will discuss the effects of the embodiment shown in FIG.
This will be explained with reference to the arrangement of memory addresses in the storage device shown in FIGS. A and B and FIGS. 5A and 5B.

The storage device does not have a configuration that converts the memory address arrangement according to changes in the memory capacity of the memory card as shown in FIG. Arrange the memory addresses as follows. That is, in the storage device shown in FIG. 4A, the memory address MAD
7 to MAD20 is the address selection in the 16K bit memory element when using a memory card with a memory capacity of 64K bytes, and the memory address MAD5 to MAD20 is
When a memory card with a memory capacity of 256 Kbytes is used, the addresses in the 64 K-bit memory element are selected, memory addresses MAD3 and MAD4 are used to select a memory element column, and memory addresses MAD1 and MAD2 are used to select a memory card. Also the fourth
In the storage device shown in Figure B, memory addresses MAD7 to MAD20 are used to select addresses within a 16K bit memory element, and memory addresses MAD1, MAD
2 and MAD7 to MAD20 are address selections within the 64K bit memory element, and memory address MAD5 and
MAD6 is arranged to select a memory element column, and memory addresses MAD3 and MAD4 are arranged to select a memory card.

Here, if the memory addresses in the storage device are arranged as shown in Figure 4A and a memory card with a memory capacity of 64 Kbytes is used, the central processing unit will specify the memory address when specifying the memory address.
It becomes necessary to fix MAD5 and MAD6 to logic "0" and "0" and determine the logic values of other memory addresses. Furthermore, even if the memory addresses in the storage device are arranged as shown in Figure 4B and only one memory card with a memory capacity of 256 KB is used, the central processing unit will logically assign memory addresses MAD3 and MAD4 when specifying the memory address. It becomes necessary to fix the logic values to "0" and "0" and determine the logical values of other memory addresses.

In other words, when the memory addresses in the storage device are arranged as shown in FIG. Address selection within memory, memory element column selection, and memory card selection cannot be performed consecutively in the bit order of memory address data.

However, if the storage device is constructed as in the embodiment shown in FIG. 1, the memory address arrangement can be changed as shown in FIGS. 5A and 5B in response to changes in the memory capacity of the memory card. That is, when the storage device uses a memory card with a memory capacity of 64 Kbytes, the memory address MAD7 to MAD20 is selected as an address within a 16 Kbit memory element, as shown in FIG. 5A.
MAD5 and MAD6 are arranged to select a memory element column, and memory addresses MAD3 and MAD4 are arranged to select a memory card. And storage is 256K
When using a memory card with a byte memory capacity, the memory address is as shown in Figure 5B.
MAD5 to MAD20 select addresses within the 64K bit memory element, memory addresses MAD3 and MAD4
means memory element column selection, memory address MAD
1 and MAD2 are arranged as memory card selection.

Therefore, the central processing unit does not logically fix a part of the memory address data, but uses memory address data according to the memory capacity of the storage device to select addresses within the memory element, and to select memory element columns. The selection and memory card selection can be performed sequentially in bit order of the memory address.

The present invention has the advantage that a host device can use memory address data to successively select an address within a memory element, a memory element column, and a memory card in the bit order of the memory address data. be.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIGS. 2A, B, and 3 are diagrams showing an example of a circuit that outputs the memory capacity signal shown in FIG. 1, and FIGS.
B and FIGS. 5A and 5B are diagrams showing memory address arrays for explaining the effects of the operation of the embodiment of FIG. 1. 1...Central processing unit, 2...Storage device, 3...
NAND circuit, 4...address circuit, 5...selection circuit, 6-13...AND circuit, 14-17...OR circuit, 18...address buffer circuit, 19-
34...AND circuit, 35...Decoder circuit, 3
6...Memory module section, 37-40...Memory card, 101, 105...Memory card, 1
02,106...Output pin on memory card, 1
03,107...Input pin on memory card, 1
08... Backboard, 109... Output pin on the backboard, 110... Input pin on the backboard, 111, 113... NAND circuit, 112...
...Switch.

Claims (1)

[Scope of Claims] 1. At least one storage module having a plurality of storage cards each having a plurality of storage element rows each comprising a plurality of storage elements; and an identification device that generates an identification signal for identifying the storage capacity of the storage element. a signal generating means, M (positive integer) first address lines and N
(a positive integer) number of second address lines are connected, and a signal is supplied to I (an integer greater than or equal to 0 and less than N) of the N second address lines in response to the identification signal; Selecting signals supplied to (M-I) of the M first address lines and supplying these selected signals to the storage module as information specifying the storage card and the storage element array. and address switching means for supplying the signals supplied to the remaining (N−I) of the N second address lines to the memory module as information specifying an address within the memory element. A storage device characterized by comprising: