JPS6235269B2 - - Google Patents
Info
- Publication number
- JPS6235269B2 JPS6235269B2 JP55122626A JP12262680A JPS6235269B2 JP S6235269 B2 JPS6235269 B2 JP S6235269B2 JP 55122626 A JP55122626 A JP 55122626A JP 12262680 A JP12262680 A JP 12262680A JP S6235269 B2 JPS6235269 B2 JP S6235269B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- point metal
- temperature
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法にかかり、段
差のある半導体基板の表面に高融点金属材料を用
いてゲート電極や配線パターンなどを形成する際
に、その段差部分において断線が発生するおそれ
のない方法を提供しようとするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and when forming a gate electrode, a wiring pattern, etc. using a high melting point metal material on the surface of a semiconductor substrate having a step, the step is The purpose is to provide a method that does not cause the possibility of wire breakage.
半導体装置の高密度化、高性能化に伴なつて、
ゲート電極や多層配線の材料として、MoやＷな
どの高融点金属が用いられるようになつて来てい
る。たとえばMoをゲート電極や配線用パターン
に使用する場合、これまで、Moをスパツタ法な
どで半導体基板上に蒸着したのち、ただちにホト
マスク工程でレジストパターンを形成し、CF4に
よるMo膜のドライエツチングを行なつている。
この方法によれば、Mo膜の下地の半導体基板の
表面に段差があると、Mo膜の断線がかなりの頻
度で発生するのが認められる。 With the increasing density and performance of semiconductor devices,
High melting point metals such as Mo and W are increasingly being used as materials for gate electrodes and multilayer wiring. For example, when Mo is used for gate electrodes or wiring patterns, conventional methods have been to deposit Mo on a semiconductor substrate using a sputtering method, immediately form a resist pattern using a photomask process, and then dry-etch the Mo film using CF4 . I am doing it.
According to this method, if there is a step on the surface of the semiconductor substrate underlying the Mo film, it is observed that disconnection of the Mo film occurs quite frequently.
その詳細について、第１図および第２図を用い
て説明する。 The details will be explained using FIG. 1 and FIG. 2.
第１図は段差のある半導体基板上にMo膜を蒸
着法など公知の方法で形成したときの断面図であ
る。図において、１はシリコン基板で、２は選択
酸化膜、３はゲート酸化膜、４はMo膜である。 FIG. 1 is a cross-sectional view of a Mo film formed on a semiconductor substrate with steps by a known method such as vapor deposition. In the figure, 1 is a silicon substrate, 2 is a selective oxide film, 3 is a gate oxide film, and 4 is a Mo film.
Mo膜４の結晶粒の形状をみると、図に示すよ
うに、それは被蒸着面である酸化膜２，３の表面
に垂直な柱状となつている。そのため、酸化膜
２，３の段差部分Ａ，Ｂでは平面部分に比べて
Moの密度が小さく、段差部分Ａ，Ｂでのエツチ
ング速度は平面部分のそれのおよそ３倍となる。 Looking at the shape of the crystal grains of the Mo film 4, as shown in the figure, they are in the form of columns perpendicular to the surfaces of the oxide films 2 and 3, which are the surfaces to be deposited. Therefore, the stepped portions A and B of the oxide films 2 and 3 are larger than the flat portions.
The density of Mo is low, and the etching rate at the stepped portions A and B is approximately three times that of the flat portion.
したがつて、Mo膜４をたとえば第２図に示す
ような帯状のパターンにエツチングすると、パタ
ーン出しされたMo膜４′は上記段差部分Ａ，Ｂで
くびれを生じてしまう。最悪の場合には、この段
差部分Ａ，ＢでMo膜４′が断線してしまう。 Therefore, when the Mo film 4 is etched into a band-like pattern as shown in FIG. 2, the patterned Mo film 4' becomes constricted at the stepped portions A and B. In the worst case, the Mo film 4' will be disconnected at the stepped portions A and B.
この現象は他の高融点金属材料についても同様
のことが言える。 This phenomenon also applies to other high melting point metal materials.
本発明は、MoやＷなどの高融点金属を蒸着し
たのち、高融点金属を蒸着するときの温度より高
温でかつ高融点金属が溶融しない温度までの範囲
の温度で熱処理することにより形状を殆んど変形
することなく高融点金属膜の密度を一定化するこ
とによつて、上述の従来法にあつた問題点を解決
したものである。 In the present invention, after vapor-depositing a high-melting point metal such as Mo or W, the shape is almost completely changed by heat treatment at a temperature higher than the temperature at which the high-melting point metal is vapor-deposited and up to a temperature at which the high-melting point metal does not melt. This method solves the above-mentioned problems of the conventional method by making the density of the high-melting point metal film constant without causing constant deformation.
以下、その一実施例について第３図を用いて説
明する。 An example of this will be described below with reference to FIG.
まず、シリコン基板１１の表面に、公知の方法
で厚さ5000Åの選択酸化膜１２と、厚さ1000Åの
ゲート酸化膜１３を形成する（第３図ａ）。それ
からスパツタ蒸着法で基板温度をたとえば室温に
保つて厚さ3000ÅのMo膜１４を酸化膜１２，１
３上に形成する（第３図ｂ）。このMo膜１４にお
いて、前述したように、Mo結晶粒子は柱状をな
しており、その段差部分Ａ，Ｂ、特に選択酸化膜
１２のバーズヘツドと称される部分Ａでは、Mo
の密度が他の部分におけるそれよりも小さい。次
に、Mo膜１４上にSiO2膜もしくはSi3N4膜１５を
形成してから、N2またはArなどの不活性ガス中
において、前記シリコン基板全体を室温より高温
でMo膜の溶融温度より低温のたとえば900〜1000
℃の範囲内の温度、ですなわち高融点金属である
Moが溶融しない範囲内の温度で熱処理する。こ
の熱処理により、Mo膜１４は第３図ｃに示すよ
うに全体にわたつて一様な密度となる。そのた
め、Mo膜１４の段差部分Ａ，Ｂのエツチング速
度は平面部分のそれと等しくなる。以後、一般に
実施されている方法でMo膜１４をエツチングし
て、帯状のパターンのMo膜１４′とする（第３図
ｄ）。図に示すように、パターン出しされたMo膜
１４′において、段差部分Ａ，Ｂにおけるくびれ
がほとんど認められず、断線のおそれのないもの
である。 First, a selective oxide film 12 with a thickness of 5000 Å and a gate oxide film 13 with a thickness of 1000 Å are formed on the surface of a silicon substrate 11 by a known method (FIG. 3a). Then, using a sputter deposition method, the substrate temperature is kept at room temperature, and a Mo film 14 with a thickness of 3000 Å is deposited on the oxide films 12 and 1.
3 (Fig. 3b). In this Mo film 14, as described above, the Mo crystal grains are columnar, and in the step portions A and B, especially in the portion A called the bird's head of the selective oxide film 12, the Mo crystal grains are columnar.
density is smaller than that in other parts. Next, after forming a SiO 2 film or a Si 3 N 4 film 15 on the Mo film 14, the entire silicon substrate is heated to a temperature higher than room temperature in an inert gas such as N 2 or Ar to the melting temperature of the Mo film. Lower temperature e.g. 900-1000
It is a high melting point metal, i.e. at a temperature within the range of °C.
Heat treatment is performed at a temperature within a range where Mo does not melt. By this heat treatment, the Mo film 14 has a uniform density throughout, as shown in FIG. 3c. Therefore, the etching rate of the step portions A and B of the Mo film 14 is equal to that of the flat portion. Thereafter, the Mo film 14 is etched by a commonly used method to form a band-shaped Mo film 14' (FIG. 3d). As shown in the figure, in the patterned Mo film 14', almost no constriction is observed at the stepped portions A and B, and there is no risk of wire breakage.
なお、上記実施例ではMo膜１４の熱処理に先
立つて、その表面をSiO2膜またはSi3N4膜１５で
コートしたが、この膜１５を形成することなく、
不活性ガス中においてMo膜１４に熱処理を施し
てもよい。ただ、この場合には、Moは酸化され
やすく、またその酸化物は蒸気圧が低く蒸発しや
すいものであるので、十分な注意を必要とする。 Note that in the above embodiment, the surface of the Mo film 14 was coated with the SiO 2 film or the Si 3 N 4 film 15 prior to the heat treatment, but without forming this film 15,
The Mo film 14 may be subjected to heat treatment in an inert gas. However, in this case, sufficient care must be taken because Mo is easily oxidized and its oxide has a low vapor pressure and easily evaporates.
以上説明したように、本発明の方法は、高融点
金属からなるゲート電極や配線を形成するに先立
つて、高融点金属が溶融しない範囲の温度で熱処
理することにより形状を殆んど変形することな
く、高融点金属膜の密度を一定化しているので、
断線のおそれなしに高融点金属膜のパターン形成
が可能となる。したがつて、本発明によれば、高
密度、高性能の半導体装置を歩留りよく製造する
ことができる。 As explained above, in the method of the present invention, prior to forming gate electrodes and wiring made of a high-melting point metal, the shape is almost deformed by heat treatment at a temperature within a range in which the high-melting point metal does not melt. Since the density of the high melting point metal film is kept constant,
Pattern formation of a high melting point metal film is possible without fear of wire breakage. Therefore, according to the present invention, high-density, high-performance semiconductor devices can be manufactured with good yield.
第１図および第２図は従来の半導体装置の製造
方法を説明するための図である。第３図は本発明
にかかる半導体装置の製造方法の一実施例を説明
するための工程図で、図ａ〜ｃは断面図、図ｄは
平面図である。
１１……シリコン基板、１２……選択酸化膜、
１３……ゲート酸化膜、１４……Mo膜、１４′…
…パターン出しされたMo膜、Ａ，Ｂ……段差部
分。
FIGS. 1 and 2 are diagrams for explaining a conventional method of manufacturing a semiconductor device. FIG. 3 is a process diagram for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention, in which figures a to c are cross-sectional views, and figure d is a plan view. 11...Silicon substrate, 12...Selective oxide film,
13... Gate oxide film, 14... Mo film, 14'...
...Patterned Mo film, A, B...stepped parts.
Claims (1)
に前記高融点金属膜を堆積するときの温度より高
温でかつ前記高融点金属膜が溶融しない温度まで
の範囲の温度で前記半導体基板全体に熱処理を施
してから、前記高融点金属膜を所定のパターンに
エツチングすることを特徴とする半導体装置の製
造方法。1 Depositing a high melting point metal film on a semiconductor substrate, and further heat-treating the entire semiconductor substrate at a temperature higher than the temperature at which the high melting point metal film is deposited and up to a temperature at which the high melting point metal film does not melt. A method of manufacturing a semiconductor device, comprising etching the high melting point metal film into a predetermined pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55122626A JPS5745951A (en) | 1980-09-03 | 1980-09-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55122626A JPS5745951A (en) | 1980-09-03 | 1980-09-03 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5745951A JPS5745951A (en) | 1982-03-16 |
| JPS6235269B2 true JPS6235269B2 (en) | 1987-07-31 |
Family
ID=14840613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55122626A Granted JPS5745951A (en) | 1980-09-03 | 1980-09-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5745951A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4973975A (en) * | 1972-11-16 | 1974-07-17 | ||
| JPS5370765A (en) * | 1976-12-07 | 1978-06-23 | Fujitsu Ltd | Production of semiconductor device |
| JPS5546535A (en) * | 1978-09-28 | 1980-04-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of manufacturing semiconductor device |
| JPS56142651A (en) * | 1980-04-07 | 1981-11-07 | Toshiba Corp | Manufacture of semiconductor device |
-
1980
- 1980-09-03 JP JP55122626A patent/JPS5745951A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5745951A (en) | 1982-03-16 |
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