JPS623579B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to automation of position measurement of wire bonding in the assembly process of semiconductor integrated circuits such as ICs and LSIs. Conventionally, in the pellet die bonding process in the assembly process of semiconductor products such as ICs and LSIs, the pellets are quite large in size.
When thermocompression bonding pellets onto a jig called a lead frame, the positioning accuracy is ±100μ or more, so the amount of positional deviation is measured visually by the operator, but this visual work requires that the patterns are extremely concentrated. This caused mental pain to the workers. In addition, in such precision work, a slight measurement error can lead to a decrease in product yield, so a highly reliable automatic position measuring device has been required. A method of using pattern matching to automate such visual inspection work was proposed in Japanese Patent Application Laid-Open No. 49-1989.
No. 111665. However, as mentioned above, ICs and LSIs require fine alignment, and in order to perform conventional pattern matching, it is necessary to perform matching using even finer standard patterns. There is. When such a fine standard pattern is used, the number of pixels to be compared increases, which impedes high-speed processing and requires a larger device to accommodate the number of pixels. An object of the present invention is to provide a position detection device that performs fine alignment at high speed and without requiring a large-scale device. In order to achieve such an object, the present invention provides an input means for inputting a pattern of an object whose position is to be detected, a standard pattern of a plurality of regions having a positional relationship of a predetermined distance and direction from each other, a first detection means for detecting the approximate position of a specific shaped part of the object by comparing the pattern of the object inputted by the means; , a second detection means for setting a plurality of rectangular areas on the pattern of the object, checking the area of a specific level of the object pattern within the rectangular area, and detecting the accurate position of the specific shape of the object; There is a characteristic of becoming. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a semiconductor component, such as an LSI pellet, before wire bonding. In the figure, 1 is an LSI pellet (hereinafter abbreviated as pellet), 2 is a pedestal part of the pellet called a tab, and 3-0, 3-1, ... (some not shown) are inside pellet 1. Bonding pads (hereinafter abbreviated as pads), 4-0, 4-1, etc. are external electrodes that are part of the lead frame, and pads 3-0, 3-1 are not shown in the figure for simplicity. 3-0,3
-1, only two are listed, but external electrode 4-
The same number of pads as 0 and 4-1, in fact about 20 to 40, are provided, and the corresponding pads and external electrodes are connected to each other by wire bonding with gold wires or aluminum wires. The problem here is the variation in the pellet position, ie, the coordinates (X, Y) expressed in rectangular coordinates, and the pellet direction, ie, the angle (θ). In this case, the magnitude of the dispersion, that is, ΔX
and ΔY is ±100 to 150μ, Δθ is about 30′, and in order to perform wire bonding automatically,
It is necessary to detect the position of each pad within ±10μ. In the present invention, for example, as shown in FIG. is a “specific pattern recognition method” that has already been filed by the same applicant as the present invention.
(Patent Application No. 51-14031). Although a plurality of visual field images are required in order to detect the rotational deviation Δθ of the pellet, in order to simplify the explanation, the number of visual field images is set to two for convenience. The size of the visual field image is approximately 600 μ so as to cover the pellet positional deviations ΔX, ΔY, rotational deviation Δθ, etc. In addition, the position of the visual field image is variable,
In order to perform pad detection on pellets of various sizes, the apparatus of the present invention allows the position of each visual field image to be specified arbitrarily. FIG. 3 shows the basic configuration of a position detection device according to the present invention. In the figure, reference numeral 6 denotes a metal plate called a lead frame, and as shown in FIG. 1, the pellets 1 are crimped onto the tabs 2 at a constant pitch. Reference numeral 7 denotes a frame feeding mechanism that intermittently feeds the lead frame 6 in the direction of the dashed arrow shown in the figure, and feeds the pellets 1 one by one directly below the optical system. Further, 8 is a light source for illuminating the pellet, 9 is a semitransparent mirror, 10 is an objective lens for obtaining an enlarged image of the pellet 1, and 1
Reference numeral 1 denotes a reflecting mirror for image division, which divides the enlarged image from the pellet 1 into at least two partial images. The figure shows the case of dividing into two partial images, whereby an enlarged real image of a part of the pellet 1 is obtained at the positions 12-0 and 12-1 shown in the figure. 13-0, 13-1 are relay lenses, 14-
0, 14-1 is a photoelectric conversion device for scanning an optical image and converting it into a temporal analog video signal, and for example, a TV camera such as a vidicon is used.
Reference numerals 15-0 and 15-1 are mounting stands for moving the TV camera, and pellets 1 are moved by moving the photoelectric conversion devices within a plane parallel to the light receiving surfaces of the photoelectric conversion devices 14-0 and 14-1. This is to adjust the position of the field of view depending on the pellet when changing the type of pellet. 16-0, 16-1 are photoelectric conversion devices 15-0,
15-1 is an analog video signal, 17 is a video processing device, analog video signals 16-0, 16-1
Performs binarization, pad detection processing, etc. Reference numeral 21 denotes a control device such as a computer, which controls the data processing and video processing circuit necessary for pad detection processing by sending signals 18,
20 and interface 19. 22 is a frame feeding mechanism 7 and a stage 15-
Drive circuits 0 and 15-1, 23 are circuits for controlling the drive circuit 22, and are connected to the computer via a signal 24, an interface 19, and a signal 20. 25 is an automatic wire bonder, and an image processing device 17
Based on the positions of the pads determined in step 1, a computer 21 determines the positions of all pads, and an automatic wire bonder 25 automatically connects each pad to an external electrode using a metal wire. In this case, if the speed at which the pad position is detected and the speed at which automatic wire bonding is performed do not match, a buffer such as a cassette tape is added to the automatic wire bonder 25 to temporarily store the input signal, and the detection station 26 and the automatic wire bonder 25 A system that combines these offline is also conceivable. Also, if the pad position detection speed is sufficiently faster than the frame feed speed, as shown in Figure 4,
A plurality of detection stations 26 can be controlled with one video processing device and computer. The present invention provides a system in which one video processing device and computer can serve at least four detection stations. Next, an overview of video processing according to the present invention will be described. In FIG. 5, 30 is in the optical system of the present invention.
An analog video of a partially enlarged pellet image obtained from a photoelectric converter such as a TV camera is shown. In the figure, a square portion 31 is an aluminum pad, 32 is an extension of the above-mentioned 31 and is a lead-out portion to the internal wiring, and 33 is a scar from an inspection prober in the previous process. There are pellets of various sizes depending on the variety, but the size of the square portion 31 of the pad is common to all pellets, and is approximately 120 μ□. in this case,
Depending on the type of LSI and the position of the field of view within the pellet, the pull-out portion 32 may extend to either the top, bottom, left or right. Furthermore, although the size of the prober scar 33 is approximately constant, its position within the pad is indeterminate. The peripheral part 34 of the pad 31 is a silicon oxide coating part, 35 is a silicon part at the edge of the pellet, and 36 is a gold-silicon eutectic part outside the pellet. In the case of epi-illumination as shown in FIG. 3, the aluminum part like the pad is the brightest, followed by the silicon part 35 and the silicon oxide part 34 which become darker in that order. Since the gold-silicon eutectic region 36 is inclined in the optical axis direction of the optical system, it is darkest near the pellet as shown in the figure and gradually becomes brighter as it moves away from the pellet. Further, the prober scar 33 is dark because it is depressed. FIG. 6 is a binarized image obtained by converting the analog image 30 of FIG. 5 into a binarized image using the intermediate brightness between the brightness of the aluminum part and the brightness of the silicon oxide part as a threshold value. As shown, the pad 41, the pull-out portion 42, the silicon portion 45, and the portions 46-1 of the gold-silicon eutectic portion 46 that are far from the pellet are white, and the prober scar 43, the silicon oxide portion 44, and the gold-eutectic portion 46 are white. Portion 46 of portion 46 near the pellet 46-
0 is black (hatched part). in this way,
If an analog video signal can be binarized, a relatively simple video processing device can be realized, so in the present invention, the processing target is a binarized video. Further, in the present invention, in order to further facilitate the electrical processing of the image, the binarized image is sampled into 320 pixels in the X direction and 240 pixels in the Y direction, for example, as shown in FIG. In addition, 64 pixels in the X direction and 20 pixels in the Y direction in the same figure.
The picture element part is the return line section, and the X direction 32 in it
The picture element, a band-shaped part of 12 picture elements in the Y direction, is the part where the pulse of the external synchronization signal of the TV camera is output. In addition,
Hereinafter, the video will be sampled every 1 pixel, every 2 pixel, etc. in both the X and Y directions of each divided grid point shown in the figure, and will be referred to as "mode 1", "mode 2", etc. I'll call you. In Figure 7,
The mark indicates sampling in mode 1, and the mark indicates sampling in mode 4. By the way, the basic video processing of the present invention for pad detection consists of four steps: (1) threshold calculation for binarization, (2) macro processing, (3) direction check, and (4) micro processing. , Other processing includes (5) determining mutual positions of pads in each field of view, and (6) calculating positions of all pads. Of these, (1) is a process for determining the intermediate value between the video signal levels of the aluminum part and the silicon oxide part as a threshold value, as described above. (2) is for detecting the approximate position of the pad. (3) is
This is to check whether the pad detected in (2) is actually a drawer protruding in a predetermined direction. Furthermore, the process (4) is for detecting the position of the pad detected in (2) with high precision. These processes (1) to (4) use the video processing circuit of the present invention, and only the data processing necessary for each process is performed by a computer program, whereas (5) and (6) are all performed by a computer program. Let it be processed. Also,
In the present invention, the pellet is moved intermittently, and the above-described image processing is performed while the pellet is stopped. Therefore, during that period, the same video signal is repeatedly obtained from each TV camera. Below, the status of each of the video processing in (1) to (4) above will be outlined. First, change the state of the binarization threshold calculation in (1) to the 8th
As shown in the figure. In the figure, f ₀ (t) and f (t) are analog video signals obtained from a TV camera, and originally f ₀
Assume that what was (t) has changed to f(t) due to drift. As mentioned above, since the pellet is stopped, f(t) can be considered to be a substantially periodic signal (period: about 167 ms) in which the same signal is repeatedly input during the short period shown. In the figure, l ₀ , l ₁ ,
l ₂ and l ₃ are extremely bright parts of the pellet, respectively;
This signal level corresponds to aluminum parts, silicon oxide parts, and extremely dark parts. In the case of epi-illumination, extremely bright areas are specular reflection areas that exist in aluminum parts, gold-silicon eutectic areas, etc., and extremely dark areas are areas near pellets in gold-silicon eutectic areas. It's the dark side. For the purpose of binarization, such signal levels should be ignored. Therefore, we set signal level limits that should be ignored such as l _B and l _W , set a certain threshold value θ _o-1 in the range of l _B to l _W , and set θ _o-1 within this range.
Each video average level Δf _W ⁽ _n
^-1) and Δf _B ^(n-1) , and determine a new threshold value θ _o from each average level as follows. That is, for n=1, 2,...N, θ _o = θ _o-1 + γ{βΔf _W ^(n-1) −(1−β)Δf _B ^(n-1) } …(1) However, , Here, β, 1−β are Δf _W ^(n-1) , Δf _B ^(n-1)
, γ is a coefficient that compensates for the excess or deficiency of the threshold correction amount in the second term on the right side of equation (1), and t _Wo-1 is θ _o-
1 ≦f(t)≦l _W , t _Bo-1 is θ _o-1 ≧f(t)≧l
These are the time intervals that satisfy each of _B. Δf _W ^(n-1) means the difference between the average value of the bright portion and the previous threshold value θ _o-1 . Here, the bright portion is a portion that satisfies the condition that the value f(t) of the image is equal to or greater than the threshold value θ _{o -1} and equal to or less than the level l _W set as an upper limit. The denominator of equation (2) above is the time width of the bright part, and the numerator is the image value f(t) and the threshold value θ _o-
This is the integral of the difference from ₁ . Therefore, the above equation (2) is the difference between the average value of the video value f(t) in the time period t _W ^(n-1) and the threshold value θ _o-1 . Similarly, Δf _B ^(n-1) is the average value for dark parts where the video value f(t) is below the threshold θ _{o -1} and above the level l _B set as the lower limit, and the threshold θ _{o -1} means the difference. {βΔf _W ^(n-1) −(1−β)Δf _B ^(n
-1) } is Δf when θ _o-1 is the temporary origin
The value at the point where the area between _B ^(n-1) and Δf _W ^(n-1) is divided at a ratio of β:1-β is shown. Note that Δf _W was specifically determined as the level of the aluminum portion, and Δf _B was determined as the level of the silicon oxide portion. β means the division ratio for the final threshold values Δf _W and Δf _B. Initially, for example, the silicon oxide part enters at a level higher than θ _o-1 , or conversely, the aluminum part becomes lower than θ _o-1 , so Δf _B ,
Although the value of Δf _W is inaccurate, as the threshold value θ _o becomes more accurate, Δf _B and Δf _W come to accurately reflect the levels of the aluminum part and the silicon oxide part. If γ is 1, it works to find a new threshold using the final distribution ratio for the previous Δf _W and Δf _B , but
If it appears that there is an excess or deficiency in correction based on the state of convergence, it is possible to respond by changing γ. Note that by masking signals outside the time period corresponding to T shown in the figure, the binarization threshold can be determined with even greater accuracy. In this way, when processing only signals in a certain time period, "area gate processing" is performed after that time period. That is, since a time period like T corresponds to a certain rectangular area on the screen, the upper left corner position and the size in the X and Y directions of the rectangle are specified, and only the signals within that rectangle are processed.
In addition, in the above threshold calculation process, since it is acceptable even if the screen sampling is coarse, in the present invention,
For example, sampling should be performed in mode 4 or so. By doing as described above, even if the analog video signal drifts, it is possible to stably follow the threshold value and its drift, and a highly reliable binary signal can be obtained. FIG. 9 shows the processing status of the computer software for operating the binarization threshold calculation processing circuit described above. As shown in the figure, first, at step 50, data necessary for the processing of the threshold calculation circuit is given, and then,
At step 51, the threshold calculation circuit is activated. after that,
The computer enters a waiting state for processing to finish as shown in step 52, but if you do a separate task instead of just leaving the computer waiting during that time, you can significantly shorten the processing time. . Note that 53 is an interrupt request from the threshold calculation circuit to end the processing, which occurs when the video scanning point completely exits the area gate given by 50 (i.e., immediately after passing through time period T in Fig. 8). ), and the computer can move on to the next step 54. 55 is a process for determining the number of iterations of threshold calculation, and n
In the case of <N, n is updated and the process of 50 is repeated again, and in the case of n=N, the threshold value is determined and the process moves on to the next process of 56. As described above, a processing method in which a computer supplies necessary data to a processing circuit, starts it up, and then performs another task while waiting for a termination interrupt is the method of the present invention.
This is a basic form common to video processing in (1) to (4). This makes it possible to make the most of the computer's processing time, which enables high-speed processing, so multiple detection stations as shown in Figure 4 can be handled by a single computer and video processing circuit. It is possible to realize a system like this. Next, the state of macro processing in section (2) will be explained. There are two circuits related to the macro processing of the present invention: (a) a noise removal circuit and (b) a group pattern matching circuit. (a) is for processing noise and quantization errors in the quantized binarized video, and (b) is for detecting the position of the main path of the pad. Here, since detection accuracy is not a problem in either (a) or (b), in the present invention, processing is performed using sampling in mode 4, for example. However, if there is little video noise, the process in (a) may be omitted. FIGS. 10 and 11 show the state of noise removal processing by the circuit (a). In this case, if the binarized video of the pad is sampled in mode 4 or so, the first
A pattern like the one shown in Figure 0 is obtained, but generally 70
Quantization errors at pattern boundaries such as −0, 70-1, and 70-2 and minute noises such as 71-0 and 71-1 occur. However, when paying attention to the pellet pattern, it consists almost entirely of components parallel to either the X or Y direction, with exceptions such as the prober scar 43 and the drawn-out portion 42. Therefore, for example, for each point in the quantized image, a cross-shaped area (consisting of i picture elements in both the X and Y directions) that has only components parallel to the X and Y directions, such as 72 in FIG. If we consider that, if it contains white picture element i-1 or more, it becomes white, and if it contains less than i-1 picture element, it becomes black.
A pattern like the one shown is obtained. However, the figure is an example where i=5. If this conversion is performed, the pad 41, the drawer part 42, the blowbar scar 43, etc. in FIG. 10 will become like 61, 62, and 63 shown in FIG. can be removed. However, if i is made too large, the shape of the pad may change significantly when noise is present near the pad, so in the case of LSI pellets, i = about 5 is considered appropriate. Therefore, although relatively large noise and quantization errors can be slightly reduced, it is difficult to completely eliminate them. Next, FIG. 12 shows the state of group pattern matching processing by the circuit (b). As shown in the same figure,
In both directions, for example, four square areas (standard pattern) with a width of 5 pixels 73-0, 73-1, 73
-2 and 73-3 are scanned on the image plane after noise removal using a pattern 73 that is integrated with their relative positions preserved, and the target pattern in each area and the black and white standard as shown are Determine whether it matches a pattern. As shown in the figure, providing a mask pattern is
This is to reduce the influence of large quantization errors that could not be removed by noise removal and the inclination of the pad due to rotational deviation of the pellet. In this way, if the patterns match in three or more of the four areas and are within the designated area gate, that point is extracted as a pad. for example,
For pad 61 with prober scar 63 in the lower right corner as shown, areas 73-0, 73-
When the centers of 1 and 73-2 pass through features such as point A, point B, and point C, they match the respective black and white standard patterns, so a "pattern detection" signal can be issued at that timing. . The coordinates of the scanning point of the camera are determined by X, Y counters 322 and 324, which perform basic clock frequency division, as shown in FIG.
It is obtained by That is, since the camera is driven by the values of the X and Y counters, the scanning point of the camera and the values of the X and Y counters match, and the coordinates of the scanning point of the camera can be determined. The camera scanning point and the matched cutting position are in a predetermined positional relationship, and each of the four square areas also has a predetermined relative positional relationship, so from the coordinates of the camera scanning point, A It is possible to calculate the coordinates of feature points such as point B, point B, and point C. In this case, although there are a plurality of points A to C, one point each is shown in the figure for simplicity. Now, the black and white standard pattern of each area is S(u,v), and the mask pattern is M
(u, v), a certain point (X, Y) on the quantized image plane and the corresponding target pattern in the area U are (X+u, Y+v), then the pattern at the point (X, Y) is Whether they match or not is determined by the following logical function J
All you have to do is check whether (X, Y) holds. Here, is exclusive OR, 〓 is logical product,

[Formula] represents the logical sum of all picture element information in area U, and 〓〓 represents logical negation. The distance in the X and Y directions between each area is determined by the size of the pad, that is, the magnification of the detection system. If the area size is 5 pixels x 5 pixels, K _X = K _Y = 3 (pixel ) is appropriate. However, in addition to the large quantization errors and pad inclinations that cannot be completely removed using the above mask pattern alone, there are actually additional distortions such as deflection distortion of the TV camera and distortion of the optical system. Therefore, in the present invention, taking these influences into consideration, the distance between regions is set to K _x ±1 (picture element), K in the X direction as shown in FIG.
A width of _Y ±1 (picture element) is given, and each distance combination is (K _X , K _Y ), (K _X -1, K _Y -1), (K _X +1, K
Group pattern matching that satisfies the following three conditions _(Y + 1) is simultaneously determined. As described above, all pads are extracted in slightly larger quantities by providing a variation tolerance range for the distance between regions within the pattern 43. That is, for example, points near extraction points A, B, and C in FIG. 12, such as points A', B', and C', are also extracted. Therefore, in the group pattern matching circuit, the position of the extracted pad and how it was extracted, in other words, in which region out of the four regions and at which distance between the regions, matching was achieved (this process is performed in matching mode) This is called a determination of pads) and is temporarily stored in a buffer memory, and a computer program is used to combine (bind) adjacent pads. Therefore, the operation of the computer program is as shown in FIG. As shown in the figure, similar to the threshold calculation process,
The group pattern matching circuit performs a pad extraction operation while in a waiting state for the completion of processing, and the waiting state can be canceled by a processing end interrupt request 77, and the process can proceed to the next processing 78. Next, change the state of the direction check process in item (3) to the first
It is shown in Figure 5. As shown in the figure, this process consists of four points located d (picture elements) outside the pad feature points (points A, B, and C in the example in the figure) extracted by the macro process in (2). A rectangle 80 with lengths a (picture element) and b (picture element) in the longitudinal direction and short direction, respectively.
Assuming -0, 80-1, 80-2, 80-3,
This is to count the white area within each rectangle. Then, the white area within the rectangle in a predetermined direction (the right direction in the example in the figure) is greater than or equal to a predetermined threshold value S ₀ , and the white area within the rectangle in the other three directions is less than or equal to a predetermined threshold value S ₀ ' Determine whether or not. With such a determination, even if a pad is mistakenly detected in the group pattern matching process (2), it can be rejected and only a predetermined pad can be reliably extracted. In the present invention, among the above direction check processes,
The process of counting the white area within the four rectangles is performed by a dedicated device, and the other processes are performed by a computer program. Further, in the direction check processing as described above, it is desirable to prepare a plurality of white area counters and operate them in parallel in order to speed up the processing. In the present invention, for example, four white area counters are grouped together as a "white area counter group", and an area gate and a rectangle for white area counting as shown in FIG. 16 are specified. In other words, generally take the S _* point above all rectangular figures for white area counting (small Y coordinate), and use this S _* point as a reference to set the point _S0 at the upper left corner of each rectangle.
~Coordinates of S ₃ and lengths in the X and Y directions (a ₀ , b ₀ ) ~
Give (a ₃ , b ₃ ). In this case, the coordinates of S _* are (X
_S , Y _S ), the coordinates of S ₀ are (X _S +X _S0 , Y _S +y _S0 ),
_The coordinates of S ₁ are (X _S + X _S1 , _{Y S} + _{y S1 )} , the coordinates of S ₂ are ₍ X _S +
x _S3 , Y _S +y _S3 ). By doing this, among all the rectangles, the point E where the video scan ends is automatically determined by the white area counter group, and the area inside the broken line shown in the figure becomes an area gate.
As a result, after the video scanning point passes point E, the white area counter group can be operated again, and the processing of multiple white area counter groups within the same screen can be performed in real time (that is, within the same field).
There is an advantage that it can be done with FIG. 17 shows the operation of a direction check program using such white area counter group D. Next, FIG. 18 shows the state of microprocessing in item (4). As shown in the figure, each feature point of the pad extracted by the macro process (2) (point A, point B in the figure)
In the vicinity of point C), at a distance of c (picture element), the long and short directions are f (picture element) and g (picture element).
Assume a rectangle with length and count the white area within each rectangle. Based on the position of the detected feature point,
The position of each rectangle is calculated by a computer and sent to white area counters 111 and 112. The number of rectangles at each feature point is, for example, two rectangles each at right angle corners such as points A and C (but they are perpendicular to each other), and one rectangle at a ridgeline such as point B, and the number of rectangles is always black and white in the longitudinal direction. It is necessary to take the size of f so that the pattern changes. The white area within each rectangle assumed in this way takes a value that depends on the position of the feature point extracted by macro processing. From the white area of each rectangle, it is possible to find the position of the boundary line of the part and the positions on the boundary line, such as A ₀ point, B ₀ point, and C ₀ point. In other words, by dividing the white area within each rectangle by the length g of the rectangle in the short direction, you can find the length of the white part in each rectangle, and use this value as the coordinate of the known edge of each rectangle. By adding , the coordinates of the pad boundary line position can be calculated. The above microprocessing can use the white area counter group M as in the direction check in section (3).
All you have to do is change the position and size of the assumed rectangle. In addition, in the group pattern matching circuit of the macro processing in section (2), if there is a match in three or more of the four areas, that point is extracted as a pad.
In the micro processing, each rectangle is provided according to the matched feature points (points A, B, and C in the figure). FIG. 19 shows the operation of the program for micro processing. In the figure, the white area counter group M is a group of four white area counters, for example, and may be the same as the white area counter D described above.
It may be a separate item. If they are made the same, the scale of the apparatus will be reduced, but the processing will take longer because the processing must be performed sequentially, such as performing direction check processing and then micro processing.
On the other hand, if they are separate, the scale of the device will be somewhat larger, but simultaneous processing is possible and the processing time will not be long. In this embodiment, the white area counter groups D and M are provided as separate circuits to perform high-speed processing. In addition, the white area counter group M is shared with the processes 92 and 96 in the same figure, but this is the same because there is sufficient time during the transition of image scanning from the upper feature point to the lower feature point. This is because micro processing can be completed within the field time, and the white area counter group M can be used effectively. FIG. 20 shows an example of multiple operations of the four processes (1) to (4) above. However, the figure shows one detection station, two TV cameras, one binarization threshold calculation circuit, one group pattern matching circuit, and a group of white area counters (four white area counters each).
This is the case of two units. Here, among the numbers j-k written in the figure showing each process, j indicates the detection operation trial circuit, k indicates the process using the TV camera number (0, 1), and the number between each process is The arrows each indicate activation by a processing end interrupt of the processing circuit. In addition, the arrows between the fields of the threshold calculation process (binarization process) in (1) represent the repeated operation of threshold calculation, and in this case, the threshold value is determined from the analog video signal from each camera. This means that three fields are spent on each field.
Furthermore, the arrow in the middle of micro processing in (4) means restarting the white area counter group. The reason why the macro processing in (2) is started from the beginning is as follows. (i) In the case of LSI pellets, there is little variation in pellet reflectance, so in practice the threshold for binarization does not suddenly change. (ii) Therefore, it is highly likely that the threshold applied to the binarization of the previous pellet can also be applied to the pellet currently being investigated. (iii) Furthermore, since the binarization process takes a total of 6 fields, waiting for the calculation of the threshold value for the pellet currently being examined will slow down the process. However, the purpose of the binarization process in (1) is to find a threshold that follows very slow changes due to video signal gain and DC level drift, so this process also requires activation. It is necessary to apply Therefore, as a video processing circuit, the threshold calculation circuit and the binarization circuit in (1) are separated into separate circuits, and the threshold of the binarization circuit is given independently from the threshold calculation circuit. be able to do so. Also, after the macro processing in (2) is completed, the direction check processing in (3) and the micro processing in (4) are started at the same time because the position of the pad is roughly given by the macro processing. This is because information on this position is sufficient for both microprocessing, and a plurality of predetermined rectangles can be generated. As described above, if the "judgment" in (5), that is, the two-view rationality check passes, it is possible to detect pads using the previous threshold value, but the threshold calculation in (1) Since only the threshold corresponding to TV camera 0 has been completed yet, the next TV camera 1
Wait until the threshold calculation corresponding to is completed. However, if the test fails, the macro processing→direction check processing and micro processing may be started again at the stage when a new threshold value is determined as shown in the figure.
In this way, pad detection can be performed in 6 fields (=100 ms) when the first judgment is passed, and in 8 fields (=133 ms) when the second judgment is passed. If it is desired to further shorten the processing time, the number of each processing circuit may be increased. However, since the above processing time is sufficiently short compared to the time for frame feeding, writing to a cassette tape, or wire bonding, it does not pose a practical problem in a detection system where n=4 in FIG. In each of the above processes, some processing was performed by computer programs, but since most of the processing is as simple as calculating coordinates, the calculator can be replaced with a microcomputer, or if you are willing to increase the scale of the equipment, it can be realized with dedicated equipment. . Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 21 shows the video processing device 17 in FIG.
1 shows an example of the basic configuration of the device of the present invention, including a portion 19' of the interface 19 related to the video processing device. In this figure, the number of detection stations in FIG. 4 is 4, the number of threshold calculation circuits is 1,
The number of group pattern matching circuits is 1, and the number of white area counter groups consisting of 4 white area counters is 2.
This is an example of a configuration in the case of . In the same figure, 16-i _S -i _T
(i _S =0 to 3, i _T =0, 1) is an analog video signal from the i _T -th TV camera of the i _S -th detection station. Reference numeral 100 denotes a video pre-processing circuit, which performs DC reproduction, deflection distortion correction, shading correction, and binarization processing of an analog video signal from a TV camera. That is, the signal correction circuit 101 in the video preprocessing circuit 100 is a circuit that performs DC reproduction, deflection distortion correction, and shading correction of an analog video signal, and in this case, conventional methods are used for all three. 1
02 is a binarization circuit, 103 is a threshold variable Schmitt circuit, 104 is a D/A converter, and 105 is a register, which performs the binarization threshold calculation process described in (1) above. The threshold value found by
Write THRi _S i _T to one of the registers 105 and hold the value. Therefore, by processing as shown in FIG. 9, the threshold value THRi _S i _T that follows the drift change of the analog video signal VIDi _S i _T is determined from the output of the register 105, that is, the output of the D/A converter 104. The signal can be supplied to the Schmitt circuit 103, and a stable binary video signal BNRi _S i _T can always be obtained. On the other hand, analog video signal
As shown in the figure, VIDi _S i _T is input to the threshold calculation circuit 107 via the selector 106, and threshold calculation processing is performed. In this way, in the present invention, since the threshold calculation circuit for binarization and the binarization circuit are separated, the 20th
The video processing described in the figures can be performed simultaneously. In addition, the 2 obtained from each Schmitt circuit 103
The digitized video signal BNRi _S i _T is passed through the selector 106 to the noise removal circuit 109 and the white area counter group D1.
11, the white area counter group M112 is sequentially supplied as signals NBNR, DBNR, and MBNR. From each video preprocessing circuit 100, BNRi _S 0,
Although two types of binary signals are supplied as in BNRi _S 1, the selector 106 can arbitrarily specify a 2:3 signal connection relationship. Further, it is assumed that there is no signal connection relationship that straddles each video preprocessing circuit 100, and the selector 106
, the number of the video processing circuit, that is, the number i _S of the detection station is specified. The signal connection relationship as described above is written from the computer to the register 108 via the interface 19' and is provided to the selector 106 as an SEL signal. In addition, the output of the noise removal circuit 109
The PBNB is supplied to a group pattern matching circuit 110 to extract pads with coarse accuracy. Thus, as shown in the figure, the threshold calculation circuit 107, the group pattern matching circuit 110, and the white area counter group D1
11. Data transfer of white area counter group M112,
The interface 19' controls startup and interrupts.
This is done via Note that 113 is a synchronization distribution circuit that supplies synchronization signals necessary for each circuit shown in the figure and each TV camera, a signal representing the coordinates of a scanning point, etc. In the above description, the binarized video signal is given to the group pattern matching circuit 110 via the noise removal circuit 109, but if the video has little noise, the noise removal circuit is not necessarily required. A detailed explanation of the above video processing circuit can be found at HITAC.
An example of each circuit when connected to a small computer such as -10 (product name) will be explained. In addition,
Even in the case of a general computer, it can be realized using roughly the same idea as the following embodiment. FIG. 22 shows an embodiment of the interface 19' when connected to a small computer HITAC-10. In the figure, the register controller 120 is
It is used to write and sense the status of each register 105, 108 in FIG. 21. Under the condition that the register controller 120 is selected by the signals DVN and SQL, the following three operations are commanded by the signal ODR. specified by circuit 122. First, the WTHR instruction is for writing a threshold value into the binarization threshold register 105 shown in FIG. 21, and the WSEL instruction is for writing the signal connection relationship of the selector 106 into the selector register 108 shown in FIG. , the DSEL instruction is for detecting the signal connection status. Note that STR1 is a strobe signal for executing a register write instruction. Thus, data is transferred via the DOT signal when a register write command is issued, and via the DIN signal when a register state sense command is issued. Next, the channel controller 12 in FIG.
3. The video processing controller 126 will be explained. device selection circuits 124 and 127 in both circuits;
The functions of the operation command circuits 125 and 128 are the same as those of the register controller 120. The channel controller 123 performs high-speed data transfer between (1) threshold calculation circuit (2) group pattern matching circuit (3) white area counter group D (4) white area counter M and the computer, and performs image data transfer. The processing controller 126 is for controlling the operating states of the four processing circuits mentioned above. Channel controller 123 input power signal
CNT0 is a control signal for high-speed data transfer between the channel controller 123 and the computer, CNT1
is a control signal for data transfer between the channel controller 123 and the above four processing circuits, CNT2
is a control signal between the channel controller 123 and the video processing controller 126. In addition, the input/output signal CNT of the video processing controller 126
3 is a signal for controlling the operating states of the four processing circuits mentioned above, such as activation, operation, and termination. Output signal of channel controller 123
CHNINT is an interrupt request signal and is set when data transfer is completed. Video processing controller 12
The output signals IMP and INT of 6 are also interrupt request signals, and are set when any of the above four processing circuits completes processing. Both of the above interrupt request signals pass through an OR circuit as shown in the figure, and notify the computer of the interrupt request as an INT signal. As a result, the computer generates an instruction to sense the interrupt factor, and uses the FLG signal to recognize which device the interrupt request came from. FIG. 23 shows embodiments of the register 108 and selector 106 shown in FIG. 21. Register 108 is 7
For example, in the figure, the 5th and 6th bits are the detection station numbers (00) ₂ to (11) ₂ , and the 4th bit is the binary circuit number (0) ₂ , (1). ) ₂ as the analog number (0) that should be input to the threshold calculation circuit 107 at the 3rd bit.
₂ , (1) The binarized video signal number to be input to the group pattern matching circuit, white area counter group D, and white area counter group _M in order at the 2nd bit, 1st bit, and 0th bit is as follows. This is an example when each is allocated. The writing strobe to this register 108 is the WSEL command, and the reading strobe is the DSEL command.
Do it by command. First, the analog video signal VIDi _S i _T is selected by the analog selector 130 as either i _S or i _T (i.e., detection station number and TV camera number) using the STN SEL signal and the TVD SEL signal.
Threshold calculation circuit 1 in Figure 21 as TVID signal
07. Also, the binary video signal BNRi _S i _T
The detection station number i _S specified by the STN SEL signal is selected by the decoder 131, and the AND circuit group 132 selects PTM SEL, DRC.
SEL, MIC Each SEL signal causes a noise removal circuit, white area counter group D, and white area counter group M.
Binarized input signal NBNR, DBNR, MBNR for
Select. With the above configuration, the various video processing described above can be performed simultaneously by simply specifying an appropriate numerical value for the contents of one register from a computer. Figure 24 shows the channel controller 1 in Figure 22.
This is an example of No. 23. The general structure is as above.
Since it is almost the same as the HITAC10 direct mode high-speed interface standard product, explanation of the same parts will be omitted. The difference from the standard product is that each processing circuit has an input/output buffer, and there is a channel status register that indicates which of the four processing circuits data is being transferred to. 140 was established. Specifically, the number i _P (=
Bits 0 to 4) are set by the SCHN instruction. The KCHN instruction senses interrupt flag 142,
CCHN instruction clears interrupt flag 142,
The ACHN instruction sets the WAR (word address register) 143, the RCHN instruction transfers read data, and the WCHN instruction transfers write data.
The number of transferred words is set in WCR (word counter register) 144 by the WCHN instruction. Next, an outline of the operation of the channel controller shown in FIG. 24 will be explained using FIG. 25. Note that the details are the same as those of the HITAC-10 high-speed interface (direct mode), etc., so the explanation will be omitted. First, use the SCHN command to set the channel status.
Turn on the i-th _P bit of register 140,
CHN Specifies the processing circuit to be transferred as a BSY signal. Next, the address in the computer's memory is set to WAR in FIG. 24 by the ACHN instruction.
Note that the order of the SCHN command and the ACHN command may be reversed. Next, when the data transfer is a write operation, (a)
When the WCHN command and the RCHN command in (b) are issued during a read operation (hereinafter (a) means a write operation and (b) means a signal operation accompanying a read operation), the 24th
The number n of data to be transferred to the WCR 144 in the figure is set. As a result, WRITEMODE in Figure 24
Flip-flop 149 is “1” in case (a)
In case (b), it is set to "0". From then on, high-speed data transfer via this channel began.
After n data transfer is completed as shown in (ADDR IN), the interrupt request signal CHN INT is set. The computer issues the KCHN instruction, recognizes that it is an interrupt request from this channel like CHN FLG, and then issues the interrupt request signal CHN INT with the CCHN instruction.
Clear. At the same time, in the case of (a), the 24th
The AND gate 145 in the figure outputs a pulse to the i _P bit of IMP STRT to activate the corresponding processing circuit, and in the case of (b), the AND gate 146 in FIG. 24 outputs a pulse to the i _P bit of IMP STOP. is issued to stop the operation of the processing circuit, and in either case, the channel status register 140 is reset by the OR gate 147. In addition, in Figure 24, TIM, REQ,
PMTin, ADDR IN, DATA IN (input side),
The DATA OUT (output side) and RQL0 signals correspond to CNT0 in FIG. 22. Also,
R, SLCT is a decoded WCR as shown in the figure, and is a register switching signal at the time of reading. In addition to this, DATA OUT (output side), DATA IN
(input axis) and CHN BSY signals are
Corresponds to CNT1 in the figure. Furthermore, IMP STRT,
Each IMP STOP signal corresponds to CNT2 in FIG. 22. FIG. 26 shows an example of the video processing controller 126 shown in FIG. 22. The video processing status register 150 shown in the figure is for controlling the operation of the four processing circuits, and is used as described above.
The _iPth bit of this register is set and reset by the _iPth bit signal of IMP STRT and IMP STOP, respectively, and the corresponding circuit is controlled by the output signal IMP BSY. In addition, in the 151 flag register, under the condition that the i _P bit of the IMP BSY signal is set (that is, the processing circuit corresponding to i _P is in operation) as shown in the figure, the i _P bit of the IMP END signal is set. When a pulse comes, this flag
The i _Pth bit of register 151 is set.
Therefore, when any processing circuit finishes its operation, an end interrupt request signal is output from the output of OR gate 152. 154 is a mask register, and the MIMP instruction is used to control the set/reset of this register 154. When two or more processing circuits generate termination interrupt requests at the same time, it ensures smooth computer processing for each interrupt request. It is something to be done. KIMP is also a termination interrupt sense command.
CBSY is a specific bit clear instruction for the flag register 151, and DBSX is a status sense instruction for the flag register 151. Furthermore, RPTM is an instruction for controlling reading of parameters of a group pattern matching circuit, which will be described later. Next, FIG. 27 shows an example of the operation of the video processing controller shown in FIG. 26. ADDR IN in Figure 27
(a) and (b) indicate that the channel controller is transferring write and read data, and as mentioned above, after the write data transfer is completed, IMP STRT, after the read data transfer is completed, and IMP STOP, each i _P bit is A pulse appears. First, in response to the IMP STRT pulse, the output of the video processing status register 150, that is, the IMP
The i _P bit of BSY is set, and the processing circuit corresponding to i _P enters the operating state. After that, the processing circuit performs the specified operation, and when the operation is completed, the IMP
A pulse is output to END, and IMP is output as shown.
Flag register 1 under the condition that BSY is set.
If the 51st _iP bit is set and the mask register 154 is reset, a processing end interrupt request is issued from IMP INT. This causes the computer to send a KIMP instruction,
The fact that this is an interrupt request from the video input/output controller is recognized by the return of a pulse to the IMP FLG. The computer then issues a MIMP instruction to set the mask register 154 to prohibit other interrupt requests, and then issues a CIMP instruction to clear the i _P bit of the flag register 151. In this case, if there are no other interrupt requests,
IMP INT is reset. Along with this, the computer performs read data transfer using the channel controller as shown in (b). At the end of the read data transfer, a pulse is generated from the preprocessing circuit corresponding to i _P at the i _P bit of IMP STOP, and the video processing status register and therefore the i _P pit of IMP BSY are reset. At the same time, the computer resets the mask register again using the MIMP instruction to permit other termination interrupt requests. The operation of the processing circuit can be controlled in the above manner, but as shown in the above explanation,
Since the computer can perform other work for a while after the i- _P pit of IMP BSY is set, if the processing circuit corresponding to the number other than i _P is started, multiple processing Circuits can be activated simultaneously. FIG. 28 shows an embodiment of the binarization threshold calculation circuit 107 of FIG. 21. In the figure, the analog video signal TVID is connected to the sample hold circuit 16.
0, converted into a digital signal by an A/D converter 161 and stored in a latch register 162.
XCP/4 and its delayed signal are clock signals for this sample and hold circuit 160, A/D converter 161, and latch register 162. On the other hand, the area gate circuit 163 is a circuit for gating a specific rectangular area on the screen, and the terminal signal THR AREA is the gate signal. The write data transfer control of this circuit is controlled by CHN
This is done by BSY0 and DATA OUT, that is, the channel controller, and from the terminal of the area gate circuit 163 via the AND gate 164 to the area parameter latch register 165, the signal level limits l _W and l _B to be ignored, and the latch register 166 are sent. The initial value θ ₀ of the threshold value is set respectively. Comparators 167 and 168 are f and l, respectively.
It is used to compare the magnitude relationship between the values of _W・f and l _B , and is “1” when f<l _W and f>l _B , respectively.
becomes. Therefore, the output of the AND gate 169 becomes "1" when the video signal f is inside the designated area and l _W >f>l _B. 171 is an adder, which includes a latch register 162 and a knot circuit 170.
, and sends out an output with a value of f-θ ₀ . Furthermore, 172 and 173 are circuits that calculate the "brightness integral" corresponding to the numerator of equations (2) and (3), 174 and 1
75 corresponds to the denominator of equations (2) and (3). “Time integral”
When f≧θ, AND gate 176 opens and gates 172 and 174 operate, and f<
When θ, the AND gate 177 opens and 173,1
75 works. Brightness integration circuit 172, 173
The configuration can be realized by an adder and a latch register 178 as shown in the figure, and one input of this adder has f-θ ₀ and the other input has a latch register 178.
All you have to do is feed back the output of Thus, at the end of the predetermined threshold value integration operation, IMP END0 is output from the terminal of the area gate circuit 163.
A signal pulse is sent out, and the latch register 17
8, 179 are predetermined brightness integral values Fn, Gn, and counters 174, 175 are predetermined time integral values.
An and Bn are stored. Note that IMP STRT0 is a signal for resetting the counters 174 and 175 before performing an integrating operation. Each piece of data obtained in this way is sequentially read out by the channel controller. That is,
The read strobe pulse DATA IN is ANDed with CHN BSY0 by AND gate 180,
Each data selected by the AND gate 181 by the R SLCT signal is
The output of 0 is used as a read strobe and is sequentially read out via the NAND gate 182. The calculator calculates the formula based on the above four parameters.
(2) and (3), calculate a new threshold value θ ₁ in equation (1), set the contents of the latch register 166 as θ ₁ , have the threshold calculation circuit repeat the same process, and n The threshold value θ _N obtained when =N is given to the register 105 in FIG. Thus, from the output of the Schmitt circuit 103 shown in the figure, a binary signal having a threshold value of θ _N can be obtained. FIG. 29 shows an embodiment of the area gate circuit 163 of the present invention, in which the area-related parameters are
According to the diagram. Moreover, FIG. 30 shows the waveform of the main part of FIG. 29. In FIG. 29, latch registers 190, 191, 192, 193 are
This is for setting _S , _ys , a, and b. That is, a write strobe pulse from the channel controller is applied from the terminal, and each data is set from the terminal, for example, in series or in parallel as shown in the figure. On the other hand, the , terminals are for starting (initializing) the counters 194 and 195, and a pulse is applied at the timing when the screen scan becomes X=X _S and Y=Y _S in FIG. 16, and each counter is reset.
When the processing circuit corresponding to i _P enters the operational state, the terminal IMP BSYi _P turns on as shown in part A of Fig. 30, and the terminal X clock and terminal Y clock turn on AND gates 196 and 197, respectively. The counters 194 and 195 perform counting operations. Therefore, the comparators 198 and 199 send out pulses at the timings of X=X _S +x _S and Y=Y _S +y _S , respectively. Accordingly, counters 200 and 201 are reset, and flip-flops 202 and 203 are set. After that, counters 200 and 201 start operating, and X=X _S +x _S +a, Y=Y _S
Comparator 20 at the timing when +y _S +b
The output pulse is sent from 4,205, and the flip
Reset flops 202 and 203, respectively. Therefore, from the output or terminal of the AND gate 206, X _S +x _S ≦X as shown in FIG.
An ARER signal that is turned on in the time zone of the area ≦X _S +x _S a, Y _S +y _S ≦Y≦ Y _S +y _S +b is obtained. Further, the output of the AND gate circuit 207 is as shown in part B of FIG. ₃₀ , as shown in _FIG .
Since the pulse is sent out at the timing of Y=Y _S +y _S +b, a pulse indicating the end of area scanning is sent out from the terminal by the delay 208. Note that the terminal is an output terminal when data written by the channel controller spans the next stage circuit (for example, see FIG. 28). FIG. 31 shows the noise removal circuit 109 of FIG.
This is an example. This figure is an example in which the cross-shaped area in the principle explanation of FIG. 10 is set to five pixels in both the X and Y directions. In the figure, a shift buffer 210 is a series input serial output type shift register group having a memory capacity of four horizontal scanning lines (raster) of the screen, and the length of each register 211 is XCP/4, for example, mode 4 sampling. If a clock is used, it is 96 bits. On the other hand, the cutting buffer 212 is XCP/4
5 pixels from the screen as the sampling clock
This circuit cuts out an area of 5 picture elements, and is equipped with five 5-bit length serial input parallel output type shift registers 213, and each output of the shift register 211, including the input signal NBNR, is connected to each shift register in parallel. 213. This is information in which the X coordinate on the screen is the same and the Y coordinate is continuous, for example in mode 4. The output of the extraction buffer 212 is a signal corresponding to the cross-shaped area in FIG. 10, and the number of "1"s in the adder 214 having nine 1-bit inputs is counted in parallel. On the other hand, 215 is a register for presetting the threshold value, and this output and the adder 21
4 is compared with the output of the comparator 216,
If ≧, the output PBNR of the comparator 216 becomes “1”. The signal NBNR obtained in this manner is a signal from which pattern quantization errors and small isolated noises have been removed, as described above. FIG. 32 shows another embodiment of the noise removal circuit 109 of FIG. 21, and the difference from the embodiment of FIG. 31 is that a RAM (Ramdom Access
An equivalent circuit is realized using the memory) 217. If a shift register is used as a shift buffer, there is no existing one with a length of exactly 96 bits as in the present invention, so it must be realized by combining shift registers of an appropriate length, such as 64 bits + 32 bits. As a result, the number of ICs increases. Compared to this, when using RAM, the length can be freely determined and the number of ICs can be reduced. FIG. 33 shows the control operation of the RAM shown in FIG. 32. The value of the RAM address signal ADDR in the same figure is
It is updated every time a pulse of XCP/4-α is output, and changes from 0 to 95 in one raster scanning time of the screen.
The W/R signal is used to designate writing/reading of the RAM, and "0" indicates reading and "1" indicates writing. RAM STRB is a strobe signal for writing and reading RAM, and BFFR STRB is a strobe signal to buffer register (D-type flip-flop) 218. As shown, XCP/4
In the first half of each -α pulse, all addresses of the ADDR value (information in the RAM 217) are written to the buffer register 218 below. Next, in the second half, the information read from the buffer register 218 is sent to the shift register 213 and written to the same address in the next stage RAM. This action
By repeating every pulse of XCP/4,
RAM can be used as a shift register. Since the subsequent processing is exactly the same as the processing shown in FIG. 31, the explanation will be omitted. Note that the extraction buffer 212 can also be realized by using four latch registers having signals as bit components instead of the serial input parallel output type shift register 213 in the extraction buffer 212 in FIGS. 31 and 32. can. Also, an adder 214, a threshold preset register 21
5. Instead of the comparator 216, it is also conceivable to convert the signal into a current value, and then convert the result of analog addition of the current into a binary value using a Schmitt circuit. Furthermore, in general, in order to realize an extraction buffer of i picture elements+j picture elements, it is sufficient to construct a shift buffer consisting of j-1 serial input serial output type shift registers or RAMs. Noise removed signal obtained as above
The PBNR is provided to the next group pattern matching circuit. FIG. 34 shows an example of the basic configuration of the group pattern matching circuit 110 in FIG. 21. 2 in the same figure
10 or shift buffers 0 and 2, and 22
0, that is, shift buffer 1 is shown in FIGS. 31 and 32.
As shown in the figure, 4, 4, and 15 serial input serial output type shift registers or
Consists of RAM. In addition, 212, that is, cutting buffers 0, 1, 2, and 3 are shown in FIG. 31 and 3.
As in FIG. 2, it is composed of five serial input/parallel output type shift registers or latch registers. Here, the role of the shift buffers 210, 210, 2 is to obtain continuous information in parallel with the same X coordinate on the screen and mode 4, for example, in the Y coordinate, as in the case of the noise removal circuit. Also, 2
20, that is, the role of shift buffer 1 is
The purpose is to give the Y-direction spacing between each standard pattern in the figure. 212, that is, cutout buffers 0, 1, 2, and 3 are for providing target patterns of each region in FIG. 12, that is, PKUPs 0, 1, 2, and 3. 221, that is, partial pattern matching circuits 0, 1, 2, and 3 are target patterns PKUP in each area.
0,1,2,3 and standard pattern STND0,1,
2, 3 and MSK 0, 1, 2, 3 (see equation (4)), and each output PTM
0, 1, 2, and 3 are "1" if the target pattern and the standard pattern match, and "0" if they do not match. Furthermore, the matching shift circuit 222
As shown in Fig. 13, this is a circuit that determines the geometric distance between each region, and by relatively delaying the matching results PTM0, 1, 2, and 3 in the X direction, 220° in the Y direction. That is, by selecting either one of the YTAP signals sent from the shift buffer 1, the respective distances are determined. Note that MTCHij is the determination result. The matching mode determination circuit 223 performs the aforementioned matching mode (ie, matching method) determination process, and MTCH MODE is the determination result. As the screen is scanned in this way, the determination results MTCH MODE and the screen coordinates X/4 and Y/4 that are matched are temporarily stored in the memory buffer 224. Further, the area gate circuit 163 is a circuit for generating a signal PTM AREA for gating so as to extract only pads in a designated area. In this way, the number N of pads within the designated area on the screen and the extraction result PAD are transferred to the computer. Although the above configuration uses one area gate circuit, if it is desired to gate an area with a more complicated shape for video processing reasons, a plurality of area gate circuits may be used. Hereinafter, embodiments of each circuit constituting the group pattern matching circuit 110 in FIG. 21 will be described. First, FIG. 35 shows an embodiment of the partial pattern matching circuit 221 shown in FIG. 34, and shows an example of a partial pattern matching circuit of 5 pixels×5 pixels. In the figure, 230 and 231 are registers for the standard pattern and mask pattern, each with 5 registers as shown in the figure.
It consists of 5 latch registers (5 bits). The registers are connected in series as shown, and each data is written by the channel controller. In other words, the write strobe signal DATA OUT is set to AND gate 2 under the condition of CHN BSY1.
32, data is transferred from the left to the right of each latch register. PKUPi is a two-dimensional signal of the target pattern,
The outputs of each latch register and the corresponding ones of the standard pattern register 230 are exclusive-ORed in an exclusive OR (EOR) circuit matrix, and each result is sent to the next NAND circuit matrix 234. Each NAND circuit is an open collector as shown in the figure, and the NAND result of each exclusive OR result and its corresponding mask pattern is wired-ORed at the output section as shown in the figure, and the NAND circuit 2
35, the pattern matching result signal PTMi
is obtained. FIG. 36 shows an embodiment of the matching shift circuit 222 of FIG. 34. Latch register 24
1,242 is for storing "distance -1" between the areas in FIGS. 12 and 13, that is, K _X -1, K _Y -1, and each data is written by the channel controller. That is, similar to FIG. 35,
CHN BSY1 and DATA OUT are AND gate 24
0 and a write strobe signal is applied to its output. Note that this part is the same as in FIG. 35, so the AND gate 232 in FIG.
The output signal may be used as a strobe signal for the latch registers 241 and 242. The output of latch register 241, that is, _K
are given to selectors 244 and 246, respectively
One of the signals obtained by delaying PTM2 and PTM0 by serial input parallel output type shift registers 243 and 245 is selected. In addition, the output of the latch register 242, that is, K _Y -1 is the selector 2
47 and select one of the output TAP signals of shift buffer 1 shown in FIG.
Outputs YSEL signal. Matching result PTM3 is the same signal as MTCH30, and regarding matching result PTM2 corresponding to point _P30 in FIG. The output of
The signals delayed by one picture element and delayed by two picture elements by the shift register 248 are sequentially transmitted to MTCH20, 21,
22, which corresponds to points P ₂₀ , P ₂₁ , and P ₂₂ in FIG. Matching result PTM1 is each two RAM2
49 and buffer memory 250 by 2 rasters, PTM 1 itself is delayed by 1 raster,
Each signal delayed by 2 rasters is sent to MTCH10, 1 in turn.
1 and 12, which correspond to points P ₁₀ , P ₁₁ , and P ₁₂ in FIG. Regarding PTM0 of the matching result, similarly, two RAMs 249, buffer memories 250 and 251, and a serial input/serial output shift register 252 are used to output the output of the selector 246, 1 raster + 1 picture element delay, 2 raster + 2 picture element delay, Each signal corresponds in turn to points P ₀₀ , P ₀₁ , and P ₀₂ in FIG. 13. As described above, each matching result is
It is possible to create a spatial correspondence as shown in the figure. Also, as in the case of the noise removal circuit 109,
A shift register may be used in place of RAM 249 and buffer memory 250 in the shift buffer of this circuit. FIG. 37 shows an embodiment of the matching mode determination circuit 223 shown in FIG. 34. The AND gate circuit groups 260, 261, and 262 in the same figure determine whether three or more of the four partial pattern matchings are successful. That is, the AND gate 263 in each AND gate circuit group becomes 264 when all four partial patterns are matched.
265 is when only the upper left corner of Figure 12 cannot be matched, 266 is when only the lower left corner is not matched, and 267 is when only the lower right corner is not matched. When the output is not reached, the output becomes "1". The AND gate circuit groups 260, 261, and 262 have distances between each region in _{FIG .}
-1), (K _X ×K _Y ), (K _X +1) × (K _Y +1) group pattern matching. Each output of these AND gate circuit groups 260, 261, 262 passes through an OR gate 268 and is output to an encoder 2.
69 is encoded into 3 bits. The 1 bit output from this OR gate 269 and the 3 bits of the code, a total of 4 bits, correspond to 4 bits for three types of distances between regions.
This is temporarily stored in the latch register 270 as ×3=12 (bits) information. On the other hand, the outputs of the three OR gates 268 are applied to the OR gate 271 as shown, which detects that at least one of the AND gates 263 to 267 has become "1", that is, a pad. It means what you did. Then,
The flip-flop 272 is set and the DTCT signal becomes "1". In addition, the latch resistor 270
The output represents the matching, and the MTCH
It is sent as a MODE signal to the memory buffer described next. FIG. 38 shows an embodiment of the memory buffer 224 of FIG. 34. If a pad is detected, the third
This shows how to find the pad explained in Figure 6.
MTCH MODE and its pad screen coordinates (X/
4, Y/4) must be transferred to the computer. In FIG. 38 and FIG. 39 showing the operation of each part, when a pad is detected under the condition of PTM AREA="1" (that is, DTCT="1"),
When a pulse is generated at XCP/4-ε ₀ , the flip-flop 280 is set, the AND gate 281 is opened, and the MTCH MODE data is transferred to the memory buffer 2.
Sent to 83. Furthermore, if a pulse is generated at XCP/4- _ε1 , the flip-flop 280 is reset, the AND gate 282 is opened, and the binary data (X/4, Y/4) of the screen coordinates is transferred to the memory buffer 28.
Sent to 3. The pulses of XCP/4-ε ₀ and XCP/4-ε ₁ are
Since it appears one by one in the time width of DTCT="1",
By or gate 284, and gate 285
The value of the up-down counter 286 is increased by 2 each time DTCT="1". On the other hand, the memory buffer 283 has multiple RAMs 28 as shown in the figure.
Each bit of MTCH MODE or (X/4, Y/4) data is
Compatible with RAM. Now, if a pulse is output from the AND gate 283, the flip-flop 287 is set and the RAM is
289 write operation, or gate 288
The contents of the up-down counter 286 are written to the address of the RAM 289 using the pulse from the up-down counter 286 as a strobe. Here, the delay 290 is determined by the timing of the first strobe pulse for writing.
This is to ensure that RAM addresses start from 0. Therefore, MTCH MODE is stored in the even addresses of the RAM 289, and (X/4, Y/4) is stored in the odd addresses. Next, the operation in the case of reading will be explained. RPTM
When a command (see FIG. 26) is issued, first, the contents of the up-down counter 286 (that is, the value 2N, where N is the number of pads detected) are read into the computer via the AND gate 291. As a result, the computer reads 2N pieces of data at high speed using the channel controller. In other words, the read strobe pulse
DATAIN is ANDed with CHN BSY1 by AND gate 292, and under the condition that PTM AREA="0", this strobe pulse is
93 and causes the up-down counter 286 to go down. At the same time, the flip-flop 287 is reset to specify the RAM read operation, and the contents of the up-down counter 286 are
From the RAM address, using the output pulse of the OR gate 288 as a strobe, the AND gate 294
Read sequentially via . The purpose of the delay 295 is to ensure that the RAM address is set from 2N-1 at the timing of the first strobe pulse for reading. Therefore, this read operation depletes the RAM.
It is read out in order from 2N-1 to 0. With the circuit configuration as described above, a group pattern matching circuit can be realized. Next, FIG. 40 shows the white area counter group D111 (or white area counter group M112) shown in FIG.
An example is shown below. Since the circuit configurations of white area counter groups D and M are exactly the same, the circuit numbers, signal names, etc. related to counter group D are shown in the figure, and those related to counter group M are shown in parentheses. Parameter writing of this circuit is also performed under the control of the channel controller. That is, CHN
BSY2(3) and DATA OUT are AND gate 300
Using the output as a write strobe, data is serially written into, for example, area gate circuit 163, ie, area gate circuits 3, 2, 1, 0 and latch registers 302 and 301 as shown.
However, the data in the latch registers 301 and 302 are X _S and Y _S (mode 1) in FIG. 16. Comparators 303 and 304 each have X=X
When _S , Y=Y _S , each area gate circuit 1
The X and Y counters in 63 are reset through the terminals, and the flip-flops 305 and
Set 306. Therefore IMP BSY2(3)
="1", the AND gate 307 opens at the timing when X=X _S and Y=Y _S , and all area gate circuits 163 are activated by the terminal. On the other hand, the mode 1 clock pulse XCP,
YCP is added from the terminal to operate the X and Y counters of all area gate circuits 163. Since each area gate circuit becomes "1" while scanning each area shown in FIG. 16, the AND gate 308 receives the XCP pulse in that time period, and When the signal DBNR (MBNO)=“1”, that is, the target pattern is white, an output is sent out and counted by the counter 309. In this manner, each area gate circuit 163 sends out a pulse from its terminal at the end of area scanning to set the flip-flop 310. Therefore, all flip-flops 31
AND gate 311 at the timing when 0 is set
becomes “1”, and the flip-flops 305, 30
6,310 and send out a pulse from IMP END2(3). In this way, 309 or counter 0,
1, 2, and 3 are the white area values of each area S ₀ , S ₁ , S ₂ , S ₃
However, each data is read out sequentially by the channel controller. That is, CHN BSY2
(3) and DATA IN are added to AND gate 311, and its output is used as a read strobe.
Each data selected by RSLCT and the AND gate 312 is sequentially read out via the NAND gate 313. FIG. 41 shows an embodiment of the synchronous distribution circuit 113 of FIG. 21. In the same figure, 320 is, for example, 6M
A Hz pulse oscillator 321 is a shaping circuit for pulse width conversion, and is connected as shown in the figure along with X, Y counters 322, 324 and decoders 323, 325. Note that the waveform of this main output signal is shown in FIG. Here, XCP is the output of the shaping circuit 321 and is 6MHz
pulse, YCP is the output value of the decoder 323 is 3
It is sent once every 84 times. i.e. 15.7KHz
This is the pulse of External synchronization signals for HD, VD, or TV cameras are provided by flip-flop 3.
26, 328 and waveform shaping circuits (for level and polarity conversion) 327, 329 as shown in the figure.
In addition, SYNC, that is, an external synchronization signal for monitoring, is sent to the flip-flops 330, 331 and the EOR circuit 33.
2 and waveform shaping circuit (for level and polarity conversion) 3
33, it becomes as shown in the figure. XCP/4 is the mode 4 sampling clock pulse;
36, a pulse is generated every time the value of the X counter is a multiple of 4 only when the value of the Y counter is a multiple of 4.
On the other hand, YCP/4 is an and gate 335, 337
Therefore, a pulse is output only once every time the value of the Y counter is a multiple of 4. Note that FIG. 43 shows a more detailed signal waveform diagram. 338 to 341 in Fig. 41 are delays or delay groups, and assuming that each delay time is as shown in the figure, XCP, XCP/4, RAM STRB,
Regarding W/R, it is as shown in Fig. 43. In addition
BFFR STRB is omitted in both figures. Furthermore, X ₀ and Y ₀ in Figure 41 are each X=
This is a signal that outputs a pulse at the timing of X ₀ , Y=Y ₀ . As explained above, in the present invention, all main parts are realized by hardware, and the computer only performs simple coordinate calculations.
A highly reliable automatic position detection device can be provided, and its effects are significant.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a pellet of IC, LSI, etc. before wire bonding, Fig. 2 is an explanatory diagram showing the field of view set on the pellet, Fig. 3 is an explanatory diagram showing the basic device configuration of the present invention, and Fig. 4 is an explanatory diagram showing the field of view set on the pellet. The figure is an explanatory diagram of a configuration example of a position detection system to which the present invention is applied, Figure 5 is an analog video diagram of a partially enlarged image of a pellet obtained from a photoelectric converter, and Figure 6 is a binarized image of Figure 5. figure,
Fig. 7 is an explanatory diagram of an example of video sampling in the present invention, Fig. 8 is an explanatory diagram of the principle of threshold calculation for binarization, and Fig. 9 is a computer program for performing the threshold calculation of Fig. 8. Explanatory diagram, Figure 10, Figure 11
Figure 12 is a diagram explaining the principle of noise removal processing, Figure 12 is a diagram explaining the principle of group pattern matching processing, Figure 13 is a diagram explaining the combination of areas for group pattern matching processing, Figure 14 is Figure 12, Figure 13 is a diagram explaining the principle of group pattern matching processing. Fig. 15 is an explanatory diagram of the computer program for performing the group pattern matching process shown in Fig. 15. Fig. 15 is an explanatory diagram of the principle of direction check processing. Fig. 17 is an explanatory diagram of a computer program for performing the direction check process shown in Fig. 15, Fig. 18 is an explanatory diagram of the principle of micro processing, and Fig. 19 is an explanatory diagram of a computer program for performing the micro processing shown in Fig. 18. , 20th
FIG. 21 is an explanatory diagram showing an example of a multiplex operation for operating the device of the present invention, FIG. 21 is an explanatory diagram of an example of the basic device configuration of the present invention in the position detection system of FIG. 4, and FIG. equipment small computer
A connection diagram showing an example of the configuration of the interface section when connected to HITAC10, Fig. 23 is a connection diagram showing an example of the register and selector in Fig. 21, and Fig. 24 shows an example of the channel controller in Fig. 22. The connection diagram shown in Fig. 25 is Fig. 24.
Operation explanatory diagram of the channel controller shown in Fig. 26
The figure is a connection diagram showing an embodiment of the video processing controller in FIG. 22, FIG. 27 is an explanatory diagram of the operation of the video processing controller in FIG. 26, and FIG.
A connection diagram showing an example of a value threshold calculation circuit,
Fig. 29 is a connection diagram showing an embodiment of the area gate circuit, Fig. 30 is an operational explanatory diagram of the main part of Fig. 29,
31 is a connection diagram showing an embodiment of the noise removal circuit in FIG. 21, FIG. 32 is a connection diagram showing another embodiment of the noise removal circuit in FIG. An explanatory diagram of control operation, FIG. 34 is a connection diagram showing an embodiment of the group pattern matching circuit in FIG. 21, FIG. 35 is a connection diagram showing an embodiment of the partial pattern matching circuit in FIG. 34,
36 is a connection diagram showing an embodiment of the matching shift circuit in FIG. 34, FIG. 37 is a connection diagram showing an embodiment of the matching mode determination circuit in FIG. 34, and FIG. 38 is a connection diagram showing an embodiment of the matching shift circuit in FIG. 34. 39 is an operation explanatory diagram of FIG. 38, FIG. 40 is a connection diagram showing an example of the white area counter group in FIG. 21, and FIG. 41 is a synchronous distribution diagram in FIG. 21. Connection diagrams showing an example of the circuit, FIGS. 42 and 43 are signal waveform diagrams in FIG. 41. 1...ISI pellet, 2...Tab (pedestal part),
3-0, 3-1... bonding pad, 4-
0, 4-1... External electrode, 5-0, 5-1... Visual field image, 6... Metal plate (lead frame), 7...
Frame feeding mechanism, 8... light source for pellet illumination,
9...Semi-transparent mirror, 10...Objective lens, 11...
Reflector, 13-0, 13-1...Relay lens,
14-0, 14-1, 15-0, 15-1...Photoelectric conversion device, 16-0, 16-1...Analog video signal, 17...Video processing device, 19...Interface, 21... Control device (computer), 22
... Drive circuit, 23 ... Control circuit, 25 ... Automatic wire bonder, 26 ... Detection station.

Claims (1)

[Claims] 1. Conversion means for converting an object whose position is to be detected into a two-dimensional pattern signal, means for binarizing the two-dimensional pattern signal, and a specific pattern portion on the two-dimensional pattern of the object. means for sampling a partial pattern at a predetermined relative position with respect to the sample at a first sampling interval and storing it as a standard pattern; means for sampling at sampling intervals and sequentially cutting out partial pattern signals from the sampled two-dimensional pattern signal; and sequentially comparing the standard pattern stored in the storage means with each of the partial patterns sequentially cut out by the cutting means. means for calculating a position of a rectangular area that should straddle the boundary line of the specific pattern portion located at a predetermined relative position with respect to the position of the partial pattern for which the comparison means detects a match; and 2 of the object. A dimensional pattern signal is sampled at a second sampling interval smaller than the first sampling interval, and from the sampled signal one of two values belonging to the rectangular area and determined by the binarization means is obtained. 1. A position detection device comprising: means for calculating the number of picture elements having a pixel value; and means for detecting a boundary line position of the specific pattern portion based on the calculation result. 2. The storage means samples a plurality of partial patterns located at predetermined relative positions with respect to a specific pattern portion on the two-dimensional pattern of the object at the first sampling interval, and stores the plurality of sampled portions. The cutting means stores signals of a plurality of partial pattern groups having the same relative positional relationship as the relative positional relationship between the plurality of partial patterns, respectively. means for sequentially cutting out a plurality of partial pattern groups while shifting their positions, and the comparing means is a means for simultaneously comparing each of the plurality of cut out partial patterns with one of the corresponding standard patterns. A position detection device according to claim 1.