JPS623583B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a wiring method for a semiconductor device.

Conventionally, in semiconductor integrated circuits, an insulating layer is formed on a semiconductor substrate on which predetermined circuit elements are formed.
A metal layer such as aluminum or a semiconductor layer such as silicon is formed on the insulating layer by vapor deposition, sputtering, vapor phase growth, etc., and then photolithography is used to remove only the metal layer or semiconductor layer in the portion that will become the wiring path. Wiring was formed by leaving some parts and removing other parts. In order to prevent the surface of the semiconductor device from coming into direct contact with the outside air, the entire surface of the semiconductor device was coated with an insulating layer, except for the areas where the external electrodes were taken out.

Conventionally, in this semiconductor device, the side surfaces of the wiring path are exposed at least during the manufacturing process from forming the wiring path to covering the wiring path with an insulating layer, and even after the device is completed, the insulating layer covering the wiring path is exposed. It is difficult to obtain a completely strong and dense insulating layer using any method other than thermal oxidation, not only for those without an insulating layer, but also for those with an insulating layer, so dirt can enter from the sides of the wiring path, impairing the stability of the device, and damaging the semiconductor device. Reliability decreased. Further, a first metal layer or a semiconductor layer is formed on the main plane on which a predetermined circuit element of the semiconductor substrate is formed, with an insulating layer interposed therebetween, a first wiring path is formed by photolithography, and the first wiring path is formed by photolithography. A semiconductor device having a multilayer wiring structure has also been proposed in which the top surface is covered with an insulating layer, a second metal layer or a semiconductor layer is formed, and a second wiring path is formed again by photolithography. In this device, there is a step on the surface of the device due to the thickness of the first wiring path itself, and when an insulating layer is applied thereon, the insulating layer becomes thinner or breaks at this step. For this reason, the first wiring path and the second wiring path were sometimes short-circuited. Also, when forming the second metal layer or semiconductor layer, the first wiring path itself may be thinned or cut at a step, or when forming the second wiring path by photolithography, this step may be removed. There was also the inconvenience that etching progressed quickly at the point where the second wiring path could become disconnected. For the various reasons mentioned above, it has been almost impossible to manufacture a highly reliable multilayer wiring structure with a high yield in conventional semiconductor devices.

Furthermore, when making ohmic contact between a conductivity type region in a semiconductor substrate and a wiring path, an opening must be provided in the insulating film on the substrate, and the position of this opening is Must be within the area. This is because, if even a slight opening is made across the area, the wiring layer will cause a short circuit between the base and the area. Therefore, extremely high accuracy is required in determining the position of the openings, which necessitates providing the above-mentioned area somewhat large, which is also one of the causes of a decrease in the degree of integration.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a multilayer interconnection structure that is difficult to infiltrate with external dirt, is stable and highly reliable, and allows for a smaller device area.

A feature of the present invention is that a thin insulating film having an opening reaching the region is formed on a semiconductor substrate provided with a region of one conductivity type, and an insulating film thicker than the thin insulating film is formed on the semiconductor substrate adjacent to the region. The thin insulating film is formed by forming a semiconductor layer continuously on the thin insulating film, in the opening, and on the thick insulating film, and selectively thermally oxidizing the semiconductor layer. A step of forming a first layer wiring pattern of a wiring path made of the semiconductor layer from above to the thick insulating film, and forming a thermal oxide film converted from the semiconductor layer to be deposited on the side surface of the wiring path. introducing an impurity of one conductivity type into the semiconductor substrate from the upper surface of the wiring path through the wiring path and the opening; The method of manufacturing a semiconductor device includes a step of covering with a thermal oxide film, and after forming a contact hole in the thermal oxide film, a second layer wiring pattern made of aluminum is formed on the thermal oxide film.

According to the manufacturing method of the present invention, the side surfaces of the wiring path made of semiconductor are not exposed, and the side surfaces and top surface of the wiring path can be covered with a strong and dense thermal oxide film, so that dirt cannot enter from the outside. A semiconductor device with excellent stability and high reliability can be obtained. Furthermore, in the semiconductor device obtained by this invention, a thermally oxidized insulating layer is embedded between the wiring paths,
The surface of the semiconductor device is almost flat with only the unevenness present, and therefore, this semiconductor wiring path is used as the first wiring path, and an insulating layer is coated on this, and a second wiring path is further formed on this. , a multilayer wiring structure can be easily formed. In this case, since the insulating layer on the first wiring path can be formed substantially uniformly and uniformly, short circuits between the first wiring path and the second wiring path will not occur, and the photograph for forming the second wiring path will not occur. Since the etching method can be easily performed, the thickness of the second wiring path is uniform and uniform, and no disconnection due to undesirable etching or the like occurs. This second wiring path may be formed of a metal layer by photolithography, similar to conventional wiring. It can be seen that with the multilayer wiring structure having such a configuration, a highly reliable semiconductor device can be easily realized with a high yield.

Furthermore, in the manufacturing method of the present invention, when making ohmic contact between a region having a conductivity type in a semiconductor substrate and a wiring path, the conductivity type of the impurity added to the wiring path and the conductivity type of the region are made to be the same type. By selecting this, it is possible to add this impurity into the semiconductor substrate through the wiring path, so even if the part of the wiring path that contacts the above region is partially outside the above region, the impurity can be diffused through the wiring path. This makes it possible to successfully establish an ohmic contact between the area and the wiring path. This means that the margin for element arrangement can be increased and the area of the element itself can be reduced. Therefore, according to the wiring of the present invention, it is possible to realize a semiconductor device with a smaller element area and higher integration density with greater margin.

Next, an embodiment in which the present invention is applied to an insulated gate field effect semiconductor device, which is considered to be particularly effective when the present invention is applied, will be described in detail with reference to the drawings.

In FIG. 1, the same reference numerals represent the same elements, and a source region 2 and a drain region 3, which are P-type diffusion regions, are formed in an N-type single-crystal silicon substrate 1. In FIG. These regions are formed and a silicon dioxide layer 4 is formed on the main plane of the substrate 1 by thermal oxidation. A silicon dioxide layer 4 is etched using standard photolithographic masking and etching techniques to make ohmic contact between the source region 2 and the drain region 3.
After making an opening as shown in FIG. 1A, a P-type silico layer 5 of about 1 micron was formed thereon by vapor deposition, sputtering, vapor deposition, or the like. Next, a silicon nitride film 6 is formed as a non-oxidizing insulating film on this by vapor phase growth, and then other parts except for the silicon nitride film 6 on the silicon layer 5, which is to become a wiring path, are formed by standard photolithography. was removed.

By further performing thermal oxidation, as shown in FIG. A wiring path (source electrode 7, gate electrode 8, drain electrode 9) was formed. Since the thickness of this silicon dioxide layer 10 was about 2.4 microns, 1.4 microns of this thickness was removed by etching to make the silicon dioxide layer 10 and wiring paths 7, 8, and 9 on the same surface, and then the silicon nitride film 6 was removed. Next, by thermal oxidation,
The surface of the semiconductor device was coated with silicon dioxide 11 as shown in FIG.

During the above-mentioned two thermal oxidations (formation of 10 and 11), P-type impurities in the silicon wiring layers 7 and 9 are introduced into the P-type source and drain regions 2 and 3 through the conductive holes, and the wiring layers and Good ohmic contact with the above region is achieved.

In the above embodiment, the silicon layer 5 was doped with P-type impurities, but after the silicon layer 5 without any impurities was deposited,
At the stage shown in FIG. 1B, impurities may be selectively introduced from the outside by diffusion in order to lower the resistance of the wiring layers 7, 8, and 9. In such a case, the ohmic contact between the regions 2 and 3 and the wirings 7 and 9 will be better than in the above embodiment. Of course, at this time, the diffused impurities are introduced through the openings.

In the insulated gate field effect transistor manufactured in this manner, the wiring paths 7, 8, and 9 are buried in the silicon dioxide layer, so that the side surfaces of the wiring paths are not exposed, and the insulating layer covering the wiring paths This thermally oxidized silicon is much stronger and denser than insulating layers formed by evaporation, sputtering, vapor phase growth, etc., resulting in excellent stability and high reliability. A semiconductor device having the above structure is obtained.

According to the above method, as shown in FIG. 2, an insulating layer is formed on regions 2 and 3 in order to make ohmic contact between the diffusion regions (source region 2, drain region 3) in the single crystal silicon substrate 1 and the wiring path. 4, even if the position of the hole is not completely within the area 2, 3 and extends slightly, the wiring path 7,
When performing diffusion to lower the resistance of 8 and 9, impurities are diffused into the single crystal silicon substrate 1 through the silicon layer 5, forming regions 17 and 18, and these regions 17 and 18 become regions 2 and 3. Successful electrical contact was established with each of them. In this case, the impurities are introduced into the wiring paths 7, 8, and 9 in the first
As explained in the drawing, it is of course possible to use a silicon layer containing impurities when depositing the silicon layer in advance. Therefore, in the wiring of the semiconductor device of the present invention, there is a large degree of latitude in determining the position for making ohmic contact between the diffusion region and the wiring path, and the area of the diffusion region can be reduced to the necessary minimum, thereby reducing the degree of integration of the device. will improve dramatically.

After FIG. 1C, holes are drilled in the silicon dioxide 11 by standard photolithography to provide ohmic contact between traces, as shown in FIG. 3A, and then aluminum is deposited over the entire surface. A wiring path 12 is formed by standard photolithography and covered with an insulating layer 13 to form a multilayer wiring structure.

In such a semiconductor device, when aluminum is deposited on the entire surface to form the wiring path 12, the unevenness existing on the surface of the semiconductor device is almost entirely due to the insulating layer 4, and the surface is almost flat, so the thickness of the aluminum is Since uniformity and uniformity are guaranteed over the entire surface, and the photolithography method for forming the wiring path 12 can be performed easily and accurately, a stable and reliable multilayer wiring structure can be easily produced with a high yield. I was able to make it happen.

Although not an embodiment of the present invention, FIGS. 1C to 3
A method as shown in Figure B is also conceivable. That is, after drilling holes in the silicon dioxide 11 by standard photolithography in order to establish ohmic contact between the wiring paths in the state shown in FIG.
A silicon wiring path 15 is formed as shown in FIG. A multilayer wiring structure was created using the following methods.
In such a multilayer wiring structure, wiring paths can be overlapped in many layers because multilayer wiring hardly increases the unevenness on the surface of the semiconductor device.

The embodiments described above are for illustrative purposes only, and
The present invention is not limited to these. For example, although the present invention is applied to an insulated gate field effect transistor in the above embodiment, it is generally applicable to unipolar type field effect semiconductor devices, field effect semiconductor integrated circuit devices, etc. The present invention can be applied to any so-called planar semiconductor device, such as a semiconductor device or a bipolar semiconductor device. Further, instead of single crystal silicon, semiconductor materials such as germanium and gallium arsenide can be used, and as the insulating layer 4, instead of silicon dioxide formed by thermal oxidation, silicon dioxide formed by thermal oxidation, vapor deposition, sputtering, vapor phase growth, etc. can be used. Silicon oxide, silicon dioxide, silicon nitride film, alumina, phosphorus glass, etc. can also be used. Further, instead of the silicon layer used as the wiring layer, a semiconductor layer of germanium, gallium arsenide, etc. formed by vapor deposition, sputtering, vapor phase growth, etc. can also be used. Furthermore, the dimensions and conductivity type of each part of the semiconductor device can be freely selected. Furthermore, it is also possible to use a partial combination of the wiring structure of the present invention and the conventional wiring structure within one semiconductor device.

[Brief explanation of the drawing]

FIGS. 1A, B, and C, FIGS. 2 and 3A are process cross-sectional views showing embodiments of the present invention. Figure 3B
FIG. 2 is a cross-sectional view showing technology related to the present invention. 1: Semiconductor base, 2: Source region, 3: Drain region, 4: Insulating layer, 5: Semiconductor layer, 7, 8,
9: Wiring, 10: Thermal oxidation insulator.

Claims (1)

[Claims] 1. Forming a thin insulating film having an opening reaching the region on a semiconductor substrate provided with a region of one conductivity type, and forming an insulating film thicker than the thin insulating film on the semiconductor substrate adjacent to the region, A step of continuously forming a semiconductor layer on the thin insulating film, inside the opening, and on the thick insulating film, and selectively thermally oxidizing the semiconductor layer, forms the thick insulating layer from above the thin insulating film. The first wiring path made of the semiconductor layer that reaches the top of the film
A step of forming a pattern of layer wiring and forming a thermal oxide film converted from the semiconductor layer to be deposited on the side surface of the wiring path, and adding an impurity of one conductivity type from the top surface of the wiring path to the wiring path and the wiring path. a step of introducing into the semiconductor substrate through the opening; and a step of introducing the semiconductor layer into the semiconductor substrate through the opening;
A process of covering the upper surface of the wiring pattern of the second layer with a thermal oxide film of the semiconductor layer, and forming a contact hole in the thermal oxide film, and then forming a second wiring pattern of aluminum on the thermal oxide film. A method for manufacturing a semiconductor device, characterized in that: