JPS623584B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a building block type integrated circuit in which an LSI (Large Scale Integrated Circuit) is designed using a computer.

Conventionally, when designing an LSI using a computer, a so-called building block method as shown in FIG. 1 has been adopted. In the figure, 1 is a logic circuit block formed by forming a logic circuit pattern within a rectangular block, 2 is inter-block wiring formed using a computer, and 3 is a bonding pad. This building block method eliminates the diversity of handwritten patterns by standardizing blocks for computers, making them easier to process automatically. However, the drawback of this method is that as the system increases, the shaded area (the area connecting the upper and lower lines, hereinafter referred to as the through area) 4 increases, and the occupied area on the semiconductor chip increases. The reason for this is that the through section 4 was used simply to connect the upper wiring area and the lower wiring area.

The present invention has been made in view of the above-mentioned circumstances, and by configuring the wiring pattern of a logic circuit block to penetrate in the vertical direction of the block, the number of wires in the through section can be reduced as much as possible, and the through-hole wiring pattern can be reduced as much as possible. The object of the present invention is to provide a building block type integrated circuit that can reduce the chip area by using it as part of the wiring within the block.

Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is particularly effective in the case of a silicon gate type E/D (enhancement/depression) MOS circuit, so the following explanations are all for this circuit. It can also be applied to configurations of (enhancement), E/D type, and complementary type MOS.

FIG. 2 shows a negative logic 2NOR circuit to which the present invention is applied; FIG. 2A is an integrated circuit pattern diagram, FIG. 2B is an equivalent circuit diagram thereof, and FIG. In the figure, 11 is a depression type load
MOS transistor section, 12 and 13 are enhanced type drive MOS transistor sections, a, b, d
14 and 15 are power supply wirings provided on the polysilicon layer via an insulating film, the wiring 14 is for the power supply V _DD , and the wiring 15 is for grounding. 16 is a wiring contact portion.

A feature of this configuration is that the gate wirings a, b, and d are formed so as to penetrate through the block in the vertical direction, so that they can be connected from either the upper end or the lower end.Hereinafter, this block will be referred to as a penetration block. . As shown in FIG. 3, various punch-through blocks 17, 17... having such a configuration are arranged in multiple rows in the horizontal direction, and each row 18, 18... is arranged so as to be spaced apart from each other, and the wiring between the blocks is Do this. 19, 19... indicate the wiring thereof. In other words, when automatically forming such wiring using a computer, the through-through wiring patterns of a logic circuit block (for example, a, b, d) and the wiring between other logic circuit blocks are formed using the through-through wiring patterns that are closer to each other. If this is done between the ends, the wiring length will be shortened, the number of wirings in the through section 4 as shown in FIG. 1 will be reduced, and the chip area can be reduced. In the figure 1
9 ₁ to 19 ₄ are through portions and horizontal wiring that can be removed by using the present invention. In particular, the through-hole wiring patterns a, b, and d are effective in that they also serve as the through parts shown in FIG. 1, and also serve as gate wiring for transistors 11, 12, and 13 in the logic circuit block. Also, horizontal power lines 14, 15 and vertical polysilicon wirings a, b,
d is a multilayer wiring, which is constructed so that it does not collide with each other, so it is advantageous in terms of area and is extremely easy to implement. Furthermore, in the case of E/D MOS, the gate of the depletion type transistor can be connected to the output terminal, so polysilicon wiring can be easily extended upward and downward.

In the above embodiment, a punch-through block in which all terminals can be wired from the top and bottom is shown, but in reality, it is not necessary to punch through all the terminals from the top and bottom, and all the terminals can be wired from the top and bottom. In some cases, the block itself becomes larger in the horizontal direction in order to project upward or downward. FIG. 4a shows a partial punch-through block that takes this point into consideration, and FIG. 4b shows its equivalent circuit diagram. As can be seen from the figure, the input wirings are a, b, and c, and the output wiring is d, and only wiring a penetrates upward and downward, so that it can be wired from both sides. Although the number of transistors (shaded area) is increased by one compared to the previous embodiment, the block area remains approximately the same.

Note that the present invention is not limited to the above embodiments,
For example, changing the silicon gate structure to a molybdenum gate structure, or placing the horizontal aluminum power supply wiring of each logic circuit block in the corresponding position, so that when the blocks are arranged horizontally, the power supply wiring is automatically connected. Deformation is possible. Furthermore, the terms "vertical direction" and "horizontal direction" used in the present invention are convenient expressions that define directions.

As described above, according to the present invention, since a through-hole wiring pattern is used, it is possible to provide a building block type integrated circuit that can reduce the area of a semiconductor chip.

[Brief explanation of the drawing]

Figure 1 is a schematic wiring pattern diagram for explaining a conventional building block type integrated circuit, Figure 2a is a pattern diagram of a logic circuit block showing an embodiment of the present invention, and Figure 2b is its equivalent. FIG. 3 is a schematic wiring pattern diagram showing one embodiment of the present invention, and FIG. 4 a is a logic circuit block diagram showing another embodiment of the present invention. , FIG. 2B is an equivalent circuit diagram thereof. a, b, c... penetration wiring pattern, 14,
15...Power supply wiring, 17...Logic circuit block,
18...Block row, 19...Inter-block wiring.

Claims (1)

[Claims] 1 A plurality of logic blocks each having a logic circuit in each block are arranged in a row in the horizontal (or vertical) direction, and are arranged in parallel in multiple rows at predetermined intervals in the vertical (or horizontal) direction, and the logic block row is In a building block type integrated circuit in which the signal input/output terminals derived from each logic block are interconnected by wiring between the logic blocks, each logic block connects at least one of the signal input/output terminals of the logic circuit to the interconnection of the logic blocks. A building block type integrated circuit characterized in that the logic block has two sides extending along the direction, and the signal input/output terminals of the logic block can be interconnected on either side of the two sides. .