JPS623594B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static induction transistor that performs high-speed switching in a large current region.

A static induction transistor (hereinafter referred to as SIT) exhibits unsaturated current-voltage characteristics by controlling the potential barrier appearing in front of the source using the gate voltage and drain voltage to control the amount of carriers injected from the source.
can carry a large current, have a large conversion conductance, and can easily increase the withstand voltage.
Gate capacitance can also be reduced, allowing high-power, high-frequency operation. There are two operating modes in junction-type SIT. When the gate is kept at the same potential as the source, it is in a conductive state, and in the main operating state, the gate is operated by applying a reverse bias (normally-on type), and when the gate is kept at the same potential as the source, it is in a conductive state. , the gate is in a cut-off state, and a forward bias is applied to the gate to make it conductive (normally-off type). When the gate is operated with a forward bias, minority carriers are inevitably injected from the gate into the channel. Of course, injection of minority carriers into a moderate channel works effectively by increasing the injection efficiency of majority carriers from the source and increasing conversion conductance and current gain.
If too many minority carriers are injected, the effect of accumulating excess minority carriers in the channel becomes significant, resulting in a reduction in operating speed.

Split gate SIT proposed by the inventor of the present application (Patent No. 1302727 (Special Publication No. 60-20910) "Static Induction Transistor and Semiconductor Integrated Circuit", Patent No. 1236163
(Special Publication No. 59-12017) "Semiconductor integrated circuit", Patent No. 1247054 (Special Publication No. 59-21176) "Static induction transistor semiconductor integrated circuit", Patent No. 1231827 (Special Publication No. 59-8068) " (Details in “Semiconductor Integrated Circuits”)
This eliminates the above-mentioned accumulation effect of excess minority carriers, reduces the gate capacitance without reducing the conversion conductance, and is extremely suitable for high-speed operation.

An object of the present invention is to provide a large current, high speed switching semiconductor device incorporating a split gate structure.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a structural example of a divided gate SIT in which the gate is divided into a drive gate and a fixed potential gate.
Figures 1a and b are plan views, respectively, and Figure 1c
is a cross-sectional view taken along the line A-A' in FIG. 1a, and FIG. 1d is a cross-sectional view taken along the line B-B' in FIG. 1b. In FIGS. 1a and 1b, electrode wiring is not shown for simplicity. n ⁺ region 1 is the source, P ⁺ region 2,
3 are drive gate, fixed potential gate, n ^-
Area 4 is an area including a portion corresponding to a channel;
n ⁺ region 5 is a drain. 1', 2', 5' are
The source, drive gate, and drain electrodes are made of metal such as Al, Mo, or low-resistance polysilicon, respectively. FIG. 1a shows a structure in which a fixed potential gate completely surrounds the source and drive gate. In FIG. 1b, the fixed potential gate has a structure in which a part of the fixed potential gate has a cut so as to reduce the capacitance between the drive gate electrode 2' and the fixed potential gate. As shown in FIG. 1d, the source electrode 1' is in direct contact with the fixed potential gate 3, illustrating the case where the fixed potential gate is kept at the same potential as the source. Of course, it is also possible to apply a predetermined constant bias to the fixed potential gate instead of setting it at the same potential as the source. Region 6 is SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃
This is an insulating layer such as, or a composite insulating layer that is a combination of multiple insulating layers. The impurity density of each region is about 10 ¹⁸ to 10 ²¹ cm ^-3 for 1, about 10 ¹⁶ to 10 21 cm ^-3 for 2 and 3, about 10 ¹¹ to 10 ¹⁶ cm -3 for 4, and about 10 ¹⁶ cm ^-3 for 5.
It is about 10 ¹⁷ to 10 ²⁰ cm ^-3 . The width of the channel sandwiched between the drive gate and the fixed potential gate varies depending on the voltage applied to the fixed potential gate, but when the potential of the drive gate is the same as that of the source, the width of the channel is due to the depletion layer extending from both gates. It is chosen so that it is completely covered, creating some potential barrier and being in a blocking state. This varies depending on the impurity density of the channel and the impurity density of the gate, and the higher the impurity density of the channel, the narrower the channel width usually has to be. sauce,
The distance between the drains may be set to such a length that the transit time of electrons between the source and the drain does not deteriorate the frequency characteristics of the operation. For example, if a switching speed of 1 nsec is to be obtained, the thickness should be about 20 μm or less. Although the fixed potential gate is often directly connected to the source, it is of course possible to apply a predetermined reverse bias. Even if a drain voltage (positive voltage in this case) is applied, a potential barrier is created in front of the source due to the diffusion potential of the gate, and no current will flow. If a certain amount of voltage is applied to the drive gate, in this case, for example, about +0.4 to +0.7V (for Si, about 0.6 to 1.1V for GaAs), the potential barrier height decreases or the neutral region appears,
Changes to conductive state. At this time, holes are injected into the channel from the forward biased gate. The injected electrons promote electron injection from the source and reduce the conduction state resistance. Furthermore, since the fixed potential gate is maintained at the same potential as the source, the injected holes are sucked out by the fixed potential gate and do not accumulate in the channel. Since the channel width is usually shorter than the hole diffusion length in the channel region, the hole sucking effect by the fixed potential gate is extremely effective. Therefore, the switch-off when the driving gate voltage is cut off is extremely fast, and there is almost no delay due to the accumulation effect of minority carriers. The drive gate that controls the channel has a small volume and a small capacitance. Minority carriers injected from the drive gate cross the channel and flow into the fixed potential gate, so they are always present in the channel portion and effectively cause majority carrier injection from the source. Therefore, the current gain will be extremely high. Of course, the conversion conductance is also large. FIG. 2 shows an example of the structure of the split gate SIT of the present invention, in which the capacitance of the drive gate is further reduced and the conversion conductance and current gain are increased.

FIG. 2a is a plan view, and FIG. 2b is a sectional view taken along line A-A'. The drive gate 2 has a cylindrical shape, the source 1 has an annular shape, and the fixed potential gate 3 extends over the required entire surface. As shown in FIG. 2, when the drive gate is configured in a cylindrical or annular shape, a wide channel can be controlled even with a small drive gate, and the capacitance of the drive gate is small and the conversion conductance and current gain are large. Since the minority carriers injected into the channel are immediately sucked out of the fixed potential gate, there is little effect of minority carrier accumulation and the switching speed is extremely fast. The source electrode 1' faces the fixed potential gate via the insulating layer 6, but since the source and the fixed potential gate are usually directly connected or kept at a constant potential, an increase in the capacitance between them is not a problem. It doesn't affect you very much. The fact that the switching operation is normally performed in a source-grounded circuit further confirms the above. The operation is almost the same as the example shown in FIG.

Operate by forward biasing the drive gate
In SIT (bipolar mode SIT, hereinafter referred to as BSIT), only a very small voltage of around 1V is usually applied between the source and gate, so there is almost no need for a withstand voltage. Therefore, the source and gate may be separated by a high resistance region as shown in FIGS. 1 and 2, or may be in direct contact with each other. Of course, the structure of the channel is not limited to the striped or annular shape as shown in Figures 1 and 2.
It may be of any shape such as an ellipse or a rectangle. It is sufficient that the gates surrounding the channel are divided, one part being a fixed potential gate and the other being a driving gate, and the fixed potential gate serving as the extraction electrode for the minority carriers injected from the driving gate into the channel. . Of course, the conductivity type may be reversed.

Although FIGS. 1 and 2 show the structure in which the driving gate and the fixed potential gate have almost the same depth from the surface, they may of course be different. If the fixed potential gate is made deeper, the first
In the SIT shown in Figures and Figure 2, the effect of sucking out the minority carriers injected into the channel becomes noticeable.

Figures 1 and 2 show the cross-sectional structure of a surface wiring structure in which the source and gate are both on the same plane, but in order to further reduce the capacitance of the drive gate and increase the current gain, It is also possible to provide a rectangular, V-shaped, etc. notch and provide a drive gate on the side surface of the notch.

The structure of the present invention can be manufactured by conventionally known crystal growth techniques, fine processing techniques, selective diffusion techniques, selective etching techniques (dry chemical), ion implantation techniques, and the like.

The static induction transistor of the present invention has a plurality of units arranged in parallel in which a source for supplying a carrier to a channel is interposed between a drive gate and a fixed potential gate, and the capacitance of the drive gate is small.
There is almost no carrier accumulation effect in the channel, the conversion conductance and current gain are large, and high-speed switching of large currents can be performed, so its industrial value is extremely high.

[Brief explanation of the drawing]

FIGS. 1a and 1b are plan views of structural examples of the power-transmitting induction transistor of the present invention, and FIG. 1c is A--A in FIG.
FIG. 1d is a sectional view taken along line A', FIG. 1d is a sectional view taken along line B-B' in FIG. aA in the figure
It is a cross-sectional view along the −A′ line.

Claims (1)

[Claims] 1. A source region and a drain region made of high impurity density regions, a channel made of a high resistance region of the same conductivity type as the high impurity density region, and a high impurity density region of the opposite conductivity type to the channel in the channel. one gate region of the source region is a driving gate region, the gate region on the opposite side of the driving gate region with respect to the source region is a fixed potential gate region, and the driving gate region connects the gate electrode. and the fixed potential gate electrode is
The structure is characterized in that no external electrode is provided, and a plurality of structures each consisting of the source region and the gate region are arranged in parallel, and the respective electrodes of the source region and the driving gate region are connected to each other to form a source electrode and a gate electrode. A static induction transistor characterized by: 2. The static induction transistor according to claim 1, wherein the fixed potential gate region is directly connected to the source region by an electrode.