JPS623611B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit composed of complementary MOS field effect transistors, and an object of the present invention is to provide a complementary MOS field effect transistor circuit that can obtain an output signal having hysteresis characteristics with respect to an input signal. Our goal is to provide the following.

According to the invention, the first and second P channels
MOSFET and first and second channel MOSFET
a first inverting circuit having a third P-channel MOSFET and a third N-channel MOSFET; and a second inverting circuit having a fourth P-channel MOSFET and a fourth N-channel MOSFET. The gates of the first and second P-channel MOSFETs and the first and second N-channel MOSFETs are connected to an input terminal that receives an input signal, and the first, third and third channel MOSFETs are connected to the first power supply line. The drain of the fourth P-channel MOSFET is connected to the second power supply line, the sources of the first, third and fourth N-channel MOSFETs are connected to the second power supply line, and the sources of the first and third P-channel MOSFET are connected to the second power supply line. connected to the drains of the second P-channel MOSFETs, and connected to the drains of the first and third N-channel MOSFETs.
The drain of the MOSFET is the second N-channel
connected to the source of the MOSFET, and connected to the source of the second P-channel MOSFET and the second N-channel MOSFET.
A fourth P channel MOSFET and a fourth N
The gate of the fourth P-channel MOSFET is connected, and the source of the fourth P-channel MOSFET and the fourth N-channel MOSFET are connected.
The drain of the channel MOSFET is connected to provide an output terminal of a second inversion circuit, and the gates of a third P-channel MOSFET and a third N-channel MOSFET are connected to the output terminal of the second inversion circuit. , a complementary MOS field effect transistor is obtained, characterized in that an output signal having a hysteresis characteristic with respect to the input signal is obtained at the second inverting output terminal.

the third P-channel MOSFET and the third P-channel MOSFET;
The N-channel MOSFET constitutes a circuit that changes the resistance division ratio of the first inverting circuit at the output point of the first inverting circuit in accordance with the output of the second inverting circuit.

That is, the present invention provides an input signal having a slowly changing input voltage at a predetermined threshold voltage by changing the resistance division ratio of the first inverting circuit at the output point of the first inverting circuit. Converts to an output signal with a steep digital voltage, and converts it into an output signal with a steep digital voltage with a different threshold voltage depending on whether the input signal voltage increases or decreases. An output signal with hysteresis characteristics was obtained.

Therefore, the present invention can be used as an interface circuit that digitally converts a signal from an analog circuit, or as an interface circuit that converts a signal with a distorted waveform from a digital circuit into a good digital waveform. Further, the present invention is a circuit having a hysteresis characteristic that makes it difficult to malfunction due to noise contained in an input signal, and has a large noise margin, and can also be used as an input interface circuit of a digital circuit.

Furthermore, according to the transistor arrangement according to the present invention, the degree of hysteresis characteristic can be selected depending on the on-resistance ratio of the transistor, making it easier to manage integrated circuit manufacturing parameters and minimizing the circuit area, making it ideal for integrated circuits. A circuit with excellent hysteresis characteristics can be provided.

In addition, the present invention provides first and second P-channel MOSFETs and first and second channel MOSFETs.
A circuit in which four transistors with MOSFETs are connected in series with each other is connected between the first and second power supply lines. During the transition period of the input signal applied to the input terminal, there is a period in which all four transistors are turned on.
Since the resistance between the first and second power supply lines is the sum of the on-resistances of the four transistors described above, the through current between the first and second power supply lines can be kept small, making it suitable for reducing power consumption. ing.

Next, embodiments of the present invention will be described with reference to the drawings. Note that in the following description, the field effect transistor will be abbreviated as FET. In FIG. 1 showing an embodiment of the present invention, P1, P2, P3,
P4 is each P channel MOSFET, and N
1, N2, N3, N4 are N-channel MOSFETs
It is. This example uses two pairs of complementary MOSFETs P1,
First inversion circuit 10 composed of N1, P2, N2
, a second inverting circuit 20 configured with a pair of complementary MOSFETs P4 and N4 and inputting the output of the first inverting circuit 10, and a pair of complementary MOSFETs P3,
N3 and a circuit that changes the resistance division ratio of the first inverting circuit 10 at the output point A of the first inverting circuit 10 according to the output of the second inverting circuit 20. This is a complementary MOSFET circuit characterized in that an output signal having a hysteresis characteristic is obtained at the output OUT of the second inverting circuit 20 with respect to the input signal applied to the input signal IN of the second inverting circuit 20.

To explain the circuit configuration of Fig. 1 in detail, the input signal IN is connected to the gate electrodes of FETs P1, P2, N1, and N2, and is connected to the drain electrodes and substrate electrodes of FETs P1, P3, and P4, and the substrate of FET P2. The electrode is connected to the power supply _VDD ,
The source electrodes and substrate electrodes of FET N1, N3, N4 and the substrate electrode of FET N2 are connected to earth GND (zero potential), and FET P
The source electrodes of FET P1 and P3 are connected to the drain electrode of FET P2, and the source electrodes of FET P2 and
The drain electrodes of FET N2 are connected to each other, and the point A becomes the output of the first stage inversion circuit 10, and the point A becomes the output of the first stage inverting circuit 10.
The point is connected to the gate electrode of FET P4 and N4, and the source electrode of FET N2 is connected to FETN1 and N3.
The source electrode of FET P4 and the drain electrode of FET N4 are connected to each other, which becomes the output OUT of this circuit, and is simultaneously connected to the gate electrodes of FETs P3 and N3.

Next, the operation shown in FIG. 1 will be explained. The threshold voltage of P channel FET is V _TP ,
The threshold voltage of N-channel FET is V _TN , and FET P1, P2, P3, N1, N
The on-resistances of 2 and N3 are R _P1 , R _P2 , and R _{P ,} respectively.
₃ , _RN1 , _RN2 , and _RN3 . Figure 2 is complementary type
This is a diagram for explaining the range in which the MOSFET is turned on and off depending on the input voltage V _IN , and region a is P
The channel FET is off and the N-channel FET is on. Region b is P channel FET,
Both N-channel FETs are in the on state. In region c, P channel FET is on, N channel
FET is in off state.

First, considering the first state when V _IN =V _DD , the first stage inverting circuit 10 is in region a of FIG. 2, so FETs N1 and N2 are on, and FET P
1 and P2 are in the off state. Therefore, point A is V _DD
High resistance (very large compared to on-resistance) towards the GND side, on-resistance R _N1 and R _N2 towards the GND side
Since the output of the first stage inverting circuit 10, that is, the voltage at point A, V _A =0.
Since the input of the second stage inverting circuit 20 is V _A =0, it is in region c in FIG. 2, and the output voltage V _OUT =V _DD
It is. At the same time, the output of the second-stage inversion circuit 20 is applied to the gate electrodes of FETs P3 and N3, so the complementary MOSFETs P3 and N3 are
It is located in region a of the figure, and P3 is in the off state and N3 is in the on state.

Next, as a second state, the input voltage V _IN is gradually lowered until V _IN <V _DD -|V _TP
and P2 changes from off state to on state, and point A
The voltage V _A is Therefore, the output voltage V _OUT does not invert and maintains the previous state until V _A =V _TN . That is, the state of the second stage inverting circuit 20 does not invert up to the points shown in FIGS. 3A, B, and C. When the input voltage V _IN is further lowered, the output voltage V _OU increases along the -1 line in A and B in Figure 3.
_T changes.

As the third state, the input voltage V _IN is further lowered to 0≦
When V _IN ≦V _TN , the first stage inverting circuit 10 is
Since this is region c in the figure, FETs N1 and N2 change from on to off. Therefore, on-resistances R _P1 , R _P2 , R _P3 are connected to point A for the V _DD side,
A high resistance (very large compared to on-resistance) is connected to the GND side, and the first stage inverting circuit 10
, the voltage at point A is V _A =V _DD .
Since the input of the second stage inverting circuit 20 is V _A =V _DD , the output voltage is V _OUT =0. At this time, complementary type
MOSFETs P3 and N3 are located in region c of FIG. 2, with P3 in the on state and N3 in the off state.

Conversely, as the fourth state, when the input voltage V _IN is gradually increased until V _IN > V _TN , FETs N1 and N2 change from the off state to the on state, and the voltage at point A becomes Therefore, the second stage inverting circuit 20 maintains the output voltage V _OUT =0 without inverting until V _A =V _DD -|V _TP |. That is, the state of the second-stage inversion circuit 20 does not invert until the points shown in FIG. 3A, B, and C. When the input voltage V _IN is further increased, the output voltage V _OUT changes along the -2 line in FIGS. 3A and 3B.

As the fifth state, the input voltage V _IN is further increased to V _DD
When −|V _TP |<V _IN ≦V _DD , the output voltage becomes V _OUT =V _DD as in the first state.

In other words, the circuit of FIG. 1 has a hysteresis characteristic between the input voltage V _IN and the output voltage V _OUT as shown in _FIG. , R _P2 , R _P3 , R _N1 , R _N2 , R _N3 values, that is, transistors P1, P2, P3, N1,
By changing the channel width and channel length of N2 and N3, the degree of hysteresis characteristic can be changed.

Nowadays, circuits that traditionally belonged to the analog domain are increasingly being converted to digital, and there is a need for an interface circuit that converts analog voltages to digital voltages. There is also a need for a digital conversion interface circuit that is less likely to malfunction in response to an input signal that contains noise or has an analog voltage with a small amount of change. There is also a need for an interface circuit that converts an input signal having a digital voltage with a corrupted waveform into a good digital waveform. Furthermore, there is a need for an input interface circuit of a digital circuit that is less likely to malfunction due to noise contained in an input digital signal.

The circuit of the invention can meet all of the above requirements. It goes without saying that the present invention can also be used in other fields where it is necessary to obtain an output signal having hysteresis characteristics with respect to an input signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the range in which a complementary MOS field effect transistor is turned on and off depending on the voltage applied to the gate electrode, and FIG. Figure 3A is a diagram showing the input voltage V _IN -output voltage V _OUT characteristic of the circuit in Figure 1, and Figure 3B is a diagram showing the input voltage V _IN -A of the circuit in Figure 1.
FIG. 3C is a diagram showing the point voltage V _A characteristic and the A point voltage V _A -output voltage V _OUT characteristic of the circuit of FIG. 1. In the figure, 10 is a first inverting circuit composed of two pairs of complementary MOS field effect transistors P1, N1, P2, N2, and 20 is a pair of complementary MOS field effect transistors.
The second inverting circuit is composed of field effect transistors P4 and N4, and P3 and N3 are the resistances of the first inverting circuit 10 at the output point A of the first inverting circuit 10 according to the output of the second inverting circuit 20. These are a pair of complementary MOS field effect transistors that constitute a circuit that changes the division ratio.

Claims (1)

[Claims] 1 A first inverting circuit having first and second P-channel MOSFETs and first and second N-channel MOSFETs, and a third P-channel MOSFET.
a circuit having a MOSFET and a third N-channel MOSFET; a second inverting circuit having a fourth P-channel MOSFET and a fourth N-channel MOSFET; The gates of the second P-channel MOSFET and the first and second N-channel MOSFETs are connected, the drains of the first, third, and fourth P-channel MOSFETs are connected to the first power supply line, and the gates of the second P-channel MOSFET are connected to the first power supply line. 1st, 3rd and 4th in the power supply line
The source of the N-channel MOSFET is connected,
The sources of the first and third P-channel MOSFETs are connected to the drains of the second P-channel MOSFET, and the sources of the first and third P-channel MOSFETs are connected to the drains of the second P-channel MOSFET.
is connected to the source of the second N-channel MOSFET, and the drain of the second P-channel MOSFET is connected to the source of the second N-channel MOSFET.
and the drain of the second N-channel MOSFET are connected to provide an output terminal of the first inverting circuit, and the output terminal of the first inverting circuit is connected to the source of the fourth P-channel MOSFET and the drain of the fourth N-channel MOSFET. channel
The gate of the MOSFET is connected, and the source of the fourth P-channel MOSFET and the fourth N-channel MOSFET are connected.
A third P-channel MOSFET and a third N-channel MOSFET are connected to the drain of the MOSFET to provide an output terminal of a second inverting circuit.
1. A complementary MOS field effect transistor circuit, wherein a gate of a channel MOSFET is connected, and an output signal having hysteresis characteristics with respect to the input signal is obtained at the output end of the second inverting circuit.