JPS623614B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is used in phase-locked loops such as phase-lock loops and Costas loops.
Regarding digitization of VCO (voltage controlled oscillator).

With the development of digital technology in recent years, circuits that were conventionally constructed using analog circuits have been converted to digital, and some have even been implemented as LSI. Extract carrier from amplitude modulated wave or phase shift modulated wave,
In recent years, research has been underway to digitize phase-locked loops used for demodulating frequency modulated waves.

FIG. 1 shows the configuration of a digital phase lock loop. Input 10 is the sampled sequence X(n). The output 19 is a series Y(n) obtained by sampling a sine wave. The multiplication circuit 11 plays the role of a phase comparator, and if the sampling interval T is set as is Z(n)=X(n)・Y(n)=sin(WcnT+θ)cos(WcnT)=1/2{sin(2WcnT+θ)+sinθ}...(1). Digital low-pass filter 18 reduces the double frequency component of the carrier in the above equation and determines the characteristics of the loop.

This filter may be as simple as, for example, H(z)=K ₂ /1−K ₁ Z ⁻¹ . (At this time it was 14
2Wc component is mixed) Filter output W
(n).

An adder 15, a phase designation memory 16, and a sine wave generator 18 constitute a digital VCO. The sine wave generator 18 outputs the amplitude value of the sine wave corresponding to the phase 17 designated by the phase designation memory 16. For example, assume that the 360° phase is divided into 32 equal parts.
If the phase designation memory designates "15", the output of 18 is set to output a value of cos (360°×15/32).

The phase designation V(n) of No. 17 is as follows: V(n)=V(n-1)+C+W(n-1). C specifies the center frequency of the VCO, W
(n-1) becomes the VCO control signal. For example, if the control signal is always 0, the phase designation increases by C every time T, so the center frequency F ₀ becomes F ₀ =C/32·1/T. When the VCO control voltage W(n) is positive, the phase advances faster, which corresponds to increasing the oscillation frequency of the VCO. The opposite is true when W(n) is negative. Therefore, in equation (1), if θ > 0, the low-pass filter 18 emphasizes the DC component 1/2 sin θ, so the VCO
The control signal becomes positive, and the output of the VCO is controlled in the phase advance direction.

If θ<0, the opposite is true.

The Costas loop is a loop that extracts the carrier component from the DSB waveform. A block diagram of the Costas loop is shown in Figure 2.

Input 20 as DSB waveform A(t)cos(Wct+θ)
shall be. If the output 30 of the VCO 29 is sin (Wct), then E _A (t) of the output 22A of the phase comparator 21A
is E _A (t) = A (t) cos (Wct + θ) sin (Wct) = 1/2A (t) {-sin θ + sin (2Wct + θ)}...(2
) VCO output 30 passes through a 90° phase shifter 31 and outputs 3
2 to obtain −cos(Wct). Phase comparator 21
E _B (t) of output 22B of B is E _B (t) = -A (t) cos (Wct + θ) cos (Wct) = -1/2A (t) {cos θ + cos (2Wct + θ)}... (3
) LPF23A and 23B have twice the frequency of the carrier
This is to cut the modulation component due to 2Wc, and the output 2
H _A (t) and H _B (t) of 4A and 25B are H _A (t) = -1/2A (t) sinθ H _B (t) = -1/2A (t) cosθ Output of multiplication circuit 25 G(t) is G(t)=H _A (t)・H _B (t) = 1/4A(t) ² sinθcosθ = 1/8A(t) ² sin2θ ……(4) Therefore, A(t) ²⁰ , if it passes through the LPF 27, a value proportional to sin2θ can be obtained as the VCO control signal 28, so the output of the VCO can be locked with the input. The Costas loop has a 180° warmth in the lock phase. Needless to say, this Costas loop can also be digitized like the phase lock loop shown in FIG. When this Costas loop is digitized, VCO 29 is also digitized. As mentioned above, this digital VCO consists of an adder, a phase designation memory, and a sine wave generator. The sine wave generator is e.g. ROM
(Read Only Memory), and when an address (corresponding to the phase) is specified in the phase specification memory, the contents of that address are output. The ROM stores the values of the sine wave at each phase. this
The greater the number of ROM addresses, the less output jitter will occur and the more precise control will be possible, but
There is a limit because the amount of ROM becomes large.

For example, 360 degrees is divided into 128 equal parts and the value of the sine wave at each phase is stored so that the jitter is within 4 degrees. The stored content An is assumed to be, for example, An=cos (360°×n/128) (n=0 to 127). Therefore, the phase designation memory only needs to designate addresses from 0 to 127, and if expressed in binary, 7 bits are sufficient.

The adder shown in FIG. 15 only needs to perform mod128 addition, and it is sufficient to discard the overflow in the 7-bit operation. The phase designation memory has 7 bits. However, such a system has the following disadvantages. The oscillation frequency of the digital VCO mentioned above can only take discrete values. If the sampling frequency is Fs, then only the oscillation frequency every Es/128 can be obtained. Therefore, for example, if Fs is 16KHz, values can only be taken every 125Hz.

Therefore, for example, when the input frequency is 2050 Hz, the constant C in FIG. 1 is 16 if the center frequency of the VCO is 2000 Hz, and 17 if the center frequency is 2125 Hz. Therefore, if C=16, the control signal 14 becomes 1 and 0 so that the average output becomes 2050 Hz. Normally there is no problem with the above system, but inconveniences occur in the following cases. For example, if the input is temporarily lost, the control signal cannot become 1 or 0, so the VCO's oscillation frequency will be 2000Hz or 2125Hz, and the phase will change significantly by the time the input comes in again. It will shift.
Also, although the VCO is configured with only 15, 16, and 18 in Figure 1, if you change the control signal with only these,
It can also be used as a FSK (frequency shift keying) modulator. But in this case too the output is
Since the output frequency can only be set at 125Hz intervals, the output frequency may differ from the desired one. To avoid this, it is possible to increase the capacity of the ROM and increase the number of phases to be stored, but this requires a large capacity.

In this way, it is used in phase-locked loops such as phase-lock loops and Costas loops.
When attempting to digitize the VCO and control it with high precision, the ROM that made up the sine wave generator became large in capacity.

Therefore, the present invention relates to a digital voltage controlled oscillator used in phase-locked loops such as phase lock loops and Costas loops.
It is an object of the present invention to provide a digital voltage controlled oscillator that has at least a ROM capacity and can realize accurate control.

In order to achieve the above object, the present invention is characterized in that a digital voltage controlled oscillator includes means for reducing the number of bits that define the precision of its oscillation frequency from the number of bits that define the precision of its phase.

That is, a first means receives a first signal for controlling the phase as a control signal, performs an operation based on the first signal, and outputs a second signal as a phase value; The second obtained by
A digital voltage controlled oscillator having second means for outputting as a third signal an amplitude value corresponding to a phase value represented by the signal, the digital voltage controlled oscillator is provided between the first and second means, and the second signal The present invention is characterized by comprising means for converting the second signal into a signal with a smaller number of bits than the number of bits representing the signal, and supplying the converted signal to the second means.

FIG. 3 shows an embodiment of the present invention. This embodiment relates to a VCO used in a phase-locked loop such as a phase-lock loop or a Costas loop. This VCO includes a sine wave generator. This sine wave generator 48 is a ROM that divides a 360 degree phase into 128 parts and stores the value of the sine wave of that phase, as in the previous example. Of course, in general, the waveform is not limited to a sine wave, but may be any predetermined synchronous waveform. Here, the phase specification memory 44 specifies the address of the ROM 7
Suppose that in addition to bits, bits are also added that can represent numbers less than the unit of one address. For example, add 4 additional bits for a total of 11 bits. The quantization circuit 46 further coarsely quantizes the 11-bit information 45 into 7-bit address information 47. The quantization method can be rounded up, rounded down, or rounded off, but rounding down is the simplest because it just takes the upper 7 bits. Since the phase designation memory has a capacity of 4 bits below the address unit, the control signal 40 and constant C41 can also be input with that much precision. for example,
In the example above, when the sampling frequency Fs was 16KHz, the center frequency could only take values every 125Hz, but in the example of the present invention, there are 4 bits after the address, so
You will be able to take values every 125/2 ⁴ = 7.8125Hz.

For example, if the control signal is 0, the constant C is (16+
4/24)=16.25, the contents 45 of the phase memory and the address designation 47 to the ROM become as shown in FIG.
However, the quantization process in the quantization circuit 46 uses truncation. The quantization process here refers to the process of reducing the number of bits, and it is possible to use not only truncation but also rounding, rounding up, etc. Also, the adder 42
The addition by is a cyclic addition that returns to 0 when the sum reaches 128. Under these conditions, ROM
The address designation will be explained in more detail. In this embodiment, the constant C=16.25 is sequentially added at each sample timing by the phase designation memory 44 and the adder 42. In other words, the value of (constant C + control signal) maintains "16.25" and the phase designation memory 4
The output of 4 is 16.25, 32.5, 48.75... This is the correct value on this circuit, but in this embodiment, the 11-bit value is rounded down to 7 bits in the quantization circuit 46, so an error will occur. For example, when the input to the quantization circuit 46 (output 45 of the phase designation memory 44 in FIG. 4) is 16.25, it becomes "00100000100" when expressed in binary. The first 7 bits correspond to the integer part "16" and the last 4 bits correspond to the decimal part "0.25". The reason why the integer part is 7 bits is because the adder 42 has 7 bits as described above.
is a cyclic adder up to 128.

Therefore, the output of the quantization circuit 46 is 11 bits equal to 7
The bit becomes “0010000”. In short, the quantization circuit 46 truncates the decimal places when displaying in decimal notation.

Then, the error in the output of the quantization circuit 46 increases by 0.25 (in decimal notation) for each sampling time. In this embodiment, this error becomes 1 or more after four sampling times, and the phase increase amount is corrected by outputting a value increased by 1 to the output of the quantization circuit 46 and reducing the error amount to 1 or less again. That is, the output of the quantization circuit 46 increases by "16" (in decimal notation), but increases by "16+1" once every four times. That is, if you average the four times, the increase will be 16.25 for each sampling time. In terms of ROM address, this is "16"
(In decimal notation) As shown in Figure 4, when sample number is 4, it is increased by "17". This corresponds to the phase, which normally advances by 45, and advances by 47.8125 once every 4 samples. As a side note, in this example, 360 degrees is divided into 128 equal parts, so the difference in the first address corresponds to 2.8125 degrees.

If this is done, a jitter of 2.8125 degrees or less, which corresponds to address 1, will appear on the output 49, but as mentioned above, in this embodiment, the condition is to keep the jitter to 4 degrees or less, and this is satisfied. No problem.

Furthermore, in the example shown in Figure 4, the center frequency is 2031.25Hz, and the lower bits indicate 7.8125Hz.
It becomes possible to express frequencies at different locations. Since the control signal 40 can also have the same accuracy, the phase shift can be reduced even if there is no input. Note that the difference in operation between using a rounding circuit and a truncating circuit as the quantization circuit is simply that the contents of the phase specification memory are 0.5 addresses larger when using the truncating circuit, and there is no difference in output. .

By doing the above, it is possible to set high control accuracy in a VCO used in a phase-locked loop such as a phase-lock loop or a Costas loop without increasing the ROM capacity.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the circuit configuration of a general digital phase lock loop, FIG. 2 is a diagram showing an example of the circuit configuration of a Costas loop, and FIG. 3 is a diagram showing an embodiment of the present invention. , FIG. 4 is a diagram for explaining FIG. 3. 42...Adder, 44...Phase specification memory, 4
6...Quantization circuit, 48...Sine wave generator.

Claims (1)

[Claims] 1. A first means that receives a first signal for controlling the phase as a control signal, performs an operation based on the first signal, and outputs a second signal as a phase value. , a digital voltage controlled oscillator comprising a second means for outputting, as a third signal, an amplitude value corresponding to a phase value represented by a second signal obtained by the first means, wherein the first and second means and a means for converting the second signal into a signal with a smaller number of bits than the number of bits representing the second signal and supplying the converted signal to the second means. Digital voltage controlled oscillator. 2. The second means comprises a ROM that stores amplitude values corresponding to each phase value, and means for reading out the contents of the ROM using the second signal as an address. digital voltage controlled oscillator. 3 The first means cumulatively adds the first signal and a predetermined constant value for each sampling period, and when the cumulative addition value overflows a certain constant value, the overflow amount is added to a new cumulative value. It includes a cyclic accumulative adder such that the summation value is
2. The digital voltage controlled oscillator according to claim 1, wherein the cumulative addition value is output as a second signal.