JPS623615B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A voltage comparison circuit used in a monolithically integrated AD converter requires means for automatically correcting offset voltages caused by manufacturing variations in device characteristics. As conventional technology, for example,
ISSCC78, Digest of Technical Papers, 176~
JBCecil et al, “Atwochip PCM
CODEC for Per-Channel Applications", a polar signal integration circuit using capacitance and resistance is used. In this case, in order to avoid overcompensation for each A/D conversion cycle, a large time constant, , large capacitance and resistance are required, which necessitates the use of external components.

An object of the present invention is to provide a means and circuit configuration for automatically correcting the offset voltage of this voltage comparison circuit without using any external electronic components other than monolithically integrated circuit elements. .

Hereinafter, the present invention will be explained in detail using the drawings.

In FIG. 1, A is a voltage comparator, which compares the magnitude of two input voltages at the time of application of the latch enable pulse _P2 , and outputs the result as a pulse _P3 having a logic level of 1 or 0. . The non-inverting input terminal of A above is connected to the drive pulse _P1 and
Switches S ₁₁ and S ₁₂ that are turned on and off are connected at P ₁ (the logic levels of P ₁ and P ₁ are opposite to each other, and P ₁ = P ₁ holds true. The same applies below).
The other end of S ₁₁ is connected, and the other end of S ₁₂ is connected to the input signal source to be compared. On the other hand, the inverting input terminal of A above has a capacitor connected to one end.
C ₂ is connected to a switch S ₆₂ which is turned on and off by pulse P ₆ . Further, at the other end of the switch S ₆₂ , there is a switch S ₆₁ driven by the pulse P ₆ ,
It is connected to a capacitor _C1 whose one end is grounded. Furthermore, a resistance element R ₂ whose one end is grounded and another resistance element R ₁ are connected to the other end of the switch S ₆₁ .

A switch S ₅₁ driven by pulse P ₅ and a switch S ₅₂ driven by pulse P ₅ are connected in parallel to the other end of the resistance element R ₁ .
The other end of S ₅₁ is connected to a positive voltage source, and the other end of S ₅₂ is connected to a voltage source of the load. Further, a logic circuit L is connected to the output terminal of the comparator A described above. This logic circuit L is the leading edge (or trailing edge) of pulse P ₄
The logic level of the above pulse P ₃ at the time P ₄
The output pulses are _P5 and _P5 mentioned above.

In the above configuration, if the offset voltage of voltage comparator A is manufactured to be sufficiently small and there is no problem even if it is used in an AD converter, the non-inverting input terminal of the comparator A can be adjusted as shown in Figure 1. The input equivalent offset voltage is V _a =0, and the inverting input terminal voltage V _c takes a voltage value within ±1/2LSB (LSB is the minimum quantization voltage width), but it may vary due to changes in environmental conditions or manufacturing variations. If a relatively large offset voltage occurs, V _c automatically changes to follow the offset voltage value, and operates to equivalently cancel the offset.

Let V _d be the input offset of voltage comparator A, and V _p be the input voltage of switch S ₆₁ . Here V _p
is |V _p |= for compensation power supply voltage ±V
It is assumed that the relationships R ₂ /R ₁ +R ₂ V and V _p >V _d are satisfied.

Now, before executing the conversion with the AD converter, the second
When applying pulse P ₁ as shown in the figure, S ₁₁ turns on,
_S12 is in the off state. At this time, the input equivalent offset voltage V _d generated at the non-inverting input terminal is compared with the inverting input terminal voltage V _c at this time, V _d >
If there is a relationship of V _c (V _d < V _c ), the output P ₃ will be 1 as shown in the figure when the latch pulse P ₂ is applied.
(0).

Next, when pulse P ₄ is applied in the time relationship shown in the figure, the logic circuit L receives pulses P 5 and ₅ which are held for at least the time until the next pulse P ₄ is input
Outputs P ₅ , and this pulse causes the switch to
S ₅₁ is on and S ₅₂ is off.

Within the above holding period, the above pulse P ₁ becomes 0 (therefore, the switch S ₁₂ is turned on),
If a pulse P ₆ that turns on S ₆₁ is applied until the first comparison of input signals for AD conversion is made, the voltage between the terminals of C ₁ is charged to V _p .

Next, switch S ₆₁ off and S ₆₂ on,
The inverting input terminal voltage V _c of comparator A has a value increased from the voltage up to the previous point in time.

AD conversion of the input signal V _IN is started immediately after the above series of compensation operations is completed. If the previous compensation is not complete, the above compensation operation is repeated before the next AD conversion is performed. At this time,
When a large offset occurs due to a sudden change in environmental conditions, etc., in order to quickly raise V _c to the compensation voltage, the ratio of V _p to V _d must be set large, and
This is possible if the capacitance ratio of C ₁ to C ₂ is set large, but in this case, overcompensation occurs and a large ripple voltage is generated in the compensation voltage V _c , so a large drift voltage is applied equivalently. This results in a large error in AD conversion. Therefore, it is necessary to optimize the settings regarding the above-mentioned V _p and the capacitance ratio of C ₂ to C ₁ .

Now, let us consider a case in which the compensation voltage V _c is very slightly larger than the offset voltage V _d (V _d ≦V _c ), as shown in the time domain of FIG. 2. In this case, immediately after the above series of compensation operations in the next time domain are performed, P ₃ and P ₅ are 0, and S ₅₂ is on, so V _c
The value of falls below the value in the region. If this voltage drop is expressed by ε, ε can be expressed by the following equation.

ε=V _c −V _c・C ₂ −V _p・C ₁ /C ₁ +C _2By the way, in a high-precision AD converter, the drift voltage amplitude during conversion is limited to within 1/2LSB. is required, so if the AD conversion accuracy is N bits and the maximum encoding amplitude is V _n , then
The above equation is converted as follows.

V _c −V _c・C ₂ −V _p・C ₁ /C ₁ +C ₂ ≦V _n /
2 ^N+1 If we organize this regarding the capacitance ratio of the capacitor, becomes.

Now, as an example, the offset voltage V of the comparator
Taking the case where _d is 50 mV, AD conversion accuracy is N = 12 bits, and maximum amplitude is Vm = 5 V, if the compensation power supply voltage V _p is 100 mV, it is sufficient to set C ₂ /C ₁ ≧245. Therefore, specifically, C ₁ =
If it is 0.1 pF, C ₂ ≧24.5 pF, so this capacitor can be realized economically as an IC element.

FIG. 3 shows the switches S ₆₁ , R ₆₂ , and
This shows an example in which the output voltage of a compensation voltage generation circuit CMP consisting of capacitors C ₁ and C ₂ and resistors R ₁ and R ₂ is applied to a sample and hold circuit V/H, and is generally referred to as a successive approximation type. It constitutes an AD conversion circuit that can be used. In CMP, resistance
R ₁ and R ₂ are essentially not necessary.

In FIG. 3, DA is a DA conversion circuit that sequentially outputs comparison approximate voltages for AD conversion of sampled and held input signal voltages. ADD is a means or circuit that adds the respective voltages of S/H and DA in an analog manner (i.e., a circuit that obtains the difference between the sample signal and the locally decoded signal). SAR is the logic level of the output pulse _R3 of voltage comparator A. This is a successive approximation register that feeds back to the DA above. All of the circuit elements in FIG. 3 that are the same as those in FIG. 1 have the same configuration and operation as those shown in FIG.

In FIG. 3, the input-referred offset voltage V _d ' generated when P ₁ is applied and S ₁₁ is turned on is the offset voltage generated in the sample-and-hold circuit S/H and voltage comparator A, respectively. The sum is the output voltage V of the compensation voltage generation circuit CMP.
_c ' produces a value that compensates for the offset voltage summation value V _d ' of S/H and A. As a result, if we pay attention to the compensation voltage generated at the non-inverting input terminal of voltage comparator A, we can see that this voltage is the value obtained by changing the polarity of the input conversion voltage _Vd of only A shown in FIG. It operates so that _Vd .

According to the second embodiment described in detail above, a voltage comparator based on the present invention is integrated into an IC together with an AD converter and a pre-analog processing device necessary for the conversion.
In addition to the method of feeding back the compensation voltage to one end of the comparator as shown in the embodiment of the present invention, for example, when converting the compensation voltage to the hold amplifier of the sample-and-hold circuit, It has become clear that the gist of the invention can be applied.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the embodiment of FIG. 1, and FIG. 3 is a diagram showing a second embodiment of the invention.

Claims (1)

[Claims] 1. A compared input voltage is applied to one input section,
A voltage comparator to which an offset compensation voltage (described later) is applied to the other input part, a holding circuit for holding the output of the voltage comparator, and a holding circuit for compensating the offset voltage of the voltage comparator in accordance with the output of the holding circuit. A circuit comprising a compensation voltage generation circuit whose output voltage increases and decreases in stages, the compensation voltage generation circuit comprising first means for determining the polarity of the reference voltage based on the output of the holding circuit;
a second means for storing the reference voltage, the polarity of which has been determined, in a first capacitor via a first switch; and a fourth means for applying the voltage of the second capacitor to one input section of the voltage comparator; A compensation circuit for a voltage comparator, characterized in that the second switch operation is performed before the first comparison operation of each sample value of the input signal voltage to be compared is started. 2. In the voltage comparator compensation circuit described in item 1, the compared input signal of the voltage comparator is the sampled and held input signal voltage of the successive approximation type A/D converter, and the sampled and held input signal is A difference signal between the output signal of the D/A conversion circuit that sequentially outputs a comparative approximate voltage for A/D conversion, which is compared with the output voltage of the compensation circuit, and the output of the holding circuit Compensation circuit for voltage comparator whose polarity bit signal is converted by a converter. 3. The voltage comparator compensation circuit according to item 2, wherein the output of the compensation voltage generation circuit is applied to a sampling circuit that obtains the sample signal.