JPS623630B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit used for visual inspection of semiconductor devices and the like.

Conventionally, photodiode arrays (multiple photodiodes arranged in a straight line) are used.
There is a device that converts the appearance pattern of an object to be inspected into a video signal (hereinafter referred to as a video signal), quantizes this video signal using a binarization circuit, and then performs image processing using this quantized digital signal. Are known. The outline of this device is shown as a block diagram in FIG. 1 and will be explained.

In Fig. 1, 1 is a photodiode array, and photodiodes _D1 constituting a bit
~D _o , shift registers 3a and 3b, and load resistances RL ₁ and RL ₂ . A plurality of photodiodes D ₁ to _{D o} are arranged in a straight line, and among them, those with odd number bits (D ₁ , D ₃ , ..., D _o-1 ) are connected to the shift register 3a and the power source E _v . even-numbered bits (D ₂ , D ₄ , ...,
D _o ) is connected in parallel between the shift register 3b and the power source E _v . The shift registers 3a and 3b are driven by the output of the clock generator 2, and are used to sequentially switch the diodes _D1 to _D0 to charge the diodes. An odd-numbered bit video signal is taken out from the tip of the load resistor RL ₁ , and
An even bit video signal is taken out from the tip of RL ₂ . 4 is an operational amplifier (OP Amp), which has a bias resistor R _s and a feedback resistor R _f . The video signal outputs of odd and even bits are commonly applied to the input side of this operational amplifier, and the video signal is amplified. 5 is a binarization circuit to which the output of the threshold voltage (V _th ) setting circuit 6 is applied, which binarizes the amplified video signal V _A in relation to this threshold voltage V _th and outputs it as a digital output. signal
Output as V ₀ . The reason why the photodiodes are divided into odd-numbered bits and even-numbered bits and switched separately as described above is to perform high-speed operation by switching them alternately.

According to the above video signal processing circuit, highly accurate signal processing is possible while the clock frequency is relatively low, but as the frequency increases, the noise figure (S/N ratio) increases.
There is a problem that the accuracy becomes worse.
This seems to be because the video signal waveform is blunted by the stray capacitance of the photodiode array, and the waveform blunting is again amplified by the stray capacitance of the amplifier, causing the level of the amplified video signal waveform to rise. This will be explained in more detail using the waveform diagrams of FIGS. 2 and 3.

Figure 2 shows the conventionally used frequency (approximately 1MHz).
Figure 3 shows the case where signal processing is performed using a high frequency (approximately 3 MHz or higher). In both figures, A shows an example of a pattern, and B shows a video signal waveform when scanning the central part (line A--A) of the pattern in A. In the pattern example, the X portion represents a bright portion, the Y portion represents a minute pattern portion, and the Z portion represents a dark portion.

In the case of low frequency shown in Figure 2, the bright part swings from 0V to -2V (pulses P ₁ , P ₂ , P ₄ ),
The minute pattern portion and the dark portion are only slightly shaken (pulse P ₃ ). Here, the voltage difference V _s between the minute pattern part and the bright part is about 1.5 V or more, so it is easy to set the threshold voltage V _th in the binarization circuit, and the noise margin is large. This seems to be because the effects of stray capacitance of the photodiode and amplifier are ignored due to the low frequency.

In the case of the high frequency shown in Figure 3, the bright part swings to -2V (pulses P ₁ , P ₂ , P ₄ ), but the minute pattern part swings only from -1V to -1.5V (0.5V). No (pulse P ₃ ). Also, the dark parts-
It will fluctuate between 0.5V and -1V. That is, the voltage difference V _s between the minute pattern portion and the bright portion is 0.5V or less. Therefore, it becomes difficult to set the threshold voltage V _th of the binarization circuit, and the noise margin becomes low. The reason for this is that, as mentioned above, there is stray capacitance in the photodiode and amplifier, so as the frequency increases, the first pulse _P1 rises on the power supply side, and then stops falling on the GND side. 2nd pulse while not
This seems to be due to P ₂ rising on the power supply side.

Therefore, an object of the present invention is to provide a video signal processing circuit that is high speed and has high processing accuracy, and another object of the present invention is to provide a video signal processing circuit that is high speed but has a large noise margin. It is in.

An embodiment of the present invention for achieving the above object separately extracts video signals of odd bits and even bits by sequentially switching photoelectric conversion elements constituting a plurality of bits. An amplification means and a binarization means are provided in each bit video signal output stage, and the binarized output on the odd bit side and the binarized output on the even bit side are input to an OR circuit, and from this OR circuit. It is characterized by extracting the output.

The present invention will be specifically described below with reference to embodiments and drawings.

FIG. 4 is a block diagram showing one embodiment of the video processing circuit according to the present invention.

In the figure, 1 is a photodiode array, and a plurality of photodiodes D ₁ to _{D o} constitute a bit.
and shift registers 3a, 3b and load resistance
Consists of RL ₁ and RL ₂ . The photodiodes D ₁ to _{D o} are arranged in a straight line, and among them, those with odd number bits (D ₁ , D ₃ , ..., D _o-1 ) are connected in parallel between the shift register 3a and the power supply E _v The even bits (D ₂ , D ₄ , . . . , D _o ) are connected in parallel between the shift register 3b and the power source E _v .

The shift registers 3a and 3b are driven by the output of the clock generator 2, and are connected to the diodes _D1 to
The D _o is sequentially switched to charge the diode. Odd bit video signals are taken out from the tip of the load resistor RL ₁ , and RL ₂
An even-numbered bit video signal is taken out from the tip. 4a and 4b are operational amplifiers, each having a bias resistance R _s1 (R _s2 ) and a feedback resistance R _f1 (R _f2 ).
has. An odd bit video signal is applied to the operational amplifier 4a, and an even bit video signal is applied to the operational amplifier 4b. This operational amplifier 4
Video signals V _B and V _C amplified by a and 4b
are input to binarization circuits 5a and 5b, respectively.
These binarization circuits 5a and 5b have a threshold voltage (V
_th ) The output of the setting circuit 6 is commonly applied. The amplified video signals V _B and V _C are binarized in relation to the threshold voltage V _th and output as digital outputs V ₁ and V ₂ from the binarization circuits 5a and 5b. Input these outputs V ₁ and V ₂ to the logical sum circuit (OR) 7,
Take out the logical sum output as output V ₀ .

The video signal processing circuit operates as follows. That is, a photodiode can be equivalently replaced with a capacitor, but when this capacitor is exposed to light, the electric charges cancel each other out and the capacitor enters a discharge state. Thereafter, shift registers 3a and 3b corresponding to switches are driven by a clock to switch the discharged photodiode, and a charging current flows from the power source _Ev . This charging current causes a voltage drop across the load resistors RL ₁ and RL ₂ . This voltage is taken out to the outside of the photodiode array 1 as a video signal. And externally, an operational amplifier 4a for amplifying video signals of odd bits is connected.
The signals are each amplified by an operational amplifier 4b for amplifying an even-numbered video signal. These amplified video signals V _B and V _C are provided by binarization circuits 5a and 5b, respectively.
and is converted into digital signals V ₁ and V ₂ in relation to the threshold voltage V _th . The digital signals V ₁ and V ₂ are outputted by the OR circuit 7 as a logical sum output V ₀ . The video signal can be processed based on this output V ₀ .

As described above, the video signal processing circuit allows highly accurate processing even when the switching speed of the photodiode array is increased (the clock frequency is increased). This is because, whereas in the past, both the odd and even video signals were combined into one, amplified by one amplifier, and then binarized, the present invention is capable of combining the odd and even video signals. Since each bit of video signal is individually amplified and binarized, the influence of the operational amplifier's stray capacitance is halved compared to the conventional method, and the rising and falling periods of the amplified video signal waveform are sufficient. This is because it can be harvested. Therefore, if the highest frequency of the operational amplifier is f _nax , the driving frequency of the photodiode array is 2f _nax , allowing high-speed driving.

Hereinafter, the effects of the present invention will be explained in more detail using the waveforms shown in FIG.

FIG. 5 shows the relationship between the conventional amplified video signal waveform V _A at high frequency, the amplified video signal waveforms V _B , V _C and the binarized signal waveforms V ₁ , V ₂ , V ₀ of the present invention. It is a diagram. The pattern shown at the top of the figure is an example of a pattern, in which the X part shows a bright part, the Y part shows a minute pattern part, and the Z part shows a dark part. The signal waveforms in the following stages are the signal waveforms of each part when scanning the central part A-A line of the above pattern example. One of these days,
V _A is the amplified video signal waveform when high frequency is used in the conventional circuit shown in Figure 3B, and V _B and V _C
are the amplified video signal waveforms of odd bits and even bits of the embodiment circuit according to the present invention, and V ₁ and V ₂
are the output waveforms of the binarization circuits 5a and 5b, and V ₀ is the OR
This is the output waveform of circuit 7.

As shown in the figure, the amplified signal waveform V of the conventional circuit
The odd bit pulses (P ₁ , P ₃ , P ₅ , P ₇ ) of _A are the output signal waveform V _B of the operational amplifier 4a in the present invention.
It appears in In addition, even-numbered bit pulses (P ₂ ,
P ₄ , P ₆ , P ₈ ) is the output signal waveform V _C of the operational amplifier 4b
It appears in If we pay attention to the amplified video signal V _B of odd-numbered bits, we can see that the minute pattern part (Y part)
The pulse P ₃ of is equal to the first pulse P ₁ as shown by V _B
has sufficiently fallen to the GND potential side (the second pulse
When P ₂ arrives, the GND potential is maintained)
The voltage will rise slightly to the power supply potential side. Also,
The dark part (Z portion) rises to the power supply potential side after sufficiently falling to the GND potential (pulse P ₅ ,
_P7 ). Next, if we focus on the even-bit amplified video signal V _C , the bright parts always rise sufficiently from the GND potential side to the power supply potential (pulses P ₂ , P ₄ ), and the dark parts always rise slightly from the GND potential side to the power supply potential. It begins to rise to the side (pulses P ₆ , P ₈ ). Then, the threshold voltage V as shown by the dotted line in the signal waveforms V _B and V _C
If _th (approximately -1V) is set, the outputs of the binarization circuit will be _V1 and _V2 , respectively. This OR output has a waveform like V ₀ .

As is clear from the above explanation, the conventional circuit has two
According to the present invention, parts that are difficult to convert into values can be converted into binarized images with high accuracy. Further, since the difference V _s between the voltage of the minute pattern portion and the power supply voltage is about 1.5 V, it becomes easy to select the threshold voltage V _th and a large noise margin can be secured.

The present invention can be widely used in inspection and measurement devices using photodiodes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional signal processing circuit, FIGS. 2A and 2B are an example of a pattern to be measured and a video signal waveform diagram when the conventional circuit is driven at a normal frequency, and FIG. Figures A and B are video signal waveform diagrams when an example of a pattern to be measured and a conventional circuit are driven at a high frequency, Figure 4 is a block diagram showing an example of a video signal processing circuit according to the present invention, and Figure 5 is a diagram of a conventional circuit. FIG. 3 is a diagram showing a relationship between an example of a measurement pattern and a video signal waveform. 1...Photodiode array, 2...Clock generator, 3a, 3b...Shift register, 4,
4a, 4b... operational amplifier, 5, 5a, 5b...
Binarization circuit, 6...Threshold voltage setting circuit, 7...
...OR circuit, RL ₁ , RL ₂ , _Rs1 , _Rs2 , R _f , R _f
1 , R _f2 ...resistance, D ₁ -D _o ... photodiode.

Claims (1)

[Claims] 1. When reading electrical signals corresponding to optical data from a plurality of photoelectric conversion elements arranged almost in a straight line, the electrical signals are sequentially read out from the first group of elements at discrete positions among the plurality of photoelectric conversion elements. At the same time, electrical signals are sequentially extracted from the elements of the second group at discrete positions different from the elements of the first group at timings different from those of the elements of the first group. , the electrical signal from the first group of elements is amplified by the first amplifying means, and the electrical signal from the second group of elements is amplified by the second amplifying means, the first, An optical device characterized in that the outputs of the second amplifying means are supplied to respective binarizing means, and a quantized video signal is obtained by logically synthesizing the outputs of the binarizing means. signal processing circuit.