JPS623635B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time code capture device suitable for use in a video tape recorder automatic editing device, and in particular, it is capable of accurately synchronizing the capture of a time code signal with frames of a video signal with a simple configuration. I made it possible.

An example in which the time code importing device of the present invention is used in an automatic video tape recorder editing device will be explained below with reference to the drawings.

In FIG. 1, 1a and 1b each indicate a video tape recorder (hereinafter abbreviated as VTR), and these VTRs 1a and 1b each record an absolute address signal such as an SMPTE time code that advances sequentially at the timing of each frame. In this example, a predetermined video signal reproduced by the VTR 1a is dubbed to a predetermined position on the videotape by the VTR 1b. It is something.

Further, 2 indicates a main control device, and this main control device 2 is
The VTR 1a and 1b are all configured to be program-controlled. This main control device 2 is VTR1
A position detection circuit 2a is configured to read the absolute address signals (hereinafter abbreviated as time code signals) of each of a and 1b to know the recording or playback position of the videotape, and The phase detection circuits 2b and 2c detect the phase of the frame signal (recorded at the beginning of the absolute address signal, for example), and the respective output signals of the position detection circuit 2a and the phase detection circuits 2b and 2c are supplied. The judgment function circuit 2d determines the next operation based on the contents of the judgment function circuit 2d, and the operation command circuit 2e instructs the operation of the VTRs 1a and 1b based on the output signal of the judgment function circuit 2d. The main controller 2 is also connected to VTR control interfaces 3a and 3b via bus lines, and the VTR control interfaces 3a and 3b are connected to VTRs 1a and 1b, respectively. The VTR control interfaces 3a and 3b are constructed in the same way.
The VTR control interfaces 3a and 3b each include an input/output buffer circuit 5 connected to the bus line on the main controller 2 side, and a play run command circuit that issues a play run command based on the output signal of the input/output buffer circuit 5. 6, and based on the output signal of this input/output buffer circuit 5, ±0% speed running command, + several % to +10% speed running command, and -
A ±0% speed driving command circuit 7, a +several % to +several 10% speed driving command circuit 8, and a −several % to −several 10% speed driving command circuit 9, each issuing a speed driving command of several % to -several 10%. , the respective output signals of the play running command circuit 6, the ±0% speed running command circuit 7, the +several % to +several 10% speed running command circuit 8, and the -several % to -several 10% speed running command circuit 9. is supplied, and its output side is the VTR
It is composed of a VTR control buffer circuit 10 connected to bus lines 1a and 1b, and a phase matching pulse detection circuit 11. The main controller 2 is also connected via a bus line to reader interfaces 4a and 4b to which the reproduction time code signals of the VTRs 1a and 1b are supplied, respectively. The reader interfaces 4a and 4b are configured similarly, and each of the reader interfaces 4a and 4b is connected to the VTR 1.
It has a time code readout circuit 12 to which reproduced time code signals from a and 1b are supplied, and the time code data obtained at one output side of this time code readout circuit 12 is supplied to a time code buffer memory 13, Further, the frame signal obtained at the other output side of the time code readout circuit 12 is supplied to one input terminal of the AND circuit 14, and this frame signal is passed through the delay circuit 15 to reset the flip-flop circuit constituting the latch circuit 16. terminal and this latch circuit 1
6 is supplied to the other input terminal of the AND circuit 14. This delay circuit 15 has a delay time sufficient for the frame signal to pass through the AND circuit 14, and after the frame signal passes through the AND circuit 14, the latch circuit 16 is reset.

The present invention is constructed as follows. That is, the output signal of the AND circuit 14 is supplied to the set terminal of the flip-flop circuit constituting the damped flag signal forming circuit 17.
The output signal is supplied to an input/output buffer circuit 18 connected to the main controller 2 via a bus line. In this case, when a capture (hereinafter referred to as read) command signal is supplied from the main controller 2 to this input/output buffer circuit 18, only when there is an output signal from the damp flag circuit 17, the time code buffer memory 13 stores the command signal. It starts reading out the time code data that has been set and sends it to the main controller 2. Further, when reading out the time code data stored in the time code buffer memory 13 is started, a read start pulse is obtained from the time code buffer memory 13, and this read start pulse is supplied to the reset terminal of the flip-flop circuit 17. Also, when reading out the time code data from the time code buffer memory 13 is completed, a read end pulse is obtained, and this read end pulse is supplied to the set terminal of the latch circuit 16. Set after reading is completed.

Since the present invention is configured as described above, reading out a time code signal is performed as follows. That is,
The time code reading circuit 12 of the reader interface 4a, 4b reads the time code signal recorded on the magnetic tape loaded in the VTR 1a, 1b frame by frame, decodes the time code signal, and converts it into time code data. Time code data for one frame is sent to a time code buffer memory 13 to be recorded and held. Since a new time code signal is read every frame, the time code data stored in the time code buffer memory 13 is also read out by the time code reading circuit 12 every frame.
updated with new timecode data sent from. Further, the output signal of the damp flag signal forming circuit 17 is normally held at "1". When the main controller 2 needs to refer to time code data, the main controller 2 sends a message to the reader interface 4.
A test command is issued to the input/output buffer circuit 18 of the reader interfaces 4a and 4b to detect whether the damp flag is "1" or "0", and if the damp flag signal from the reader interfaces 4a and 4b is "1". After confirming that the time code data is present, send the time code data sending command to the reader interface 4a
In response to this time code data sending command, the time code data stored in the time code buffer memory 13 is sent to the main controller 2 via the input/output buffer circuit 18. In this case, once time code data begins to be read out from the time code buffer memory 13, until all digits of information of this time code data have been read out,
The contents of the time code buffer memory 13 are not updated. This prevents the content of the time code from changing while reading the time code signal, thereby preventing erroneous reading. In this case, when the damp flag signal from the reader interfaces 4a, 4b is "0", the test of the damp flag signal is repeated until the damp flag signal becomes "1". Further, when the reading of time code data from the time code buffer memory 13 starts, the damp flag signal forming circuit 17 is reset by receiving a read start pulse from the time code buffer memory 13, and the output damp flag signal is "0", but once reading of time code data starts, it becomes 1 regardless of the state of the Dan flag signal.
The read operation continues until reading of time code data for frames is completed. When the reading of this time code data is completed, this reading end pulse is supplied to the set terminal of the latch circuit 16, and the output signal of this latch circuit 16 is set to "1". When a frame signal is supplied from 12, this frame signal is supplied to the set terminal of the damped flag signal forming circuit 17 via the AND circuit 14, and the output signal of this damped flag signal forming circuit 17 is set to "1". Also, in this latch circuit 16, the frame signal is delayed by a predetermined time by the delay circuit 15 and supplied to the reset terminal, and then this latch circuit 16 is reset and its output signal is set to "0", so that the time code buffer memory 13 This function functions to prevent a malfunction in which the next frame signal is inputted and the damp flag signal becomes "1" before the readout of time code data for one frame is completely completed, and the next readout is started.

In the present invention, this time code data reading operation is performed twice in succession. In this way, the readout timing of the second readout time code automatically coincides with the frame signal. This situation will be explained using the time chart shown in FIG. 2A is a frame signal, and FIG. 2B is a reset pulse sent to the latch circuit 16, in which the frame signal A is delayed by a predetermined time by the delay circuit 15. FIG. 2C shows the contents of the time code data stored in the time code buffer memory 13, and FIG.
This shows how the readout command signal continues. Also, FIG. 2 E is a dumb flag signal,
FIG. 2F shows the timing of starting and ending reading of time code data from the time code buffer memory 13, and FIG. 2G shows the state of the latch circuit 16.

When the main controller 2 outputs the read command shown in FIG. 2D, the input/output buffer 18 checks the state of the damp flag signal and determines whether to start reading data from the time code buffer memory 13. As shown in FIG. 2E, the damp flag signal is normally kept at "1".
Then, at the same time that the read start command (D in Figure 2) becomes "1", the time code buffer memory 13
The read start pulse resets the dumb flag forming circuit 17 and the dumb flag signal becomes "0", but as mentioned above, the read operation continues until all the time code data for one frame is read out. I can continue. Next, when the reading of time code data from the buffer memory 13 is completed, a reading end pulse is generated and the latch circuit 16 is set.

The first time readout of time code data is completed with the operations up to this point, but the readout timing at this time only depends on the timing of the readout command shown in Figure 2D, and the frame signal (Figure 2A) It is clear that they are not synchronized at all. As mentioned above, the read command lasts for two times of time code reading, but since the damp flag signal falls to "0" at the start timing of the first time code data read, the first time After the reading of the code data is completed, it is not possible to immediately start reading the second time code data. Therefore, the input/output interface 18 continues to monitor the dunn flag signal, and the dunn flag signal becomes "0".
The second time code reading is started the moment the time code becomes "1". The timing at which the damp flag signal rises from "0" to "1" is the timing when the next frame signal F _o+1 sets the damp flag signal forming circuit 17 via the AND circuit 14, as shown in FIG. 2E. Therefore, the second reading of time code data is started in coincidence with the input timing of the frame signal F _o+1 . When the second time code data reading is started, the damp flag signal becomes "0" level, and the next frame pulse F _o+
However , at this time, the time code data read command has not already been given to the input/output buffer, so the third time code data readout will not start.

Therefore, according to the present invention, it is possible to accurately synchronize the acquisition of a time code signal with the frame of a video signal.

Next, a case will be described in which the two VTRs 1a and 1b are synchronized with the desired positional relationship of the video tapes using a flowchart as shown in FIG.
In this case, the absolute addresses of the time code signals of the video tape frames that are desired to match on the two VTRs 1a and 1b are respectively T _Ap and T _Bp , and T _A and T _B are read from the VTRs 1a and 1b, respectively. Assuming that the time code signal is a time code signal, it is sufficient to detect T _{Ap -TA} = T _Bp - T _B. If this formula is transformed, it becomes T _A - T _B = (T _Ap - T _Bp ). Therefore, the difference in time code read from these two VTRs 1a and 1b (T _Ap - T
All you have to do is monitor whether it has become _Bp ).

First, pre-roll VTR1a and 1b to appropriate positions, then run VTR1a in the playback state, and increase VTR1b by a few percent to +10
% speed. First, VTR1a at this time is placed in advance, and then this VTR1a is set at an appropriate time.
VTR 1b may be run so as to follow a. The main controller 2 detects whether a frame signal from the VTR 1a as shown in FIG. 2A and a frame signal from the VTR 1b as shown in FIG. 2H match in phase within a predetermined error range. in this case
Since the speeds of the VTRs 1Ma and 1b are slightly different, the phases shift sequentially for each frame, but there is a time when they are substantially in agreement, and this is detected. Both of these
The frame signals of VTR1a and 1b are
The state of substantially matching is repeated at a certain period depending on the speed difference between 1a and 1b. The VTR control interfaces 3a and 3b read out the state "1" in which the frame signals substantially match, and only when this phase match signal is "1", the VTR is controlled as described above.
Read and check the time code signal 1a. In this case, first, the main controller 2 reads the time code signal of the VTR 1a from the reader interface 4a at an arbitrary time twice in succession as shown in _{FIG .} ≦T−T ₁ , where T is the interframe error and T ₁ is
This time corresponds to the phase difference between the VTRs 1a and 1b. ) is read once as the time code signal T _B of VTR 1b as shown in Figure 2 J. In this case, two VTRs
1a and 1b are operated in a frame synchronized state, and the reader interface 4a
The second time code signal T read out from
Since _A is synchronized with the frame signal as mentioned above, the time code signal T _B read out from this VTR 1b after a predetermined time T ₀ after this second time code signal T _A is read out is also synchronized with the frame timing. I will do it. In this case, if the delay time T ₀ is set to approximately half the frame signal period, even if the phase of the frame signal of the magnetic tape of the VTR 1a and the frame signal of the magnetic tape of the VTR 1b are slightly different, The data captured at t=n and t=m in FIGS. 2A and 2H will be read, and no misreading will occur due to timing differences.

For example, as shown in Figure 2 A and H, VTR1a
and VTR1b are operated with their phases aligned within a predetermined range, and by the method described above, VTR1a
Assume that reading of time code data t=n starts at time a. If the time code of VTR 1b is read out at the same timing a as that of VTR 1a, the time code signal t=m from VTR 1b has not been completely reproduced and decoded yet, so the time code buffer is read out as shown in Figure 2I. There is time code data in the memory.
=m-1 remains, which will be read out. Although VTR1a and 1b are operated in almost synchronized condition, each
Since the time code data 1 read from the VTR is shifted by a frame, the main controller 2
It is determined that the two VTRs are not being operated in the correct relationship, and the above-mentioned correction is applied to the running of the VTRs, resulting in the two VTRs losing the correct synchronization relationship.

In the present invention, this malfunction is prevented by reading the time code data in the VTR 1b a predetermined time _T0 after reading the time code data in the VTR 1a.

Then, compare the time codes T _A and T _B read from the VTRs 1a and 1b, respectively, and if T _A − T _B > (T _Ap − T _Bp ), set the VTR 1 b at a speed of + several % to + several times more than the running speed of the VTR 1 a. If T _A −T _B <(T _Ap −T _Bp ), the VTR 1b is caused to run at a speed of -several % to -several 10% of the running speed of the VTR 1a. When this is repeated and T _A - T _B = (T _Ap - T _Bp ), a run command is first given to the VTR 1b at the same speed as the play speed without going through the servo loop.
Thereafter, the VTRs 1a and 1b are run in this state, and after a certain period of time has elapsed, this comparison operation is performed a predetermined number of times, for example, three times, and when this T _A - T _B = (T _Ap - T _Bp ) is maintained, the VTR 1b If you lock the servo loop and give a play command to record it,
The VTR 1a and VTR 1b can be accurately synchronized frame by frame, and a predetermined video signal from the VTR 1a can be dubbed to a predetermined position on the magnetic tape of the VTR 1b. In FIG. 3, X is a function that counts the number of loops.

As described above, the above example has the advantage that the target frames of the video tapes of the VTRs 1a and 1b can be synchronized with high accuracy.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various other configurations can be adopted without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example in which an embodiment of the time code importing device of the present invention is used in a video tape recorder automatic editing device, FIG. 2 is a line diagram showing a time chart used to explain the present invention, and FIG. is the first
FIG. 2 is a diagram showing a flowchart for explaining the figure. 1a and 1b are VTRs, 2 is a main control device,
3a and 3b are VTR control interfaces, 4a and 4b are reader interfaces, 12 is a time code reading circuit, 1
3 is a time code buffer memory, and 17 is a flip-flop circuit constituting a damp flag signal forming circuit.

Claims (1)

[Scope of Claims] 1. A time code signal reading circuit that reads out a video signal and a time code signal corresponding to the video signal from a recording medium on which the time code signal is recorded, and a memory that stores time code data output from the reading circuit. means, a frame signal separation circuit for obtaining a frame signal synchronized with the frame of the video signal, a read start signal indicating that reading of the time code data from the memory means has started, the frame signal, and an external source. and a data read control circuit which is supplied with a time code capture command signal and controls reading of the time code data from the memory means, and the data read control circuit is supplied with the time code capture command signal. The time code data is read out from the memory means twice in succession, and the read start signal indicating the start of the first time code data read out of the two time code data reads is sent to the memory means. After prohibiting the start of continuous reading of the time code data from the means, the device operates to start reading the time code data a second time by the frame signal, and the time code data is read out in synchronization with the frame signal. A time code capture device characterized by capturing second time code data as time code data.