JPS6236394B2 - - Google Patents
Info
- Publication number
- JPS6236394B2 JPS6236394B2 JP56125465A JP12546581A JPS6236394B2 JP S6236394 B2 JPS6236394 B2 JP S6236394B2 JP 56125465 A JP56125465 A JP 56125465A JP 12546581 A JP12546581 A JP 12546581A JP S6236394 B2 JPS6236394 B2 JP S6236394B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- lead
- lead frame
- film
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/411—Chip-supporting parts, e.g. die pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/456—Materials
- H10W70/457—Materials of metallic layers on leadframes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07141—Means for applying energy, e.g. ovens or lasers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07521—Aligning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/879—Bump connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置用リードフレーム、特に、
リードフレーム材の所定領域にのみボンデイング
のための貴金属膜を被着したリードフレームに関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to lead frames for semiconductor devices, particularly,
The present invention relates to a lead frame in which a noble metal film for bonding is coated only on a predetermined region of the lead frame material.
樹脂封止型半導体装置の製造等に用いられるリ
ードフレームは半導体素子をマウントするための
アイランド部および該アイランド部から離間して
その周囲に配設されたリード部を備えている。第
１図Ａは従来のリードフレームにおけるアイラン
ド部とリード部を示す斜視図である。同図におい
て、１はアイランド部である。該アイランド部１
の周囲には複数のリード部２がアイランド部１か
ら離間して配設されている。このリード部２はそ
の外側の図示しないリードフレーム外枠に連結さ
れ、また前記アイランド部１はブリツジ部３を介
してリードフレーム外枠に連結されている。そし
て、アイランド部１およびブリツジ部３に亘る表
面、並びに、リード部２の先端部表面には化学メ
ツキにより図中斜線を付して示すAu膜が被着さ
れている。このリードフレームを用いて樹脂封止
型半導体装置を製造する際には、まず、第２図に
示すように、半導体素子４をアイランド部１上に
ダイボンデイングする。このダイボンデイングで
はアイランド部表面に化学メツキされたAu膜と
半導体素子との共晶反応により良好なボンデイン
グ状態が得られる。続いて、第３図に示すよう
に、半導体素子４上に設けられているボンデイン
グパツド５とリード部２のAu膜を化学メツキさ
れた部分とをAu、Al等の細線からなるボンデイ
ング線６を介して接続し（以下、リード部におけ
るワイヤボンデイング位置をボンデイングポスト
と言う）、更にエポキジ樹脂等の封脂樹脂をモー
ルドして気密封止を行なう。 A lead frame used for manufacturing a resin-sealed semiconductor device, etc. includes an island portion for mounting a semiconductor element and a lead portion spaced apart from the island portion and arranged around the island portion. FIG. 1A is a perspective view showing an island portion and a lead portion in a conventional lead frame. In the figure, 1 is an island portion. The island part 1
A plurality of lead portions 2 are arranged around the island portion 1 at a distance from the island portion 1 . The lead portion 2 is connected to a lead frame outer frame (not shown) on the outside thereof, and the island portion 1 is connected to the lead frame outer frame via a bridge portion 3. The surface of the island portion 1 and the bridge portion 3 as well as the surface of the tip portion of the lead portion 2 are coated with an Au film indicated by diagonal lines in the figure by chemical plating. When manufacturing a resin-sealed semiconductor device using this lead frame, first, as shown in FIG. 2, the semiconductor element 4 is die-bonded onto the island portion 1. In this die bonding, a good bonding state is obtained due to the eutectic reaction between the Au film chemically plated on the surface of the island portion and the semiconductor element. Subsequently, as shown in FIG. 3, the bonding pad 5 provided on the semiconductor element 4 and the part of the lead part 2 on which the Au film has been chemically plated are bonded with a bonding wire 6 made of a fine wire of Au, Al, etc. (hereinafter, the wire bonding position in the lead portion is referred to as a bonding post), and is further hermetically sealed by molding a sealing resin such as epoxy resin.
ところで、こうして製造された樹脂封止型半導
体装置においては前記ボンデイングワイヤ６によ
る接続の良否が装置の信頼性に大きく影響する。
そして、リードフレーム材には通常Cu、Niまた
はこれらの合金、あるいはFe、コバール等のボ
ンデイング性の低い材料が用いられるため、上記
のようにボンデイング性に優れたAu膜をボンデ
イングポスト表面に化学メツキすることによりワ
イヤボンデイングの信頼性を向上させたリードフ
レームが用いられる。このAu膜は、以前はリー
ドフレームの全面に施されていたが、貴金属の高
騰等から必要な部分にのみAuメツキを行なうよ
うになつたものである。また、最近では半導体素
子４とアイランド部１との間に電気的な接続を必
要としない半導体装置も増え、この場合には上記
のようなAu共晶法によるダイボンデイングに替
えてAgペーストによるダイボンデイングを採用
することによりAu使用量の節減が計られてい
る。更に、最近の自動ボンデイング装置ではボン
デイングの位置精度が大幅に向上し、これに伴つ
てボンデイングポスト表面のAuメツキ面積を縮
小してAu使用量を節減することも可能となつ
た。 Incidentally, in the resin-sealed semiconductor device manufactured in this way, the quality of the connection by the bonding wire 6 greatly influences the reliability of the device.
Since lead frame materials are usually made of Cu, Ni or their alloys, or materials with poor bonding properties such as Fe and Kovar, it is necessary to chemically plate the surface of the bonding post with an Au film that has excellent bonding properties as described above. By doing so, a lead frame with improved wire bonding reliability is used. This Au film used to be applied to the entire surface of the lead frame, but due to the soaring price of precious metals, it became possible to apply Au plating only to the necessary parts. Furthermore, recently, the number of semiconductor devices that do not require electrical connection between the semiconductor element 4 and the island portion 1 has increased, and in this case, die bonding using Ag paste is used instead of die bonding using the Au eutectic method as described above. The use of bonding reduces the amount of Au used. Furthermore, with recent automatic bonding equipment, the positional accuracy of bonding has been greatly improved, and this has made it possible to reduce the amount of Au used by reducing the area of Au plating on the surface of the bonding post.
このように、リードフレームにおけるAuメツ
キの面積は徐々に縮小され、更にボンデイングポ
スト表面でもAuメツキに替えてAg等の他の貴金
属メツキを施したリードフレームも使用されるよ
うになつた。その結果、コストは大幅に低減され
ることになつたが、ボンデイングポスト表面にこ
れら貴金属の化学メツキを施すという方法自体は
何等かわつていない。そして、化学メツキによる
これら貴金属の被着方法は最も効率が高い反面、
メツキ溶からCl、Na等による汚染を受け易いと
いう問題があつた。これらの汚染物質、特に
Cl、Naは樹脂封止後の半導体素子に悪影響を及
ぼす危険性が高いから、IC、LSI等の半導体装置
に厳しい信頼性が要求される今日、このような汚
染を完全に排除したリードフレームが要望されて
いる。また、化学メツキを施したリードフレーム
では、このような装置の信頼性に直結する問題以
外にも、その製造上、公害対策のために特別の設
備を必要とするという問題があつた。 In this way, the area of Au plating on lead frames has been gradually reduced, and lead frames with other noble metal plating such as Ag instead of Au plating on the bonding post surfaces have also come to be used. As a result, the cost has been significantly reduced, but the method itself of chemically plating the surface of the bonding post with these noble metals has not changed in any way. While chemical plating is the most efficient method of depositing precious metals,
There was a problem in that it was susceptible to contamination by Cl, Na, etc. from the metallurgy. These pollutants, especially
Since Cl and Na have a high risk of adversely affecting semiconductor elements after resin encapsulation, in today's world where strict reliability is required for semiconductor devices such as ICs and LSIs, lead frames that completely eliminate such contamination are needed. It is requested. In addition to the problems directly connected to the reliability of such devices, chemically plated lead frames also have the problem of requiring special equipment to prevent pollution during manufacture.
本発明は上述の事情に鑑みてなされたもので、
ボンデイングポストその他ボンデイングに必要な
部分にのみ選択的に、かつCl、Na等に汚染され
ることなくボンデイングのための貴金属を被着
し、もつて貴金属の使用量を節減すると共に前記
汚染物による影響を回避した半導体装置用リード
フレームを提供するものである。 The present invention was made in view of the above circumstances, and
Precious metals for bonding are selectively applied to bonding posts and other parts necessary for bonding without being contaminated by Cl, Na, etc., thereby reducing the amount of precious metals used and reducing the effects of the above contaminants. The present invention provides a lead frame for a semiconductor device that avoids the above problems.
以下、第４図を参照して本発明の１実施例を説
明する。 Hereinafter, one embodiment of the present invention will be described with reference to FIG.
第４図は本発明の１実施例になる半導体装置用
リードフレームにおけるアイランド部およびその
周囲に配設されたリード部を示す斜示図である。
同図において、１１はアイランド部である。該ア
イランド部１１の周囲には複数のリード部１２が
アイランド部１１から離間して配設されている。
このリード部１２はその外側の図示しないリード
フレーム外枠に連結され、また前記アイランド部
１１はブリツジ部１３を介してリードフレーム外
枠に連結されている。リード部１２のボンデイン
グポスト表面およびアイランド部１１の表面には
蒸着によりスポツト的にAu膜１４が被着されて
いる。 FIG. 4 is a perspective view showing an island portion and a lead portion disposed around the island portion in a lead frame for a semiconductor device according to an embodiment of the present invention.
In the figure, 11 is an island portion. A plurality of lead portions 12 are arranged around the island portion 11 and spaced apart from the island portion 11 .
The lead portion 12 is connected to an outer frame of a lead frame (not shown) on the outside thereof, and the island portion 11 is connected to the outer frame of the lead frame via a bridge portion 13. The surface of the bonding post of the lead portion 12 and the surface of the island portion 11 are coated with an Au film 14 in spots by vapor deposition.
上記実施例のリードフレームを用いた場合に
も、従来と同様に樹脂封止型半導体装置を製造す
ることができる。第５図は第４図のアイランド部
１１に半導体素子１５をマウントし、該半導体素
子のボンデイングパツド１６とAu膜１４を蒸着
したボンデイングポストとをボンデイング線１７
によりワイヤボンデイングした状態を示す断面図
である。ワイヤボンデイングは自動ボンデイング
装置を用いて行なうが、既述のように最近の自動
ボンデイング装置はボンデイング位置精度が極め
て高いから、ボンデイングポストにおけるAu膜
１４の被着をスポツト的に行なつた場合にも充分
に信頼性の高いボンデイングを行なうことができ
る。第６図は自動ボンデイング装置によりワイヤ
ボンデイングを行なつている状態を示す断面図で
ある。同図において、１８はボンデイングルール
の先端部である。 Even when the lead frame of the above embodiment is used, a resin-sealed semiconductor device can be manufactured in the same manner as before. FIG. 5 shows that a semiconductor element 15 is mounted on the island part 11 of FIG.
FIG. 3 is a sectional view showing a state in which wire bonding is performed. Wire bonding is performed using automatic bonding equipment, but as mentioned above, recent automatic bonding equipment has extremely high bonding position accuracy, so even if the Au film 14 is deposited spot-on on the bonding post, Bonding can be performed with sufficient reliability. FIG. 6 is a sectional view showing a state in which wire bonding is being performed by an automatic bonding device. In the figure, 18 is the tip of the bonding rule.
上記実施例のリードフレームでは、Au膜１４
が化学メツキによらずに蒸着によつて被着したも
のであるから、従来のリードフレームのように半
導体素子に悪影響を及ぼすCl、Na等の物質で汚
染されることがない。また、その製造に際して排
水処理等、公害対策のための特別な設備を必要と
することもない。更に、Au膜４をスポツト的に
蒸着する方法は、化学メツキ法に比較してリード
フレームの限られた領域にのみAu膜を被着する
のが容易であるから、Auの使用量を節減すると
意味からも従来のリードフレームより優れてい
る。 In the lead frame of the above embodiment, the Au film 14
Since it is deposited by vapor deposition rather than chemical plating, unlike conventional lead frames, it is not contaminated with substances such as Cl and Na that adversely affect semiconductor devices. Further, during its production, special equipment for pollution control such as wastewater treatment is not required. Furthermore, the method of spot-depositing the Au film 4 makes it easier to deposit the Au film only on a limited area of the lead frame compared to the chemical plating method, which reduces the amount of Au used. It is also superior to conventional lead frames in terms of meaning.
なお、上記実施例において、半導体素子１５の
ダイボンデイングを銀ペーストにより行なう場合
には、アイランド部１１上にAu膜１４を被着す
る必要はない。 In the above embodiment, when die bonding of the semiconductor element 15 is performed using silver paste, it is not necessary to deposit the Au film 14 on the island portion 11.
また、Au膜１４は圧着、熔着等、蒸着以外の
物理的方法により被着したものでもよい。 Further, the Au film 14 may be deposited by a physical method other than vapor deposition, such as compression bonding or welding.
更に、Au膜１４の代りに同様の物理的方法に
より被着されたAg膜等の他の貴金属膜を用いる
こともできる。 Further, instead of the Au film 14, other noble metal films such as an Ag film deposited by a similar physical method can also be used.
以上詳述したように、化学メツキによらず、蒸
着、圧着、熔着等方法によりボンデイングのため
の貴金属膜を被着した本発明のリードフレームに
よれば、Cl、Na等の半導体素子に悪影響を及ぼ
す物質による汚染を回避できると共に、その製造
に際して公害対策のための特別な設備を必要とし
ない等、顕著な効果を得ることができる。 As detailed above, according to the lead frame of the present invention in which a noble metal film for bonding is coated by a method such as vapor deposition, compression bonding, or welding without chemical plating, Cl, Na, etc. have an adverse effect on semiconductor elements. It is possible to avoid contamination caused by substances that cause pollution, and to obtain remarkable effects such as not requiring special equipment for pollution control during production.
第１図は従来のリードフレームの要部を示す斜
視図、第２図は第１図のリードフレームに半導体
素子をマウントした状態を示す斜視図、第３図は
第２図の状態に更にワイヤボンデイングを行なつ
た状態を示す斜視図、第４図は本発明の１実施例
になるリードフレームの要部を示す斜視図、第５
図は第４図のリードフレームに半導体素子をマウ
ントし、更にワイヤボンデイングを行なつた状態
を示す断面図、第６図はボンデイングツールによ
るワイヤボンデイングの状態を示す断面図であ
る。
１１……アイランド部、１２……リード部、１
３……ブリツジ部、１４……Au膜、１５……半
導体素子、１６……ボンデイングパツド、１７…
…ボンデイング線、１１８……ボンデイングツー
ルの先端部。
Fig. 1 is a perspective view showing the main parts of a conventional lead frame, Fig. 2 is a perspective view showing a state in which a semiconductor element is mounted on the lead frame shown in Fig. 1, and Fig. 3 is a perspective view showing the state shown in Fig. 2 with additional wiring. FIG. 4 is a perspective view showing the main parts of a lead frame according to an embodiment of the present invention; FIG.
This figure is a sectional view showing a state in which a semiconductor element is mounted on the lead frame shown in FIG. 4 and wire bonding is further performed, and FIG. 6 is a sectional view showing a state in which wire bonding is performed using a bonding tool. 11...Island part, 12...Lead part, 1
3... Bridge portion, 14... Au film, 15... Semiconductor element, 16... Bonding pad, 17...
...Bonding line, 118...Tip of bonding tool.
Claims (1)
部と、該アイランド部から離間してその周囲に配
設されたリード部と、該リード部のボンデイング
ポスト部にスポツト的に被着された、半導体素子
に悪影響を及ぼす物質で汚染されていないボンデ
イングのための貴金属膜とを具備し、該金属膜が
蒸着、圧着または溶着により被着されていること
を特徴とする半導体装置用リードフレーム。1. An island part for mounting a semiconductor element, a lead part arranged around the island part at a distance from the island part, and a bonding post part of the lead part that is adhered in spots, which has an adverse effect on the semiconductor element. 1. A lead frame for a semiconductor device, comprising: a noble metal film for bonding that is not contaminated with substances that cause oxidation, and the metal film is adhered by vapor deposition, compression bonding, or welding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56125465A JPS5827353A (en) | 1981-08-11 | 1981-08-11 | Lead frame or semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56125465A JPS5827353A (en) | 1981-08-11 | 1981-08-11 | Lead frame or semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5827353A JPS5827353A (en) | 1983-02-18 |
| JPS6236394B2 true JPS6236394B2 (en) | 1987-08-06 |
Family
ID=14910754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56125465A Granted JPS5827353A (en) | 1981-08-11 | 1981-08-11 | Lead frame or semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827353A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS596850U (en) * | 1982-07-06 | 1984-01-17 | 日本電気株式会社 | Lead frame for semiconductor devices |
| US4612564A (en) * | 1984-06-04 | 1986-09-16 | At&T Bell Laboratories | Plastic integrated circuit package |
| JPS6113653A (en) * | 1984-06-29 | 1986-01-21 | Dainippon Printing Co Ltd | Coating method of metallic section of semiconductor lead frame |
| JPH0671058B2 (en) * | 1985-06-05 | 1994-09-07 | 日立電線株式会社 | Manufacturing method of lead frame having minute spot-like plated portion |
| JPH02205062A (en) * | 1989-02-02 | 1990-08-14 | Nec Kyushu Ltd | Lead frame |
| JPH0391251A (en) * | 1989-09-01 | 1991-04-16 | Nippon Avionics Co Ltd | Copper pattern board for chip on-board type hybrid ic |
| WO2005022633A1 (en) * | 2003-08-29 | 2005-03-10 | Infineon Technologies Ag | Chip support of a lead frame for an integrated circuit package |
| US20250273540A1 (en) | 2024-02-28 | 2025-08-28 | Stmicroelectronics International N.V. | Method of manufacturing semiconductor devices and corresponding semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS553641A (en) * | 1978-06-23 | 1980-01-11 | Hitachi Ltd | Lead frame |
-
1981
- 1981-08-11 JP JP56125465A patent/JPS5827353A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5827353A (en) | 1983-02-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6194777B1 (en) | Leadframes with selective palladium plating | |
| US7872336B2 (en) | Low cost lead-free preplated leadframe having improved adhesion and solderability | |
| US7413934B2 (en) | Leadframes for improved moisture reliability and enhanced solderability of semiconductor devices | |
| US7368328B2 (en) | Semiconductor device having post-mold nickel/palladium/gold plated leads | |
| US10727169B2 (en) | Semiconductor device having lead with back and end surfaces provided with plating layers | |
| JPS6236394B2 (en) | ||
| US20060125062A1 (en) | Semiconductor package having improved adhesion and solderability | |
| US5935719A (en) | Lead-free, nickel-free and cyanide-free plating finish for semiconductor leadframes | |
| JP2002064173A (en) | Pre-plating of no-lead / lead frame with small semiconductor outline | |
| US5345038A (en) | Multi-layer ceramic packages | |
| US6180999B1 (en) | Lead-free and cyanide-free plating finish for semiconductor lead frames | |
| JPS60147148A (en) | Lead frame for semiconductor device | |
| JPH0410699Y2 (en) | ||
| JPS62287657A (en) | Semiconductor device | |
| JPS634945B2 (en) | ||
| JPS61278158A (en) | Lead frame for semiconductor device | |
| JPH04155949A (en) | Resin-sealed semiconductor device | |
| JPS6050342B2 (en) | Lead frame for semiconductor device manufacturing | |
| JPH0284744A (en) | Manufacture of semiconductor device | |
| JPH02250364A (en) | Leadframe and its manufacture | |
| JPH0553310B2 (en) | ||
| JPH0689478B2 (en) | Method for manufacturing resin-sealed semiconductor device | |
| JPS6244545Y2 (en) | ||
| JPH04322435A (en) | Semiconductor device and manufacture thereof | |
| TW483057B (en) | Semiconductor device with bump electrode |