JPS6236418B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to fixed pattern suppression schemes in digital data transmission systems.

In conventional PCM transmission systems, when a logic "0" pattern of digital data occurs continuously,
Phase jitter and associated code errors occur in the timing signal that occurs in the PCM repeater. For this reason
The PCM terminal equipment uses a logic "0" pattern suppression method to deal with the above drawbacks. Specifically, the logic "0" pattern suppression method monitors the input data of the PCM terminal equipment word by word, and when consecutive words of logic "0" are detected, the bit with the lowest weight in the word is forcibly selected. This method replaces the output with logic “1”. In order to use this method, it is necessary that the influence of code errors caused by data replacement on the quality of data does not pose a practical problem. Therefore, the logic "0" pattern suppression method uses a signal from which redundant bits have been removed as much as possible, such as a band-compressed digital TV signal, and a band-compression encoding method such as variable-length encoding that makes it possible to determine the weight of each bit of data. Not suitable for difficult signals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fixed pattern suppression method that eliminates the above-mentioned drawbacks.

The system of the present invention includes an input means for receiving a digital data string having N (N is a positive integer) units of one frame each having n (n is a positive integer) bit data, and input data given to this input means. a detection means for detecting whether or not a predetermined fixed pattern is included in the N frames of the column; an interrupt means for forcibly interrupting the redundant bit; a prohibition means for prohibiting the interrupt means from taking in the input data string for the time required for the interruption of the redundant bit; and based on a detection signal from the detection means. Said N
Display information generating means for generating display information having an interrupt indication bit indicating whether or not an interrupt has occurred in a frame and an error correction bit generated for the interrupt indication bit; and display information generated by the generating means. and a multiplexing means for multiplexing the input data string applied to the input means or the input data string to which redundant bits are applied as interrupt bits by the interrupt means.

Next, the present invention will be explained in detail with reference to the drawings.

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2a shows the arrangement of output data when no fixed pattern occurs, and Fig. 2b shows the arrangement of output data when a fixed pattern occurs. FIG. 3 is a diagram showing an arrangement configuration of output data.

In FIG. 1, writing and reading operations of data to and from a memory circuit 1 that stores data for N frames are performed by a write control circuit 2 and a read control circuit 3. In the pattern detection circuit 4, N
A pattern of consecutive logic "0" bits of P (P is a positive integer) included in the input data is detected in units of frames. The inhibition pulse generation circuit 5 is the pattern detection circuit 4
The output signal of the pattern detection circuit 4 is held.
The clock generated in the clock generation circuit 10 is inhibited by the inhibit gate 12, which is applied to the write control circuit 2 and drives the read control circuit 3 for N frames at a predetermined position in one frame after N frame time. It is used to inhibit the input data acquisition clock by the inhibit gate circuit 11 and to control the selection circuit 7 which selects the memory output data and logic "1" pattern. The display information generating circuit 8 is controlled by the output of the pattern detecting circuit 4, and generates display information in order to inform the receiving side whether or not an interruption of the logic "1" redundant bit has been performed. The multiplexing circuit 9 receives the output signal of the selection circuit 7,
The information bits which are the output signals of the information bit generation circuit 8 are multiplexed. Terminal 13 is an input terminal for taking in input data, terminal 14 is an output data terminal, and terminal 15 is a terminal for outputting a clock for taking in input data to the outside.

Next, details of the operation of the present invention will be explained. Digital data applied to input terminal 13 is applied to pattern detection circuit 4 and storage circuit 1. The pattern detection circuit 4 does not generate a signal for operating the inhibition pulse generation circuit 5 when P bits of consecutive logic "0"s are not detected in the input data. Therefore, the inhibition pulse generation circuit 5 does not generate inhibition pulses. After the data given to the memory circuit 1 is held for N frame time, it is sent to the multiplexing circuit 9 via the selection circuit 7.
sent to. This multiplexing circuit 9 is given display information consisting of a display bit generated by the display information generating circuit 8 indicating that no interrupt will be performed and an error correction bit generated based on the display bit. Therefore, in the multiplexing circuit 9, the input data string from the selection circuit 7 and the display information are multiplexed and sent to the output terminal 14. The output data arrangement in this case is shown in FIG. 2a. Here, the reference symbol F is generally called a frame synchronization signal and is used on the receiving side to detect the start position of each frame. Reference numeral X is a time slot for inserting an information bit indicating the presence or absence of a redundant bit interrupt operation. Reference numbers 1 to n (n is a positive integer)
is a number to distinguish data.

Next, the operation will be described in the case where the data applied to the input terminal 13 in FIG. 1 is sent to the pattern detection circuit 4, and P bits of consecutive logic "0" are detected here. When the data applied to the input terminal 13 includes a logical "0" pattern of consecutive P bits even once during a predetermined number of N frames, the pattern detection circuit 4 outputs a signal to drive the inhibition pulse generation circuit 5. Output. At the same time as this output, the display information generating circuit 8 is activated and display information indicating that the redundant bit interrupt operation has been performed is generated.

This display information indicates, in i bits (i<N), how many interrupts have been made to the input data bit string of N frames given from the input terminal 13. Specifically, for N frames of input data, display information is allocated at a rate of 1 bit for each frame, so this display information is formed of N bits, and based on the i-bit interrupt display bit, N -i bits of error detection and correction bits are created, resulting in N bits of display information. For example, when there are 3 redundant bits in N frames due to 3 interrupts, i bit of the N bits indicates that there are 3 redundant bits. For example, if i=3, it will be "011".

In order to insert the redundant bits shown in the shaded area in FIG. 2b from the first frame of N frames, it is first necessary to provide a time slot. For this purpose, the inhibit pulse generating circuit 5 applies a pulse to the inhibit gate 12 to inhibit the memory read circuit driving clock. As a result, the clock that takes in the input data is inhibited by the inhibit gate 11 in order to prevent input data from being dropped while the memory read operation is stopped. Furthermore, in order to insert a logic "1" pattern into the hatched area in FIG. Controls circuit 7. The output of the selection circuit 7 is sent to the multiplexing circuit 9. The multiplexing circuit 9 inserts the display information into a predetermined position of the output from the selection circuit 7. In this case, the multiplexing circuit 9 can perform multiplexing such that each bit of the display information is divided into one bit for each frame and allocated to positions X in FIGS. 2a and 2b.

Information multiplexed by this multiplexing circuit 9 is sent to an output terminal 14.

In the present invention, when performing a redundant bit interrupt to suppress a fixed pattern included in input data, it is possible to stop input data capture to prevent input data from being dropped, and to check whether or not a redundant bit interrupt is to be performed. At the same time as a signal in which the information has been subjected to error correction encoding is added to the output data, a redundant bit interrupt is performed on the receiving side by detecting the position of the display information and decoding only the display information in an error correction circuit. When there is a redundant bit, the position of the redundant bit can be easily found.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG.
The figure is a data arrangement configuration diagram for explaining the operation of FIG. 1. 1 and 2, 1...memory circuit, 2...write control circuit, 3...read control circuit, 4...pattern detection circuit, 5...inhibition pulse generation circuit, 6...pattern generation circuit , 7... selection circuit, 8... display information generation circuit with error correction encoding,
9... Multiplexing circuit, 10... Clock generation circuit,
11, 12...Inhibition gate circuit, 13...Input terminal, 14...Output terminal, 15...Clock output terminal.

Claims (1)

[Claims] 1 1 having n (n is a positive integer) bit data
an input means for receiving a digital data string having N frames (N is a positive integer); and an input means for receiving a digital data string having N frames (N is a positive integer); a detection means for detecting the fixed pattern; an interrupt means for forcibly inserting a redundant bit into a predetermined position of each frame in the N frames when the fixed pattern is detected by the detection means; prohibition means for prohibiting the input data string from being taken in for the time required for the redundant bit interruption; and
display information generating means for generating an interrupt indication bit indicating whether or not an interrupt has occurred in a frame and generating an error correction bit for the interrupt indication bit; 1. A fixed pattern suppression method, comprising: multiplexing means for multiplexing an input data string given as an interrupt bit or an input data string given as an interrupt bit by the interrupt means.