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JPS6236460B2 - - Google Patents
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JPS6236460B2 - - Google Patents

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Publication number
JPS6236460B2
JPS6236460B2 JP2332581A JP2332581A JPS6236460B2 JP S6236460 B2 JPS6236460 B2 JP S6236460B2 JP 2332581 A JP2332581 A JP 2332581A JP 2332581 A JP2332581 A JP 2332581A JP S6236460 B2 JPS6236460 B2 JP S6236460B2
Authority
JP
Japan
Prior art keywords
circuit
chopper
signal
circuits
main
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2332581A
Other languages
Japanese (ja)
Other versions
JPS57138865A (en
Inventor
Tooru Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2332581A priority Critical patent/JPS57138865A/en
Publication of JPS57138865A publication Critical patent/JPS57138865A/en
Publication of JPS6236460B2 publication Critical patent/JPS6236460B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of DC power input into DC power output
    • H02M3/02Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Description

【発明の詳細な説明】 この発明は、高信頼度が要求されるチヨツパ回
路並列運転において、数相のチヨツパ回路が故障
した時に、あたかも、故障前と同じ働きをする様
考慮した多相並列チヨツパの制御回路に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention is a multi-phase parallel chopper circuit that is designed to operate in the same manner as before the failure when a multi-phase chopper circuit fails in parallel operation of chopper circuits that require high reliability. The present invention relates to a control circuit.

本発明は、一般の多相並列チヨツパに適用でき
るが、説明の便宜上、2相チヨツパについて述べ
ることにする。
Although the present invention can be applied to a general polyphase parallel chopper, for convenience of explanation, a two-phase chopper will be described.

従来、この種の装置として、第1図に示すもの
があつた。図において1は入力電源直流電圧プラ
ス側、2は入力電源直流電圧基準側、3a,3b
はヒユーズ、4は主要チヨツパ主回路、5は補用
チヨツパ主回路、6はチヨツピング動作異常検出
器、7は短絡サイリスタ、8は短絡電流抑制抵
抗、9は制御回路、10は負荷である。
Conventionally, there has been a device of this type as shown in FIG. In the figure, 1 is the input power supply DC voltage positive side, 2 is the input power supply DC voltage reference side, 3a, 3b
4 is a fuse, 4 is a main chopper main circuit, 5 is an auxiliary chopper main circuit, 6 is a chopping operation abnormality detector, 7 is a short circuit thyristor, 8 is a short circuit current suppressing resistor, 9 is a control circuit, and 10 is a load.

次に動作について説明する。従来の回路におい
て正常運転とはヒユーズ3a、主要チヨツパ主回
路4、チヨツピング異常検出器6、負荷10を結
ぶループで回路が形成されている。この時補用チ
ヨツパ主回路5は動作していない。
Next, the operation will be explained. In the conventional circuit, normal operation is a circuit formed by a loop connecting the fuse 3a, the main chopper main circuit 4, the chopping abnormality detector 6, and the load 10. At this time, the auxiliary chopper main circuit 5 is not operating.

今、何らかの原因で主要チヨツパ主回路4が、
消弧失敗をして故障したとすると、チヨツピング
異常検出器6は制御回路9へ異常発生を伝達す
る。制御回路9はただちに短絡サイリスタ7のゲ
ートに点弧信号を送り短絡電流抑制抵抗8を介し
て短絡電流を流す。この短絡電流によりヒユーズ
3aが切れる、これにより主要チヨツパ主回路4
は分離される、その後制御回路9より補用チヨツ
パ主回路5のゲートに信号を送りヒユーズ3b補
用チヨツパ主回路5チヨツピング異常検出器6負
荷10を結ぶループで回路を形成する、次に主要
チヨツパ主回路4が点弧失敗して故障した場合
は、動作としては上記消弧失敗のときとほぼ同じ
であるがただ短絡サイリスタ7のゲートに信号を
送つても点弧失敗故にヒユーズ3aが切れない点
が異なるのみである。
Now, for some reason, the main chopper main circuit 4 is
If arc extinguishing fails and a failure occurs, the chopping abnormality detector 6 transmits the occurrence of the abnormality to the control circuit 9. The control circuit 9 immediately sends an ignition signal to the gate of the short circuit thyristor 7 to cause a short circuit current to flow through the short circuit current suppressing resistor 8. This short circuit current blows the fuse 3a, which causes the main chopper main circuit 4
After that, a signal is sent from the control circuit 9 to the gate of the auxiliary chopper main circuit 5, and a circuit is formed with a loop connecting the fuse 3b, the auxiliary chopper main circuit 5, the chopping abnormality detector 6, the load 10, and then the main chopper If the main circuit 4 fails due to ignition failure, the operation is almost the same as when the extinguishing failure occurs, but even if a signal is sent to the gate of the short circuit thyristor 7, the fuse 3a will not blow due to the ignition failure. The only difference is in one point.

従来の多相チヨツパ装置は以上のように構成さ
れているので、正常状態においては補用チヨツパ
主回路5は全く働いておらず主要チヨツパ主回路
4の異常時のみ駆動させられるため異常時駆動出
来るか否か信頼性が低かつた。又制御回路9にお
いて主要チヨツパ主回路4の故障(消弧失敗)か
ら充分余裕を見て補用チヨツパ主回路5のゲート
を生かす必要があつた、さもないとヒユーズ3a
主要チヨツパ主回路4、チヨツピング異常検出器
6、短絡サイリスタ7、短絡電流抑制抵抗8を介
して流れる短絡電流でヒユーズ3aが切れる以前
に補用チヨツパ主回路5のゲートに信号が入れば
補用回路用ヒユーズ3bも切れてしまうのであ
る。又点弧失敗時主要チヨツパ主回路4のケシト
信号を与えなくするため制御回路9が複雑である
などの欠点があつた。
Since the conventional multi-phase chopper device is constructed as described above, the auxiliary chopper main circuit 5 does not work at all in the normal state and is driven only when the main chopper main circuit 4 is abnormal, so that it can be activated in the event of an abnormality. The reliability was low. In addition, in the control circuit 9, it was necessary to take advantage of the gate of the auxiliary chopper main circuit 5 with sufficient margin in case of a failure (failure to extinguish the arc) in the main chopper main circuit 4, otherwise the fuse 3a would fail.
If a signal enters the gate of the auxiliary chopper main circuit 5 before the fuse 3a is blown by the short-circuit current flowing through the main chopper main circuit 4, the chopping abnormality detector 6, the short-circuit thyristor 7, and the short-circuit current suppression resistor 8, the auxiliary chopper main circuit 5 is activated. The fuse 3b will also be blown. Another disadvantage is that the control circuit 9 is complicated in order to prevent the output signal from the main chopper main circuit 4 from being applied when ignition fails.

この発明は上記のような従来のものの欠点を除
去するためになされたもので制御回路を、一新す
ることにより主回路の2つのチヨツパ主回路を常
に駆動状態とし故障時同時に複数のチヨツパ主回
路を駆動しても問題が出無い様にし、切替え時間
の短縮をはかり又どちらかのチヨツパ主回路が故
障(消弧失敗、点弧失敗)しても悪い主回路を切
り離す様にし制御回路の簡単化が出来るチヨツパ
装置を提供することを目的としている。
This invention was made to eliminate the drawbacks of the conventional ones as described above, and by completely updating the control circuit, the two chopper main circuits of the main circuit are always in a driving state, and in the event of a failure, multiple chopper main circuits can be activated at the same time. The control circuit is simplified so that no problems occur even when the main circuit is driven, and the switching time is shortened.Also, even if either of the main circuits of the chopper fails (failed to extinguish or fail to ignite), the faulty main circuit is disconnected. The purpose is to provide a chopper device that can perform

以下、この発明の一実施例を図について説明す
る第2図において14,15の構成は第1図のチ
ヨツパ主回路4,5と同等であるが14は第1チ
ヨツパ主回路、15は第2チヨツパ主回路と称
す。11aは第1チヨツパNFB、11bは第2
チヨツパNFB、6aは第1チヨツパチヨツピン
グ異常検出器、6bは第2チヨツパチヨツピング
異常検出器、7aは第1チヨツパ短絡サイリス
タ、8aは同じく短絡電流抑制抵抗、7bは第2
チヨツパ短絡サイリスタ、8bは同じく短絡電流
抑制抵抗、12は制御回路、13a,13bの突
き合わせダイオード、16は電流検出器である。
第3図において18aは第1チヨツパチヨツピン
グ異常検出回路、18bは第2チヨツパチヨツピ
ング異常検出回路、19aは第1チヨツパ短絡サ
イリスタ、7aはゲート信号発生回路、19bは
第2チヨツパ短絡サイリスタ7bのゲート信号発
生回路、20は発振器、21,22は積分機能+
コンパレータ機能をもつ回路、23は切替回路、
24はコンパレータ回路、25は第1チヨツパ点
弧パルス発生回路、26は微分回路、27は第1
チヨツパ消弧パルス発生回路、28は第2チヨツ
パ点弧パルス発生回路、29は第2チヨツパ消弧
パルス発生回路、30はローレベル加え算+切替
回路、31は第1、第2チヨツパ故障時の点弧パ
ルス発生回路、32は第1、第2チヨツパ故障時
の消弧パルス発生回路、34は電流基準回路、3
5は演算器である。第4図において36は発振器
20から回路21への信号、37は発振器20か
ら回路22への信号、38は回路21の出力、3
9は回路22の出力、40は第1チヨツパ点弧パ
ルス発生器25の入力、41は第2チヨツパ点弧
パルス発生器28の入力、42は第1チヨツパ消
弧パルス発生器27の入力、43は第2チヨツパ
消弧パルス発生器29の入力、44はローレベル
加え算+切替回路30の出力、45は第1、第2
チヨツパ故障中の点弧パルス発生回路31の入
力、46は第1、第2チヨツパ故障中の消弧パル
ス発生回路32の入力、47は演算回路35の出
力で第2図について動作説明を行なうが、制御回
路12の一例を第3図に示し、その中の信号の一
例を第4図に示している。
Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. In FIG. 2, the configurations 14 and 15 are the same as the chopper main circuits 4 and 5 in FIG. 1, but 14 is the first chopper main circuit, and 15 is the second chopper main circuit. It is called Chiyotsupa main circuit. 11a is the first chiyotsupa NFB, 11b is the second
Chopper NFB, 6a is the first chopply hopping abnormality detector, 6b is the second chopply hopping abnormality detector, 7a is the first chopply short-circuit thyristor, 8a is also the short-circuit current suppression resistor, and 7b is the second chopply hopping abnormality detector.
8b is a short-circuit current suppressing resistor, 12 is a control circuit, 13a and 13b are butt diodes, and 16 is a current detector.
In FIG. 3, 18a is a first chopper hopping abnormality detection circuit, 18b is a second chopper hopping abnormality detection circuit, 19a is a first chopper short-circuit thyristor, 7a is a gate signal generation circuit, and 19b is a second chopper hopping abnormality detection circuit. A gate signal generation circuit for the short-circuit thyristor 7b, 20 is an oscillator, 21 and 22 are integral functions +
A circuit with a comparator function, 23 is a switching circuit,
24 is a comparator circuit, 25 is a first chopper firing pulse generation circuit, 26 is a differentiation circuit, and 27 is a first
28 is a second chopper ignition pulse generation circuit, 29 is a second chopper quenching pulse generation circuit, 30 is a low level addition + switching circuit, 31 is a circuit in case of failure of the first and second chopper An ignition pulse generation circuit, 32 an extinguishing pulse generation circuit when the first and second choppers fail, 34 a current reference circuit, 3
5 is a computing unit. In FIG. 4, 36 is a signal from the oscillator 20 to the circuit 21, 37 is a signal from the oscillator 20 to the circuit 22, 38 is the output of the circuit 21, and 3
9 is the output of the circuit 22, 40 is the input of the first chopper firing pulse generator 25, 41 is the input of the second chopper firing pulse generator 28, 42 is the input of the first chopper firing pulse generator 27, 43 is the input of the second chopper arc extinguishing pulse generator 29, 44 is the output of the low level addition + switching circuit 30, and 45 is the first and second
46 is the input of the ignition pulse generation circuit 31 when the chopper is out of order, 46 is the input of the extinguishing pulse generation circuit 32 when the first and second choppers are out of order, and 47 is the output of the arithmetic circuit 35.The operation will be explained with reference to FIG. , an example of the control circuit 12 is shown in FIG. 3, and an example of the signals therein is shown in FIG.

第2図〜第4図を使つて動作を説明する、第2
図において、正常状態で、第1チヨツパ主回路1
4と第2チヨツパ主回路15は交互に点弧、消弧
をくり返している。第3図、第4図を使つてこれ
を説明する。第3図において、発振器20から、
積分コンパレータ回路21,22、へ位相の180
゜ずれた第4図の波形36,37で示す信号を入
力する。その結果積分コンパレータ回路21,2
2の出力は、それぞれ第4図の波形38,39と
なる、正常状態においては、第3図の切替回路2
3のゲートを開き、ローレベル加え算+切替回路
30のゲートを閉じておく。従つて、電流フイー
ドバツク16と、電流基準34とを突き合せて、
演算する演算器35、を通しての基準、第4図の
波形47と38,39信号との突き合せを、コン
パレータ24で行ない、第1チヨツパ点弧パルス
発生回路25の点弧パルス信号、第4図の波形4
0、第2チヨツパ点弧パルス発生回路28の点弧
パルス信号、第4図の波形41となり同時に消弧
パルス発生回路27,29へも微分回路26を通
して第4図のそれぞれ波形42,43の信号を加
える。
The second part explains the operation using Figures 2 to 4.
In the figure, in a normal state, the first chopper main circuit 1
4 and the second chopper main circuit 15 are alternately turned on and off. This will be explained using FIGS. 3 and 4. In FIG. 3, from the oscillator 20,
Integral comparator circuit 21, 22, phase 180
Signals shown as waveforms 36 and 37 in FIG. 4 shifted by .degree. are input. As a result, the integral comparator circuit 21,2
The outputs of switching circuit 2 have waveforms 38 and 39 in FIG. 4, respectively.In a normal state, the outputs of switching circuit 2 in FIG.
3 is opened, and the gate of the low level addition + switching circuit 30 is closed. Therefore, by comparing the current feedback 16 and the current reference 34,
The comparator 24 compares the reference waveform 47 and the signals 38 and 39 in FIG. Waveform 4
0, the ignition pulse signal of the second chopper ignition pulse generation circuit 28 becomes waveform 41 in FIG. 4, and at the same time, the signals of waveforms 42 and 43 in FIG. Add.

従つて、正常状態においては第4図の40と4
1、また42と43の波形は位相が180゜ずれた
信号になつており、これにより第2図の主回路は
駆動されるため、第1、第2チヨツパ主回路1
4,15は交互に点弧、消弧をくり返えすことに
なる。
Therefore, under normal conditions, 40 and 4 in FIG.
1, and the waveforms 42 and 43 are signals with a phase shift of 180 degrees, and this drives the main circuit in Fig. 2, so the first and second chopper main circuits 1
4 and 15 will alternately repeat firing and extinguishing.

今、何らかの原因で例えば、第1チヨツパ主回
路14が故障したと仮定すると、チヨツピング異
常検出器6aが異常を検出し、第3図のチヨツピ
ング異常検出回路18aが作動し、この出力の1
つが切替回路23のゲートを閉め、ローレベル加
算器+切替回路30のゲートを開くと同時に短絡
サイリスタ7aのゲート信号発生回路19aへ信
号を送る。これにより、短絡サイリスタ7aが導
通し、短絡電流によりNFB11aがトリツプす
る、一方、制御回路12は切替回路23がゲート
を閉じ、ローレベル加算器+切替回路30におい
て第4図の波形38,39のローレベル加え算が
行なわれ、30の出力には第4図の波形44が出
てくる。以下は正常状態と同様である、第4図の
波形47と44が24で比較される、この状態を
波形45に示す。又微分回路26を通した第4図
の波形46の信号を、第1、第2チヨツパ主回路
の消弧パルスとして同時に与える。
Now, assuming that the first chopper main circuit 14 has failed for some reason, the chopping abnormality detector 6a detects the abnormality, the chopping abnormality detection circuit 18a shown in FIG.
closes the gate of the switching circuit 23 and opens the gate of the low-level adder+switching circuit 30, and at the same time sends a signal to the gate signal generation circuit 19a of the short-circuit thyristor 7a. As a result, the short-circuit thyristor 7a conducts, and the NFB 11a trips due to the short-circuit current. On the other hand, the switching circuit 23 of the control circuit 12 closes the gate, and the low-level adder + switching circuit 30 generates the waveforms 38 and 39 in FIG. Low level addition is performed, and a waveform 44 in FIG. 4 appears at the output of 30. The following is similar to the normal condition, waveforms 47 and 44 of FIG. 4 are compared at 24, and this condition is shown in waveform 45. Further, a signal having a waveform 46 in FIG. 4 which has passed through the differentiating circuit 26 is simultaneously applied as an extinction pulse to the first and second chopper main circuits.

主回路は、点弧失敗であろうと、消弧失敗であ
ろうと、NFB11をトリツプさせるので、故障
主回路は切り離されるため、ゲートに信号を与え
られても、不具合いは生じない。
The main circuit trips the NFB 11 regardless of whether it fails to start or extinguish, so the faulty main circuit is disconnected, so even if a signal is given to the gate, no problem will occur.

又第2図のダイオード13によりNFB11の
トリツプ動作中、制御回路が健全なチヨツパ主回
路のゲートに信号を送つても、2次故障は誘発さ
れず、正常状態の2倍の周波数で電力を出力し、
負荷にとつては、正常状態の時も異常状態のとき
も、同じ周波数で電力を供給されていることにな
る。
Furthermore, even if the control circuit sends a signal to the gate of the healthy chopper main circuit during the trip operation of the NFB 11 by the diode 13 in Fig. 2, a secondary failure will not be induced and power will be output at twice the frequency of the normal state. death,
This means that power is supplied to the load at the same frequency both in normal and abnormal states.

尚、上記実施例では、2相並列チヨツパ主回路
で述べたが、一般に多相並列チヨツパ主回路に適
応される。又、主回路切り離しをNFBで述べた
が、ヒユーズ等高速引きはずし装置を用いても良
あ。
In the above embodiment, a two-phase parallel chopper main circuit is described, but the present invention is generally applied to a multi-phase parallel chopper main circuit. Also, although the main circuit is disconnected using NFB, it is also possible to use a high-speed tripping device such as a fuse.

以上のように、この発明によれば、多相のチヨ
ツパ主回路が正常状態においても駆動しているの
で、万一の場合、トラブルの発生した相を残りの
何相かのチヨツパ主回路で賄え、信頼性が高く、
また故障検出、切替等を電気信号で取り扱うた
め、切替時間が短縮できる。また故障後、異常主
回路はNFB等により完全に切り離してしまうた
め、故障チヨツパ主回路のサイリスタゲートに信
号が入つても、差し支えなく、制御回路も簡単化
される効果がある。
As described above, according to the present invention, the multi-phase chopper main circuit is driven even in the normal state, so in the unlikely event that a phase in which a problem occurs can be covered by the remaining phase chopper main circuits. Yes, it is highly reliable.
Furthermore, since failure detection, switching, etc. are handled using electrical signals, switching time can be shortened. Furthermore, after a failure, the abnormal main circuit is completely disconnected by NFB or the like, so even if a signal enters the thyristor gate of the failed chopper main circuit, there is no problem, and the control circuit is also simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の2相チヨツパ装置を示す回路
図、第2図はこの発明の一実施例を示す回路図、
第3図はこの発明の一実施例による制御回路の詳
細を示すブロツク図、第4図は第3図に示すブロ
ツクの各部の波形を示す波形図である。 4…主要チヨツパ主回路、5…補用チヨツパ主
回路、6…チヨツピング異常検出器、7…短絡サ
イリスタ、8…短絡電流抑制抵抗、9…制御回
路、10…負荷、12…本発明制御回路、13…
ダイオード、14…第1チヨツパ主回路、15…
第2チヨツパ主回路、16…電流検出器、18…
チヨツピング異常検出回路、19…短絡サイリス
タゲートパルス発生回路、20…発振器、21,
22…積分+コンパレータ回路、23…切替回
路、24…コンパレータ、25…第1チヨツパ点
弧パルス、26…微分回路、27…第1チヨツパ
消弧パルス回路、28…第2チヨツパ点弧パル
ス、29…第2チヨツパ消弧パルス回路、30…
ローレベル加え算器+切替回路、31…故障時第
1、第2チヨツパ主回路点弧パルス回路、32…
故障時第1、第2チヨツパ主回路消弧パルス回
路、34…電流基準、35…演算回路。なお、各
図中、同一符号は、同一あるいは相当部分を示す
ものとする。
FIG. 1 is a circuit diagram showing a conventional two-phase chopper device, FIG. 2 is a circuit diagram showing an embodiment of the present invention,
FIG. 3 is a block diagram showing details of a control circuit according to an embodiment of the present invention, and FIG. 4 is a waveform diagram showing waveforms of various parts of the block shown in FIG. 4... Main chopper main circuit, 5... Auxiliary chopper main circuit, 6... Chopping abnormality detector, 7... Short circuit thyristor, 8... Short circuit current suppression resistor, 9... Control circuit, 10... Load, 12... Control circuit of the present invention, 13...
Diode, 14...First chopper main circuit, 15...
2nd chopper main circuit, 16... current detector, 18...
Chopping abnormality detection circuit, 19... Short circuit thyristor gate pulse generation circuit, 20... Oscillator, 21,
22... Integral + comparator circuit, 23... Switching circuit, 24... Comparator, 25... First chopper firing pulse, 26... Differential circuit, 27... First chopper extinguishing pulse circuit, 28... Second chopper firing pulse, 29 ...Second chopper arc extinguishing pulse circuit, 30...
Low level adder + switching circuit, 31... First and second chopper main circuit ignition pulse circuit in case of failure, 32...
1st and 2nd chopper main circuit arc extinguishing pulse circuit at the time of failure, 34...Current reference, 35...Arithmetic circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 多相並列チヨツパ主回路を制御するものにお
いて、各チヨツパ主回路と入力電源との間にそれ
ぞれ挿入され、通過電流の増大により動作する複
数の引外し装置、この引外し装置と上記各チヨツ
パ主回路との間にそれぞれ挿入され、入力信号を
受けて対応する上記引外し装置に短絡電流を流す
複数の第1の回路、それぞれ所定角位相のずれた
信号を発生する複数の第2の回路、この複数の第
2の回路の発生信号により対応するチヨツパ主回
路の点弧信号、消弧信号をそれぞれ導出し、発生
する複数の第3の回路、上記複数の第2の回路の
発生する信号を加え合した信号を発生する第4の
回路、この第4の回路の出力により各チヨツパ主
回路の点弧信号、消弧信号を導出する第5の回
路、任意のチヨツパ主回路の異常を検出する第6
の回路、この第6の回路の動作により上記任意の
チヨツパ主回路に対応する第1の回路に入力信号
を供給する第7の回路、上記第6の回路の動作に
より、上記第3の回路の動作を断ち、上記第5の
回路の発生する点弧信号、消弧信号を各チヨツパ
主回路へ供給する第8の回路を備えたことを特徴
とする多相並列チヨツパ制御装置。
1. In a device that controls a multi-phase parallel chopper main circuit, a plurality of tripping devices are inserted between each chopper main circuit and the input power source and are activated by an increase in passing current, and this tripping device and each of the chopper main circuits mentioned above are connected to each other. a plurality of first circuits each inserted between the circuit and the circuit, each receiving an input signal and causing a short-circuit current to flow to the corresponding tripping device; a plurality of second circuits each generating a signal having a phase shift by a predetermined angle; The firing signals and extinction signals of the corresponding chopper main circuits are derived from the signals generated by the plurality of second circuits, and the signals generated by the plurality of third circuits and the plurality of second circuits are derived. A fourth circuit that generates the combined signal; a fifth circuit that derives the firing signal and extinguishing signal for each chopper main circuit from the output of this fourth circuit; and detects an abnormality in any chopper main circuit. 6th
a seventh circuit that supplies an input signal to the first circuit corresponding to the arbitrary chopper main circuit by the operation of this sixth circuit; A multiphase parallel chopper control device comprising an eighth circuit that cuts off the operation and supplies the firing signal and extinction signal generated by the fifth circuit to each chopper main circuit.
JP2332581A 1981-02-18 1981-02-18 Polyphase parallel chopper controlling device Granted JPS57138865A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2332581A JPS57138865A (en) 1981-02-18 1981-02-18 Polyphase parallel chopper controlling device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2332581A JPS57138865A (en) 1981-02-18 1981-02-18 Polyphase parallel chopper controlling device

Publications (2)

Publication Number Publication Date
JPS57138865A JPS57138865A (en) 1982-08-27
JPS6236460B2 true JPS6236460B2 (en) 1987-08-07

Family

ID=12107426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2332581A Granted JPS57138865A (en) 1981-02-18 1981-02-18 Polyphase parallel chopper controlling device

Country Status (1)

Country Link
JP (1) JPS57138865A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6169368A (en) * 1984-09-12 1986-04-09 Toyota Motor Corp Polyphase chopper
DE102024121436A1 (en) * 2024-07-26 2026-01-29 Embex Gmbh Converter device

Also Published As

Publication number Publication date
JPS57138865A (en) 1982-08-27

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