JPS6236572B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital servo device suitable for use in controlling the rotation system of a video tape recorder.

In a helical scan type video tape recorder, it is necessary to maintain a predetermined relationship between the running speed of the magnetic tape and the rotational speed of the rotary head to obtain stable scanning of the recording track. For this purpose, a capstan servo device related to the tape speed and a rotary head servo device related to the rotational speed of the rotary head are provided. The capstan servo device controls the rotational frequency and rotational phase of the capstan motor to a target value. The rotary head servo device also controls the rotational frequency and rotational phase of the rotary head motor to a target value.

As this type of servo device, there is a digital servo device that uses digital signals to detect the rotational frequency and phase of the motor and converts the detected digital signals into analog signals to control the motor. It is considered.

On the other hand, since video tape recorders are required to have functions such as slow playback, double speed playback, double speed recording, and low speed recording, the servo device must also be configured to be able to switch target values. However, changing the frequency of the reference clock pulse used in the servo device in order to switch the target value requires a new crystal oscillator or frequency divider, resulting in an increase in parts and cost.

The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide a digital servo device that can switch a target value for a device to be controlled to a plurality of values using simple means.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a digital servo device, which is used, for example, in a rotating head servo system of a video tape recorder. In Fig. 1, 11 is a stable clock pulse input terminal obtained from a crystal oscillator, etc., 12 is an input terminal to which a rotation detection pulse (so-called tank pulse) obtained from the rotation detection circuit of the rotating head is applied, and 13 is a vertical synchronization This is an input terminal to which a pulse synchronized with the signal or a reference pulse such as a control pulse is applied.

The clock pulse input terminal 11 is connected to a counter 14 which obtains a cyclic counting operation. The count contents of this counter 14 are applied to the input terminals of a first memory 15 and a third memory 20 having a latch function. The output end of the first memory 15 is
It is connected to the second memory 16 and also to one input terminal of the full subtractor 17 and one input terminal of the full subtractor 23 . Further, the second memory 16
The output terminal of is connected to the other input terminal of the full subtractor 17.

The input terminal 12 for the rotation detection pulse is connected to the first and second memories 15 and 16. When a pulse is applied to this input terminal 12, the first memory 15
latches the contents of counter 14, and second memory 16 latches the contents of first memory 15.

The output terminal of a full subtractor 17 that subtracts the contents of the second memory 16 and the first memory 15 is connected to one input terminal of a full subtractor 18. The data of constant A is set at the other input terminal of this full subtractor 18. This total subtractor 18
The output is analog-converted by a digital-to-analog converter 19 and output to an automatic frequency control (AFC) signal output terminal. Here, the first memory 1
When a subtraction process is performed between the contents of 5 and the contents of the second memory 16, the result of the calculation corresponds to the period or interval of the tack pulse converted into time (data). Here, if the calculation result is constant at a predetermined value, it means that the motor is rotating stably, but a constant A is introduced in the total subtractor 18. This is to set the output of the digital-to-analog converter 19 to the center value of the variable range so that when the calculation result matches the target value, the operation amount in the ± direction is approximately equal.

On the other hand, the output terminal of the third memory 20 is connected to the other input terminal of the full subtractor 23 via the control target value setting section 22. The output of this full subtractor 23 is
The signal is converted into analog by a digital-to-analog converter 24 and introduced into an automatic phase control (APC) signal output terminal.

Next, the control target value setting section 22 will be explained. It is composed of a target value setting circuit 25, a storage circuit 26, a selection circuit 27, a full adder 28, and the like.

In normal operation, the output of the third memory 20 is input to the full subtracter 23 through the selection circuit 27 and the full adder 28. In the full subtractor 23, a subtracted output corresponding to the time difference, that is, the phase difference, between the reference pulse (vertical synchronization pulse) and the motor rotation detection pulse is obtained. In this case, addition of the constant B is performed in the full adder 28, but when the numerical value indicating the phase difference matches the target value, the calculation output is changed within a variable range in order to make the manipulated variables in the ± direction approximately equal. This is to set it to the median value.

According to the above-described servo device, the digital-to-analog converter 19 provides the rotational frequency control output of the rotary head motor, and the digital-to-analog converter 24 provides the rotational phase control output.

By the way, when a video tape recorder is switched to a function such as high-speed playback, the tape enters high-speed forwarding or high-speed rewinding, so the relative speed between the tape and video head is different from that during recording, and the scanning frequency of the reproduced video signal is changed from the normal one. This makes it difficult to obtain a good image.

In such a case, a control target value setting section is used in the present invention. That is, this control target value control section 22 is configured as shown in FIG. The same parts as in FIG. 1 will be described with the same reference numerals. A read-only memory (ROM) is used as the storage circuit 26, and various constants B are stored in this. A read address can be specified for this storage circuit 26 via the decoder 30, and the read constant B is input to the full adder 28.

When specifying the address of the memory circuit 26,
Phase and speed correction terminal of target value setting circuit 25
A designated code signal is added from _t1 to _t3 and from _t4 to _t6 . Terminals _t1 to _t3 are used during playback by the video tape recorder, and terminals _t4 to _t6 are used during recording. Further, the terminal t ₇ is a recording/reproduction switching signal input terminal, and is connected to one input terminal of each of the AND circuits 32 , 34 , 36 , the decoder 30 , and the inverter 40 . Further, the other input terminals of the AND circuits 32, 34, and ₃₆ are connected to the terminals _t4 , _t5 , and t6, respectively. Next, the output terminal of the inverter 40 is commonly connected to one input terminal of each of the AND circuits 31, 33, and 35, and the terminals _t1 ,
t ₂ and t ₃ are connected. Next, the AND circuit 31,
The output terminal of 32 is connected to the first and second input terminals of an OR circuit 37, and the output terminal of this OR circuit 37 is connected to the decoder 30. Also, AND circuits 33, 3
The output terminal of 4 is connected to the first and second input terminals of an OR circuit 38, and the output terminal of this OR circuit 38 is connected to the decoder 30. Similarly, AND circuits 35 and 36
The output terminal of is connected to an OR circuit 39, and the output terminal of this OR circuit 39 is connected to a decoder 30.

Next, the selection circuit 27 will be explained. This selection circuit 27 selects either the output data of the third memory 20 or the output data of the full adder 28 according to the logic signal applied to the terminal _t7 . The switch section corresponding to each bit includes AND circuits 41 and 42, and OR circuit 45.
The configuration is similar to that of . In the illustrated example, a switch section including AND circuits 41 and 42 and an OR circuit 45, and a switch section including AND circuits 43 and 44 and an OR circuit 46 are representatively shown. The input end side of the inverter 40 is connected to one input end of each of the AND circuits 41 and 43, and the AND circuit 4
The inverter 4 is connected to one input terminal of each of the inverters 2 and 44.
The output end side of 0 is connected. Further, the other input terminals of the AND circuits 41 and 43 are connected to the corresponding output terminals of the full adder 28, and the other input terminals of the AND circuits 42 and 44 are connected to the third memory 20. Each corresponding output terminal is connected respectively.

The operation of the control target value setting section shown in FIG. 2 will be explained as follows. Now, when the video tape recorder is in the recording mode in normal operation, the terminal _t7 becomes 1. Therefore, AND circuits 32, 34, 3
6 becomes conductive. Furthermore, in the selection circuit 27, the AND circuits 42 and 44 are rendered conductive. In this state, the output data of the third memory circuit 20 and the ROM are sent to the full adder 28.
A constant B (the value of which can be switched by a code signal applied to terminals _t4 to _t6 ) is input from . In this case, selecting and switching the constant B corresponds to shifting the target value, that is, the center value of the speed variable range, and corrects the tape speed due to variations in capstan diameter, etc. In other words, selecting and switching the constant B can expand the phase correction range.

Next, during playback, since the terminal t ₇ becomes 0, the AND circuits 31, 33, and 35 become conductive, and in the selection circuit 27, the AND circuits 41, 4
3 becomes conductive.

In this case, the output C of the full adder 28 is C=C'+B (C' is the value when the output of the full adder 28 is inputted again via the switch section). 1 memory 15
The total subtracter 23 performs subtraction processing from the output of , and outputs the phase operation amount X. The arithmetic operation of the above circuit is performed at a predetermined cycle using, for example, a tack pulse. Here, when performing special reproduction, etc., a predetermined code signal is given to terminals t ₁ to _{t 3} and the value of constant B is switched, thereby setting a target value for phase correction. be done. Here, the constant B is the clock pulse within the period of the target rotation frequency of the motor to be controlled.
This is a value obtained by counting T ₀ and is obtained in advance.

As described above, according to the present invention, the control target value can be easily switched by simply switching the ROM address and selecting the constant B, without using a separate oscillator or frequency divider. be able to.

Now, in the above circuit, counter 14, memories 15, 16, 20, full subtracters 17, 18, 2
3. If the full adder 28 etc. have a 16-bit configuration and the clock pulse T ₀ =1 μsec, the counter 14
One cycle period Tm = 1 μsec x 2 ¹⁶ = 65536 μs =
It becomes 0.065536sec. Assuming that the rotational speed of the motor to be controlled is 25Hz, and four tuck pulses are obtained in one revolution, and the rotational frequency is controlled based on this, the tack period Tt = 1/100 = 0.01 sec.
becomes. This is the value of counter 14, which is 0.01sec
÷1 μse=10 ⁴ =10000, which becomes the target value.

Calculation for frequency control is performed by using a tack pulse to set the first memory = 12345 and the second memory = 01234.
Assuming that, the manipulated variable = 12345 - 01234 - {10000 - (median value of manipulated variable)} = 1111 + median value of manipulated variable, which is the manipulated variable that corresponds to the error.

Here, 10000-(median value of manipulated variables)=A (constant).

For the automatic phase control side, the calculation is similar to the above, and the phase operation amount is obtained. However, if only the frequency is desired to be constant, a constant of a preset value may be used as an element for calculating the manipulated variable instead of the reference pulse. For example, if the rotation of the motor is 25 rotations/second and the operation amount is calculated once per rotation, then B=40000=10000×4. Therefore, C=C'+40000 (mod2 ¹⁶ ).

Also, the value of memory 15 is...02345, 12345,
22345, 32345, 42345, 52345, 62345, 06809,
If the number sequence is 16809, 26809, ..., and one operation is performed out of four tuck pulses in one revolution, then from the total subtractor 23, 42345-40000=02345 16809-14464=02345 56809-54464=02345 Therefore, the manipulated variable target value is a constant value (when the motor is rotating at the target value).

By selecting and switching the constant B (40,000 in the above example), the rotational speed of the motor can be easily set.

In the embodiments described above, a cyclic counter is used as the counter 14, so if the cycle of the tack pulse or the reference pulse is longer than the one cycle cycle of the counter 14, it will malfunction due to overflow. Therefore, it is necessary to set the period of both pulses in the normal operating state to be shorter than the cycle period of the counter 14. Note that when starting a motor, etc., the cycle of the tack pulse is long, which causes malfunctions, but in general, in servo circuits, the control mode is determined according to the operating state of the controlled object. It is divided into a range where linear control is performed in the operating state and a control range other than that, and in the latter, the control loop is cut off and a constant maximum or minimum amount of control signal is applied to quickly return to a steady operating state. It is extremely easy to apply such a well-known technique to the embodiment shown in FIG. 1, and thereby malfunctions in unsteady conditions can be prevented.

As described above, according to the present invention, it is possible to provide a digital servo device that can switch a plurality of target values for a device to be controlled by simple means. Therefore, there is no need for means that require extra circuitry, such as dividing the frequency of the reference pulse or separately providing a reference pulse source of a different frequency, as has been done in the past, and the circuit configuration is simplified.

Generally, when recording, the rotating head servo system of a home VTR measures the phase of the motor's rotation detection pulse using the vertical synchronization signal of the television signal to be recorded as a reference pulse, and controls it to maintain a constant phase relationship. During playback, the head motor is controlled to rotate at a constant speed. Therefore, it can be easily applied to VTRs for television systems with different vertical frequencies.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the main part of the invention. 14... Counter, 15, 16, 20... First, second, third memory, 17, 23... Full subtractor, 25... Target value setting circuit, 26... Memory circuit, 27... Selection Circuit, 28...Full adder.

Claims (1)

[Scope of Claims] 1. In a digital servo device that compares a rotation detection pulse indicating the rotational phase of a motor, which is a controlled object, with a reference signal and derives a control amount of the motor as a digital amount, a clock with a constant frequency is counted. a cyclic counter that sequentially stores the count value of the cyclic counter using the rotation detection pulse as a latch pulse; and a memory that uses the count value of the cyclic counter during a period equal to the period of the reference signal as a reference constant, and a full adder that adds the output at the timing of the rotation detection pulse and holds the result until the next process; and a full adder that subtracts the value latched in the memory and the output of the full adder to control the rotational phase of the motor. A digital servo device characterized in that it is equipped with a full adder that obtains an output for use.