JPS6236578B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address stop control method, and in particular, in a microprocessor, etc., invalid data is inserted into data at a specific address during a debugging test, and the data at that address is called. The present invention relates to an address stop control method that stops an instruction at a specific address by generating an error state when the instruction is stopped.

2. Description of the Related Art In data processing devices, particularly microprocessors, when performing test operations such as debugging, there are cases in which a program is stored in a memory and execution of the program is stopped at a certain address point in the program. To do this, in conventional devices of this type, the address to be stopped is generally set in an address stop register, and the instruction address read from memory by the processor and the address
A comparator compares the address with a desired address set in the stop register, and if the two match, the output from the comparator generates a clock stop state or the like to stop the system.

However, the prior art scheme described above requires an address stop register and a comparator. And this address stop
The register had to be large enough to hold address information for the number of bits that make up one address; for example, if the memory was 4K, it had to be a 12-bit register. Furthermore, since the comparator must compare the number of bits held in the stop register with the same number of bits of address information read from the storage device, it requires a fairly large amount of hardware. become. This means that, for example, when configuring a microprocessor using an LSI (Large-Scale Integrated Circuit), it is difficult to incorporate address stop registers and comparison circuits after determining the functional circuits assigned for various purposes. Become. At this time, if the address comparison function is to be ensured when there is not much room left in the remaining functional circuit portions, there is a risk that a delicate situation may arise as to whether or not it can be incorporated.

In order to solve the above problems, the present invention
Instead of using an address stop register with a large number of bits or a comparator to compare the address output from the address stop register and the address output from the processor, it is possible to detect a parity error at a specific address by using only one bit. It is an object of the present invention to provide an address stop control method that intentionally causes a specific address to occur, detects the existence of that specific address, and performs an address stop. For this purpose, in the address stop control method according to the present invention, an address setting means for reading the contents of the memory and an output of the memory are provided. an output holding means for temporarily holding the check bit, a bit inverting means for inverting the check bit written in the memory, and a selection for selecting whether or not to write the inverted bit inverted by the bit inverting means in the memory. The present invention is characterized in that means is provided to detect the presence of an error in the output information at a specific address by setting the inversion bit at the specific address, thereby performing an address stop.

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

The figure shows an example configuration for implementing the method of the present invention.

In the figure, 1 is a control memory in the microprocessor, 2 is a CS address register that sets the address in the control memory, 3 is a counter that increases the address of CS address register 2 by 1, and 4 is a readout from the control memory 1. Indicates a control register that temporarily sets the contents of the 5
is an inverter which inverts only the parity check bit R of a specific address among the information stored in the control register 4 to intentionally give an error state, and then returns it to the control memory 1 for storage. It is something that exists. 6 is a parity bit inspection device, and when a parity error is detected,
This is an error detection device that reports this and performs clock stop control. 7 and 8 are AND circuits, 9 is an OR circuit, and 10 is a mode setting latch. Normally, "1" is output to AND circuit 7 to turn it on, but in invalid mode When the signal "1" is applied, it outputs "1" to the AND circuit 8, turning it on.

The operation of the apparatus of the present invention configured as above will be explained.

During normal operation, latch 10 outputs "1" to AND circuit 7, turning AND circuit 7 on.
Therefore, when the control memory 1 is read based on the address set in the CS address register 2 and the output of the control memory 1 is set in the control register 4, a parity check is performed by the parity bit checking device 6. If the result is normal, control is performed based on the output set in the control register 4. At this time, parity bit P is directly set in control memory 1 via AND circuit 7 and OR circuit 9. Then, the address set in the CS address register 2 is incremented by 1 by the counter 3, the next control information is output from the control memory 1, and data processing by the processor is performed.

However, if it is desired to stop the operation of a program at a specific address for system testing, for example, during debugging, etc., the following control is performed.

First, an invalid mode signal "1" is applied to the latch 10. As a result, the latch 10 outputs "1" to the AND circuit 8, turning the AND circuit 8 on. Then, by appropriate means, enter the address of the program you want to stop.
Set to CS address register 2. Then write the data and parity inversion bit. That is, this parity bit P is inverted by an inverter 5 and set in a control memory via an AND circuit 8 and an OR circuit 9. In other words, the correct parity bit P, which was previously set, is intentionally inverted by the inverter 5 and the parity bit is set.

After making these preparations, run the test program. At this time, when the address of the program to be stopped is set in the CS address register 2, the contents of that address are output to the control register 4. At this time, since the parity bit of the specific address is inverted as described above, the parity bit checking device 6 detects that it is invalid, that is, in an error state. Then, the system is automatically stopped using the output from the inspection device 6. That is, one method is to stop the clock device or use its detection output as an interrupt signal to bring the system to a halt state or to a manual control state (HALT).

As described above, unlike the conventional address control stop method, the present invention intentionally creates an error state by inverting the parity bit, thereby making it possible to perform automatic stop control at a predetermined address. At this time, since it is sufficient to use an existing parity bit checking device, extremely effective address stop control can be performed without increasing the amount of hardware.

[Brief explanation of the drawing]

The figure shows the configuration of an embodiment of the present invention. In the figure, 1 is control memory, 2 is CS address register, 3 is +1 counter, 4 is control register,
5 is an inverter, 6 is a parity bit inspection device,
7 and 8 are AND circuits, 9 is an OR circuit, and 10 is a latch.

Claims (1)

[Claims] 1. In an address stop control method in which the address of an instruction is stopped at a specific address in the memory, an address setting means for reading the contents of the memory, an output holding means for temporarily holding the output of the memory, and a memory A bit inverting means for inverting the check bit written in the memory, and a selection means for selecting whether or not to write the inverted bit inverted by the bit inverting means in the memory, are provided, and the inverted bit is set at a specific address. An address stop control method characterized in that the existence of an error is detected in the output information at the specific address by detecting the presence of an error in the output information, and thereby an address stop is performed.