JPS6236600B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a phase-synchronized multi-pen recorder that records input signals by appropriately delaying input signals to correct mechanical misalignment between recording pens.

FIG. 1 is an explanatory diagram of the main part of a conventional phase synchronized multi-pen recorder. In FIG. 1, the analog input signal V ₁ of the first channel is led directly to a servo amplifier 7 ₁ via a preamplifier 1 ₁ .
The servo motor ₈₁ is driven by the output signal of the servo amplifier ₇₁ , and displaces the first recording pen _P1 shown in FIG. 2, which is connected to the rotating shaft of the motor. In this way, the input signal V ₁ of the first channel is transferred to the first recording pen P ₁
The image is recorded on the recording paper 21 by. The input signals V ₂ to _{V o} from the second channel onwards are each input to the preamplifier 1.
After passing through A/D converters ₂₂ to _2o , the signals are AD-converted by AD converters ₂₂ to _2o , and temporarily stored in a processor 4 via isolators ₃₂ to _3o . The processor 4 delays the input signal for each channel by a predetermined time, and then outputs it via the isolators ₅₂ to _5o . The signals of each channel outputted in this way are subjected to DA conversion by DA converters 6 ₂ to 6 _o , and then guided to servo amplifiers 7 ₂ to 7 o, as in the case of the first channel, to the servo amplifiers 7 2 to 7 _o .
The _o-th recording pens P ₂ to _{P o} are each driven. The delay time of each signal in this case is related to the deviations d ₂ , d ₃ , ... d _o from the first recording pen and the feeding speed v of the recording paper 21 shown in FIG. It has been selected so that it can be recorded.

In such a conventional phase synchronized multi-pen recorder, isolators ₃₂ to _3o and 52 _{to 5o} are required for data transfer to the processor 4, since high insulation is required between each channel.
Furthermore, a serial data transfer method is used to reduce the number of bits to be isolated, but this requires accurate timing control, which has the disadvantage of complicating the circuit.

Furthermore, since the control of each channel is managed by one processor, there is also a drawback that the processing time for conversion, calculation, etc. increases as the number of channels increases.

The present invention solves these drawbacks at once, and provides a phase-synchronized multi-pen recorder that has a simple configuration, has good insulation between channels, and has processing times such as conversion and calculation that are not affected by the number of channels. The purpose is to

Another object of the present invention is to ensure that conversion errors occurring in AD conversion and DA conversion of input signals are mutually canceled out when data is time-delayed to correct phase differences between channels. An object of the present invention is to provide a phase-synchronous multi-pen recorder.

The present invention will be explained in detail below using the drawings. FIG. 3 is a diagram showing the configuration of essential parts of an embodiment of a phase synchronized multi-pen recorder according to the present invention. In Figure 3, parts equivalent to those in Figure 1 are given the same symbols,
The explanation will be omitted. 31 ₂ to 31 _o are delay means, and 32 is a recording paper feeding mechanism.

The delay means 31 ₂ to 31 _o each have the same configuration. The following describes the delay means ₃₁₂ as an example. That is, the output of the preamplifiers 1 _{to 2} is AD converted by the AD conversion means 311, and the converted data is stored in RAM (random access memory) inside or outside the processor 312.
(not shown) is temporarily stored in the recording paper feed mechanism 32.
After an appropriate time delay based on the clock CLK from , the signal is sent to the DA conversion means 313 . The analog output signal of the DA conversion means 313 is guided to the servo amplifier ₇₂ .

FIG. 4 is a block diagram showing a specific example of the delay means ₃₁₂ . In the figure, 41 ₂ is an analog comparator, 42 ₂ is a processor using a 1-chip microprocessor, 43 ₂ is a DA converter, and 44
₂ is a sample hold circuit, and ₄₇₂ is an output amplifier. The analog input signal V ₂ passed through the preamplifier 1 ₂ is compared in magnitude with the output of the DA converter 43 ₂ by a comparator 41 ₂ . The processor 42 ₂ is a comparator 4
Based on the comparison results of 1 _{and 2} , the DA converter input is successively changed so that the output of the DA converter ₄₃₂ matches the input signal _V2 .
AD converts V ₂ and stores it in RAM. After a predetermined time delay in relation to the clock CLK of the recording paper feed mechanism 32, this stored data is unilaterally sent to the DA converter ₄₃₂ regardless of the output of the comparator ₄₁₂ .
The analog output of the DA converter ₄₃₂ is sampled and held in a sample and hold circuit ₄₄₂ , which is composed of a switch ₄₅₂ that turns on and off under the control of the processor 422, and _a capacitor ₄₆₂ .
The signal is continuously output via the output amplifier ₄₇₂ . According to this circuit configuration, since the DA converter ₄₃₂ is shared during AD conversion and DA conversion, errors in AD conversion and DA conversion can be canceled.

The recording paper feeding mechanism 32 sends out a clock CLK related to the recording paper feeding speed, and each clock CLK is connected to an isolator (not shown).
The signals are simultaneously applied to the delay means 31 ₂ to 31 _o via.

Next, the operation when the delay means having the configuration shown in FIG. 4 is used for each channel will be described below. Here, in order to simplify the explanation, for example, the operation of the circuit related to the second channel will be explained as a representative example. When the clock CLK is applied from the recording paper feed mechanism 32,
Processor ₄₂₂ drives switch ₄₅₂ to the OFF state. Subsequently, the analog input voltage _V2 applied via the preamplifier ₁₂ is AD converted using the above-mentioned successive approximation method, and the digital value is stored in the memory. From then on, every time the clock CLK is applied, the analog input voltage V ₂ is changed to AD in the same manner as described above.
Convert and store the value.

On the other hand, the processor ₄₂₂ sends out the data stored at a point in time that is the interval _d2 between the recording pens _P1 and _P2 , based on the number of pulses of the clock CLK. That is, in other words, the data stored is delayed by the time _td required for the moving distance _d2 of the recording paper and is sent out.
The delayed output data is converted into analog data by a DA converter ₄₃₂ , sampled and held by a sample hold circuit ₄₄₂ driven by the control of a processor ₄₂₂ , and sent to a servo amplifier ₇₂ via an output amplifier ₄₇₂ . be done. Operations similar to those described above are performed in parallel on the third channel and beyond.

Note that the above-mentioned delay time differs depending on each channel, and management of the delay time is performed individually by each processor.

In this way, the input signals of the channels from the second channel to the nth channel are delayed by the respective processors _42o by a time corresponding to the deviation of each recording pen from the first recording pen, and the delayed signals are By recording, the displacement of the recording pen can be corrected and the phase of the input signal can be synchronized and recorded.

Incidentally, such phase synchronization can be canceled when recording paper feeding is stopped, if necessary. However, in this case, it is necessary to configure the recording paper feed mechanism 32 to receive a paper feed start/stop signal (binary signal) to cancel the delay of stored data in the processor _42o .

As explained above, according to the phase-synchronized multi-pen recorder of the present invention, each channel after the second recording pen is provided with a delay means using an individual processor. Computation time such as delay time is not affected by an increase in the number of channels, and all channels can be recorded simultaneously with the processing time per channel. In addition, there is no need for data conversion such as serial/parallel conversion or parallel/serial conversion that was required with conventional recorders.
Therefore, the circuit configuration can also be simplified.
Furthermore, insulation between each channel is sufficient by only insulating the clock signal, and insulation can be achieved efficiently.

Furthermore, when the delay means shown in Figure 4 is used, AD conversion and DA conversion are performed using the same DA converter, so the error of the DA converter that occurs during each conversion is automatically canceled out. It has the effect of

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the main part of a conventional phase-synchronized multi-pen recorder, Fig. 2 is a diagram illustrating mutual misalignment of recording pens, and Fig. 3 shows an embodiment of a phase-synchronized multi-pen recorder according to the present invention. Main part configuration diagram shown,
FIG. 4 is a block diagram showing a specific example of the delay means shown in FIG. 3. 1 ₁ ~ 1 _o ... Preamplifier, 7 ₁ ~ 7 _o ... Servo amplifier, 8 ₁ ~ 8 _o ... Servo motor, 31 ₁
~31 _o ...delay means, 311...AD conversion means,
312,42 ₂ ...Processor, 313...DA
Conversion means, 32... Recording paper feeding mechanism, 41 ₂ ...
Analog comparator, 43 ₂ ...DA converter, 44 ₂
...sample hold circuit, 45 ₂ ...switch, 46 ₂ ...capacitor, 47 ₂ ...output amplifier.

Claims (1)

[Scope of Claims] 1. When simultaneously recording multi-channel analog input signals with a plurality of recording pens, each input signal from the second recording pen onwards is appropriately delayed in synchronization with the recording paper feed speed, and recording is performed. A phase-synchronized multi-pen recorder that can record by correcting pen misalignment is equipped with a clock generation means that generates a clock in relation to the recording paper feed speed, and a processor for each channel after the second recording pen. and a DA that converts the digital value output from this processor into an analog signal and outputs it.
a converter; a comparator that compares the output from the DA converter with the analog input signal; and a comparator connected to the output terminal of the DA converter and holding the output in response to a command signal from the processor. , and a sample hold circuit that outputs an analog signal as an input signal of a recording pen, each of the processors having means for generating various digital values, and a sample and hold circuit that outputs an analog signal as an input signal of a recording pen, and a sample and hold circuit that outputs a digital value corresponding to the analog input signal according to the output of the comparator. means for controlling the digital value generating means to obtain a value, means for sequentially storing the digital values obtained from the digital value generating means, and storing the digital values delayed by a predetermined time determined corresponding to the channel after storing. The present invention is characterized by comprising means for sequentially outputting digital values to the DA converter regardless of the output of the comparator, and means for instructing the sample and hold circuit to hold the output of the DA converter. Phase synchronized multi-pen recorder.