JPS6237350B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the timer body is constructed of a polyhedron having one face that is always parallel to all the faces, and different timers can be set depending on the mounting state of this polyhedron. This invention relates to a timer in which a timer is set at the same time as the time is set, and the set timer time is displayed on one side of a polyhedron.

In conventional electronic timers that count the timer time using a constant signal from a reference signal source, a switch is provided specifically for setting the timer time and setting the timer, and the necessary switches must be operated. Therefore, I was setting the timer time and setting the timer. However, in the method using these operation switches, for example, when setting a timer, first,
The timer time can be set using one switch, the timer time can be set using another set of switches, the timer time can be set again using the switch, and the timer time can be set using the timer set/non-set switch. You have to operate many switches over and over again to start the timer count. Therefore, it is very time-consuming to operate and requires a large number of switches, which is also a problem in terms of cost.

Furthermore, in recent years, in order to reduce the number of timer switches, some have adopted a method in which one switch has multiple functions.
Although this method reduces the number of switches, it has the disadvantage that the user is more likely to make operational errors and the troublesomeness of switch operation cannot be improved.

In particular, timers often measure the number of minutes from the start of some operation, and with conventional timers that require tedious operations, the timer time must be set and the timer set at the time to start measurement. There were many cases where the set did not meet the question, which was a problem.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to be able to set the timer time and set the timer without having to provide a number of operation switches on the timer and without performing troublesome operations. The goal is to provide such a timer.

In order to achieve the above object, the present invention comprises a timer main body as a polyhedron having one parallel face corresponding to all the faces, and furthermore, the timer body is configured to be turned on in accordance with the mounting state of the polyhedron. a timer counter that starts counting when at least one of the switch groups is turned on and whose counting time is different depending on each switch that is turned on; and a sound generation circuit that generates an alarm sound in response to an output signal from the polyhedron, and by placing one surface of the polyhedron as a mounting surface, setting the timer time and setting the timer can be done at the same time. The set timer time is determined depending on which side of the polyhedron is the mounting surface, and is further characterized in that it is displayed by a display that displays the set timer time on at least one side of the polyhedron.

Embodiments of the present invention will be described below based on the drawings.
FIG. 1 is a perspective view of a timer with a certain surface as a mounting surface in one embodiment of the present invention. The present embodiment is characterized in that the timer main body is constituted by a regular hexahedron, and the timer time is displayed on the top surface in each mounting state.

As shown in FIG. 1, the timer body 2 includes a frame 4 forming a regular hexahedron, and a switch plate 6 fitted in a portion corresponding to the surface of the frame 4 so as to protrude slightly.
and has. On this switch board 6, a numeral 8 indicating the timer time is printed. In the placed state shown in FIG.
-1 is printed on it, a display element 8-2 that displays "2" is printed on the switch board 6-2 serving as the side surface, and a display element 8-2 that displays "3" is printed on the switch board 6-3.
3 is printed.

FIG. 2 is a perspective view of the timer main body 2 of FIG. 1 viewed from direction B. On the other side of the switch board 6-4 is a display 8-4 that displays "4".
is printed, and a display 8-5 for displaying "1" is printed on the switch board 6-5.

FIG. 3 is a perspective view of the timer body 2 in a different mounting state from that shown in FIG. 1. In FIG. 3, the surface that was the mounting surface in FIG. 1 is the top surface, and a display 8-6 for displaying "OFF" is printed on the switch board 6-6 fitted into this surface. ing.

In Figure 4, each switch board 6 is shown with the internal circuit omitted.
FIG. 2 is a sectional view taken along the line AA in FIG. 1 showing the configuration of a switch provided below.

An elastic movable piece 10 is attached to the back side of each switch plate 6, and the end of this movable piece 10 is attached to a board 12 attached to the frame body 4. A pair of conductive members 14a and 14b are provided on the substrate 12 covered by the movable piece 10, and a conductive member 16 is also provided on the inner surface of the movable piece 10 at a position corresponding to the conductive members 14a and 14b. It is pasted. This switch plate 6, movable piece 10, conductive members 14a, 14b, 16, substrate 1
2 constitute a switch 18 that is turned on depending on the placement state of the timer main body 2.

Therefore, as shown in FIG. 1, when the timer main body 2 is placed with the switch plate 6-4 facing down, the switch plate 6-4 is pressed, and the movable piece 10 is also pressed, so that the board 12 Upper conductive member 14a-
4 and 14b-4 are brought into contact with the conductive member 16-4 in the movable piece 10-4, the conductive members 14a-4 and 14b-4 are electrically connected, and the switch 18-4 is turned on. Other switch board 6-1
〜6-3, 6-5〜6-6 are movable pieces 10-1〜
10-3, 10-5 to 10-6, and conductive members 14a-1 to 14a-3 and 1
4a-5 to 14b-6 and 14b-1 to 14b-
3 and 14b-5 to 14b-6, and the switches 18-1 to 18-3 and 18-5 to 1 are disconnected.
8-6 is turned off. As a result, the timer counter of the electronic circuit (not shown) in the frame 4 is set to 5.
The timer is set at the same time as the minute timer time is set. The set timer time is displayed on the display ``5'' printed on the upper switch board 6-1.

When the timer main body 2 is placed and the switch plate 6-1 is pressed as shown in FIG. -1 only is turned on. At this time, a timer time of 0 minutes is set in the timer counter, that is, no timer time is set, and the timer does not operate.

In this way, one of the switch groups 18 is turned on depending on the mounting state of the timer main body 2, and the timer time and timer set are performed, and the settings are made depending on which switch group 18 is turned on. The timer times are different. Also, the set timer time is displayed on the timer body 2
Display 8 printed on the switch board 6 on the top of the
Displayed by.

5 and 6 show the frame body 4 in this embodiment.
5 is a circuit diagram of the timer counter 20 and the sound generation circuit 22 built into the internal circuit. In particular, FIG.
The input circuits connected to each of -2 to 18-6 are shown.

In FIG. 5, the input circuit includes a chattering prevention circuit 24, one-shot circuits 26 and 28, flip-flops (hereinafter abbreviated as FF) 30 and 32, and an AND gate 34. The timer counter 20 has five input circuits, the output signal of the switch 18-2 becomes the input signal _A4 , the switch 18-3 becomes the input signal _A1 , and the output signal of the switch 18-2 becomes the input signal A1.
The signal at 8-4 becomes input signal A ₂ , and switch 1
The signal at switch 8-5 becomes input signal _A3 , and the signal at switch 18-6 becomes input signal _A5 . These input signals An (n=1 to 5) are connected to a one-shot circuit 26 via a chattering prevention circuit 24. The output from anti-chattering circuit 24 is also connected to one input of AND gate 34 and input D of FF 30. The Q output of the FF 30 is connected to the other input of the AND gate 34, and the output of the AND gate 34 is connected to the input D of the FF 32. The output Q of this FF 32 is input to the one shot circuit 28. Also FF3
A constant period signal D from a frequency dividing circuit 44 shown in FIG. 6 is input to the clock inputs 2 and 30.

FIG. 7 shows the relationship among the input signal A ₂ from the switch group 18-2 to 18-6, the output signal Bn of the one-shot circuit 26, the output signal Cn of the one-shot circuit 28, the constant period signal D, and the Q output signal En of the FF 32. It is a time chart diagram showing.

Using this time chart, each switch group 1
The operation when any one of 8-2 to 18-6 is turned on will be explained.

When the switch plate 16 is pressed, the signal An goes to L.
Rising from H to H. Here, the chattering prevention circuit 24 is configured such that the input signal has a time period shown in FIG.
The output signal is designed not to rise from L to H unless it rises to H for T1 or _more , thereby preventing malfunctions due to chattering of the switch 18. However, if the timer body 2 is placed on any one of the switch plates 16-2 to 16-6 as a placement surface, the input signal An
becomes H for more than ₁ hour. As a result, the chattering prevention circuit 24 outputs an H signal.
A positive single pulse is obtained from the output signal Bn of the one shot circuit 26. After this, when the constant period signal D rises, the output Q of the FF 30 becomes H, and at the same time, the output signal of the AND gate 34 also becomes H. After this, when the constant period signal D rises further, the signal En of the output Q of the FF 32 changes from L to H, thereby causing the output of the one shot circuit 28.
A single positive pulse is generated from Cn.

Thereafter, when the switch 18 is turned off, the input signal An falls from H to L, and accordingly, the output signal of the AND gate 34 also falls from H to L. After that, when the constant period signal D rises, FF
The signal En of the output Q of 32 falls to L.

However, as shown in FIG. 7, if the signal An falls within two periods (indicated by _T2 ) of the constant period signal D, a positive single pulse is generated in the signal Bn, but the clock input of FF32 Since the output of the AND gate 34 falls from H to L before the rising signal of the constant periodic signal D is input to φ, the signals Cn and En maintain the L state.

In this way, the timer main body 2 is placed, and one of the switches 18 is set to 2 of the constant periodic signal D.
When turned on for more than a period, the signal Bn from the input circuit
First, a positive single pulse is obtained, and then, after a slight delay, a positive single pulse is generated on the signal Cn, and the signal En rises to H.

FIG. 6 shows the timer counter 20 excluding the input circuits connected to each switch 18-2 to 18-6.
, the sound generation circuit 22 is shown.

In FIG. 6, the timer counter 20 includes, in addition to the input circuit, frequency dividers 38 and 40, and a second counter 4.
2, 44, minute counters 46, 48, AND gates 50, 52, OR gates 54, 56, 58, AND gates 60, 62, and FF 64.

The oscillation frequency from the oscillator 36 is divided by frequency dividers 38 and 40 and input to second counters 42 and 44, respectively, which count seconds. seconds counter 4
The carry signal from 2 is input to the minute counter 46, which causes the minute counter 46 to count the minutes. The count output signal of the minute counter 46 is input to the AND gate group 50, and when the minute counter 46 counts one minute, the AND gate 50-
An H signal is input to the AND gate 50-2, and after counting 2 minutes, an H signal is input to the AND gate 50-2. Similarly, if you count 3 minutes, ANDGATE 50-3
If you count 4 minutes, the AND gate will be 50-4.
If you count 5 minutes, the AND gate will be 50-5.
It is configured so that an H signal is input to each of them.

Further, the carry signal from the second counter 44 is inputted to the minute counter 48, and thereby the carry signal from the second counter 44 is input to the minute counter 48.
8 also counts minutes. The count output signal of the minute counter 46 is input to an AND gate group 52, and when the minute counter 48 counts one minute, an H signal is input to the AND gate 52-1, and when it counts two minutes, an H signal is input to the AND gate 52-1. Input the H signal to 2. Similarly, when counting 3 minutes, an H signal is input to AND gate 52-3, when counting 4 minutes, inputting an H signal to AND gate 52-4, and when counting 5 minutes, inputting an H signal to AND gate 52-5. There is.

In addition, ANDGATE 50-1 and 52-1
In this case, the signal E ₁ from the input circuit shown in FIG.
is input, AND gates 50-2 and 52-2
The signal E ₂ is connected to AND gates 50-3 and 5
A signal E ₃ is input to 2-3, a signal E ₄ is input to AND gates 50-4 and 52-4, and a signal E ₅ is input to AND gates 50-5 and 52-5. In addition to this, FF6 is added to the AND gate group 50.
The signal of the output Q of 4 is input, and the AND gate group 52
The inverted signal is input to . The outputs of the AND gates 50 and 52 are input to an OR gate 54.

On the other hand, signals C ₁ to _{C 5} from the input circuit are input to the clock input φ of the FF64 via the OR gate 58, and the output Q of the FF64 is also input to the AND gate 62, and the inverted signal is input to the AND gate 60.
The signal of output Q of FF64 is input. In addition, signals B ₁ to _{B 5} via the OR gate 56 are input to the AND gates 60 and 62 . Then, the output of the AND gate 60 is sent to the frequency divider 38 and the second counter 42.
and the reset input R of minute counter 46, and the output of AND gate 62 is input to the reset input R of frequency divider 40, second counter 44, and minute counter 48.

Further, a constant periodic signal D is input from the second counter 44 to the input circuit.

The sound generation circuit 22 includes a gate circuit 66 and a counter 6.
8. Notification circuit 70, AND gates 72, 74, 7
Consists of 6. The gate circuit 66 is a circuit that forms an alarm sound signal using the audible frequency signal from the frequency divider 38 and the intermittent frequency signal from the second counter 42, and this alarm sound signal is input to one side of the AND gate 76. The counter 68 is a counter that counts the alarm sound generation time based on a constant signal from the minute counter 46 via an AND gate 72, and its output is inverted and sent to the AND gate 74.
Enter it on one side. Further, the output of the OR gate 58 in the timer counter 20 is input to the reset input R of the counter 68, and if a positive single pulse is generated in any one of the signals _C1 to _C5 from the input circuit, , the count contents of the counter 68 are cleared.

On the other hand, the output of the OR gate 54 in the timer counter 20 is input to the other of the AND gate 74 to which the output of the counter 68 is input, and the output of the AND gate 74 is input to the other of the AND gates 72 and 76. .

The operation of this circuit will be explained below using the time chart shown in FIG.

As shown in FIG. 1, when the switch board 6-5 on which the display 8-1 for displaying "5" is printed is placed facing upward, the switch board 6-6 on the bottom is pressed, and the switch board 6-5 is pressed. 18-6 is turned on. This initially results in a single positive pulse in the signal _B6 . The pulse is input to AND gates 60 and 62 via an OR gate 56. In this state, if the signal F of the output Q of FF64 is L, then
A single pulse in phase with the signal B ₆ is obtained only at the output H of the AND gate 60, thereby clearing the count contents of the frequency divider 38, second counter 42 and minute counter 46, and starting counting from the initial value.

After this, if the timer main body 2 is placed in the same state, the signal E ₆ becomes H and the AND gate 5
0-5, 52-5, and the count contents of the counter 68 are cleared by the rise of a positive single pulse in the signal _C6 , and the signal F of the output Q of the FF64 rises from L to H, and as a result, the AND gate 50 - Only 5 is open.

In this state, even if the user accidentally presses the side switch plate 6-5, if the user releases the switch immediately, only a positive single pulse will be generated in the signal _B3 , as described above. Then, the signal E ₃ does not become H, and the signal C ₃ does not generate a positive single pulse. Then, the single pulse generated in the signal _B3 simply clears the count contents of the frequency divider 40, second counter 44, and minute counter 48 through the OR gate 56 and AND gate 62, and the count output of the minute counter 48 is inputted. Since the AND gate group 52 is closed at this point, no malfunction will occur due to erroneously pressing the switch plate 6-3.

On the other hand, each time one minute passes after the frequency divider 38, second counter 42, and minute counter 46 restart counting, the minute counter 46 changes its output to I ₁ , I ₂ , I ₃ ,
From L to H in the order of I ₄ and I ₅ . Therefore, when 5 minutes have passed, the output _J5 of the minute counter 46 becomes H,
Accordingly, the output J ₅ of the AND gate 50-5 and the output K of the OR gate 54 become H. At this time, since the count content of the counter 68 has been cleared, its output L becomes L, so the AND gate 7
The output of 4 becomes H. This result and gate 76
is opened, and a signal in phase with the alarm sound signal from the gate circuit 66 is obtained at its output M.
An alarm sounds. At the same time, the AND gate 72 opens and the counter 68 starts counting the constant signal from the seconds counter 46. Then, after a certain period of time has elapsed, the output L of the counter 68 rises to H, so the output of the AND gate 74 becomes L.
Then, the AND gate 76 closes and the alarm sound stops.

In this way, when the timer body 2 is placed with the switch board 6-1 on which the display 8-1 for displaying "5" is printed facing up, the timer time is automatically set to 5 minutes and the timer count is started. Start. Therefore, an alarm sound will be generated 5 minutes after the set time.

After that, when the switch board 6-3 on which the display 8-3 displaying "3" is printed faces upward, the switch board 6-5 is pressed and the switch 18 is pressed.
-5 turns on. This results in a single positive pulse in signal B ₅ which is connected to OR gate 56;
It is inputted to the reset input R of the frequency divider 40, second counter 44, and minute counter 48 via the AND gate 62 to clear the contents of these counts and start counting anew. After this, the signal E ₃ becomes H, and a positive single pulse is generated in the signal C ₃ . As a result, the counter 68 is cleared and its output L becomes L, and the output Q of the FF64 is
The signal F becomes L. As a result, only the AND gate 52-3 is left open.

Frequency divider 40, second counter 44, minute counter 48
When 3 minutes have passed since restarting counting, the output N ₃ of the minute counter 48 becomes H, and accordingly, the output O ₃ of the AND gate 52-3 and the OR gate 5
The output K of No. 4 also becomes H, and an alarm sound is generated for a certain period of time in the same manner as before.

In this way, when the timer body 2 is placed with the display 8-3 displaying "3" facing upward, the timer time is set to 3 minutes and the timer count starts at the same time.

As shown in FIG. 3, when the display body 8-6 with "OFF" displayed on it is placed on top, the switch plate 6-1 is pressed, but at this time, the signals B ₁ to
Nothing occurs in B ₅ , C ₁ to C ₅ , and E ₁ to E ₅ . Therefore, the timer does not work in this case.

In this way, according to the present embodiment, by simply placing the display 8 with the printed side facing up on which the timer time to be set is displayed, the desired timer time can be set at the same time. Since the timer is set, there is no need for operating switches or their troublesome operations.

The input circuit shown in FIG. 5 also includes a chattering prevention circuit 24, an FF 30, and an AND gate 3.
4, the timer time setting and timer set are not performed unless one switch 18 is kept on for a certain period of time, so even if the user presses the switch board 6 by mistake, No malfunctions will occur. There are two sets of counters that count the timer time, and one of the counters starts counting immediately after the timer body 2 is placed, so the input circuit turns on the switch 18. Even if time is provided to determine whether or not a malfunction has occurred, the timer setting time will not be changed due to this. Further, the set timer time can be seen at a glance by looking at the top surface of the timer main body 2, which is formed of a regular hexahedron, in the placed state.

Furthermore, in this embodiment, one surface of the timer main body 2, which is made up of a regular hexahedron, is provided with an "OFF" surface that sets the timer time to 0 minutes, that is, does not operate the timer. , or to stop the timer midway, display 8-- displays "OFF".
The side on which 6 is printed should face the top.

In this embodiment, a switch group 18 that is turned on by pressing a switch plate 6 protruding from each side is provided as a group of switches that are turned on depending on the placement state of the timer body. However, it is also possible to provide other switches, such as gravity switches that are turned on depending on the placement state of the timer main body, or a touch switch may be provided on each surface.

In addition, in this embodiment, the timer body is constructed from a regular hexahedron, but it can also be constructed from other regular polyhedrons that have one face that is always parallel to all faces. It is possible.

Furthermore, in this embodiment, a display body 8 for displaying the timer time is printed on the switch board 6 which becomes the upper surface when placed in the mounted state.
may be provided on another surface, and the display body 8 may be formed of an electro-optical display element such as a liquid crystal instead of printing.

As described above, according to the present invention, the timer body is constituted by a polyhedron having one face that is always parallel to all the faces, and furthermore, the timer body is configured to be turned on in accordance with the placement state of the polyhedron. a timer counter that starts counting when one of the switches is turned on, and is configured such that the counting time differs depending on each switch that is turned on; By having a sound generation circuit that generates an alarm sound based on the output signal of This eliminates the need for tedious operations and provides an extremely easy-to-use timer. Furthermore, since the set timer time is displayed on one side of the polyhedron that constitutes the timer body, the set timer time can also be easily recognized.

[Brief explanation of the drawing]

1, 2, and 3 are perspective views of a timer according to an embodiment of the present invention, and FIG. 4 shows the switch configuration provided under each switch plate 6 with the internal circuit omitted. 1, FIG. 5 is a circuit diagram showing an input circuit in a timer counter in an embodiment of the present invention, and FIG.
Figure 7 is a circuit diagram of the timer counter and sound generation circuit excluding the input circuit connected to each switch.
FIG. 8 is a time chart in FIG. 6. 2...Timer body, 4...Frame body, 6...Switch board, 8...Display body, 18...Switch, 20
...Timer counter, 22...Sound generation circuit.

Claims (1)

[Claims] 1 Consisting of a polyhedron that has one face that is always parallel to all of its faces, it further includes a group of switches that are turned on depending on the placement state of the polyhedron, an oscillator that generates a reference signal, and A timer counter that counts signals from the oscillator and generates an output signal when the count reaches a set value; and a timer counter that is connected to each of the switches and clears the count value of the timer counter in response to an on operation of each switch. and an input circuit that outputs a setting signal that causes the timer counter to generate an output signal that differs from each other.
A sound generation circuit that generates an alarm sound based on the output signal from the timer counter, and a display corresponding to the count time of the timer counter is provided on each side of the polyhedron, so that it corresponds to the mounting state of the polyhedron. The timer is characterized in that the timer time is set and the timer is started, and the timer time is displayed on at least one side of the polyhedron by the display body.