JPS6237356B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic hourly clock in which the number of hourly strokes can be set using an operating switch, and in particular, it is possible to reliably and easily set the number of hourly strokes that have been set due to an erroneous operation. This is about an electronic time clock that can be repaired.

In conventional electronic watches of this type, the setting of the hour strikes was often done by operating an operating switch the desired number of hour strikes.

In recent years, such electronic watches have been equipped with a nighttime muting function that stops the clock ticking operation at night (for example, from 11 p.m. to 5 a.m.). In order for this nighttime muffling function to work properly, when setting the number of hour strikes, it is necessary to distinguish between the hour strikes for the morning time and the hour strikes for the afternoon time. The batting correction switch was often divided into two, one for the morning and one for the afternoon.

Providing two switches for adjusting hour strokes in this way leads to erroneous operations such as operating the switch for adjusting the number of hour strokes for afternoon time when attempting to adjust the number of hour strokes for morning time.

Furthermore, in conventional electronic watches, after a certain period of time has passed after the hour striking setting operation is completed, the currently set hour striking is canceled and a new hour striking number is set by the next hour striking setting operation. There are many.

In such an electronic watch, if you realize that you have made a mistake and operate the switch once again after performing a series of set operations, you will not be able to see whether the last operation added 1 to the hour count or not. It was difficult to determine whether the number of strokes set by the previous operation was canceled and set at 1 o'clock.

The present invention is configured such that when the number of strokes per hour is set by mistake, the currently set number of strokes per hour is cleared when the switch for correcting the morning hourly stroke and the switch for correcting the afternoon hourly stroke are operated at the same time. The purpose is to eliminate the drawbacks of the example and to enable reliable and quick time correction.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. 2
1 is a reference signal generator consisting of a crystal oscillator, etc.; 4 is a frequency dividing circuit that appropriately divides the signal from the reference signal generator 2; 6 is a waveform shaping circuit; 8 is a drive circuit; 10 is a drive circuit for driving a wheel train, etc. This is a motor for

Reference numeral 12 denotes a reference circuit, which detects the hour on the hour by the movement of the wheel train driven by the motor 10 or by an electronic circuit, and outputs a signal _A1 for starting time striking.

Reference numeral 14 denotes a timing start signal generation circuit, which generates a signal for starting the timing operation to the next stage circuit, which will be described later.
A ₂ , A ₇ , A ₁₀ and a signal A ₈ for emitting the first ticking sound are output. At this time, the hitting start signal generation circuit 14 receives the signal from the guideline circuit 12.
A ₁ or the monitor signal output from the monitor signal generation circuit described later after the correction operation is completed.
It is activated by inputting _B9 .

16 is a timer circuit, which starts counting when reset by the signal A ₂ indicating that the time striking operation has started or the signal D ₂₄ indicating that the time striking operation has been corrected. Outputs signal _B3 for emitting the subsequent ticking sound.

This signal _B3 is the first signal that is output from the time striking start signal generating circuit 14 when the counter in the timer circuit 16 has counted a predetermined time after the corrective operation has been completed, or when it is on the hour. This is the one that is output following the time signal _A8 .

18 is a monitor signal generating circuit, which generates a signal B ₆ indicating that a certain period of time has elapsed since the correction operation was completed.
By inputting, the clock start signal generation circuit 1
4. Signal prompting the start of time striking as a monitor.
Output B ₉ and further signal indicating monitor mode
_B11 is output to the next stage circuit.

20 is a stroke counter, which counts the number of pulses of the signal _B3 . 22 is a comparison circuit;
24 is a number counter.

This comparison circuit 22 detects that the content stored in the number counting counter 24 and the count value of the stroke number counter 20 match, and outputs a detection signal C ₁₈ and a signal B ₃ outputted from the timer circuit 16. It is something that makes it stop. In addition, the number counter 24
is for storing the number of strokes per hour, and this stored value is modified or incremented by 1 by the operation of an external switch, which will be described later, or by the signal _A7 from the pulse start signal generating circuit 14.

26 is a night silence circuit, for example, at 11 p.m.
to 5 a.m. to stop the clock ticking. This nighttime noise reduction circuit 26 determines whether or not the nighttime sound is silenced based on the instruction signal C ₁₇ of the counting counter 24, and when the monitor mode is instructed by the signal B ₁₁ , the nighttime noise reduction circuit 26 determines whether or not the noise is to be silenced at night. It is configured not to mute the sound.

28 is an AM time correction switch, and 30 is a PM time correction switch.

If the AM hourly stroke correction switch 28 and PM hourly stroke correction switch 30 are operated individually, the number of strokes for each hour in the morning or afternoon will be corrected, and if both switches are operated at the same time, the current number of strokes will be displayed on the counter 24. The stored count value is cleared.

32 is a correction confirmation sound generation circuit, which outputs a confirmation sound signal D ₁₅ in response to the operation of the AM time correction switch 28 or the PM time correction switch 30;
It also outputs an AM time correction signal _D3 and a PM time correction signal _D4 .

34 is a time correction signal generation circuit, which generates a correction signal.
It converts D ₃ and D ₄ into various modified signals and outputs them.

At this time, the output of the correction signal D ₁₃ outputted from the striking correction signal generation circuit 34 is stopped by the action of the signal A ₁₀ during the striking operation, and even if the correction switch is operated during the striking operation, the number counter will not be activated. It is configured to prevent the memory contents of 24 from being changed.

36 is a simultaneous operation detection circuit, and switch 2
A signal D ₅ for determining which of 8 and 30 has been operated, and morning/afternoon determination signals D ₂₀ and D ₂₁ ,
A signal D ₂₄ that resets the timer circuit 16 in response to a switch operation other than during the time striking operation, and a signal that clears the contents stored in the counting counter 24.
D ₁₉ is output.

This signal D ₁₉ is generated when one of the switches 28, 30 is operated for the first time, or when the switch 28, 30 is operated for the first time.
This signal D19 is output when switch 30 is operated at the same time, and especially this signal _D19 is output when switch 2 is operated at the same time.
It is output by simultaneous operations of 8 and 30, and clears the stored contents of the number counter 24.

38 is a ticking sound generating circuit. or gate 40
The signal E ₁ outputted by is a composite signal of the signal A ₈ and the signal B ₃ , and this signal E ₁ includes the same number of pulses as the number of hourly strokes. Therefore, when the signal C ₃₃ indicating whether or not the sound is muted is at H level, the signal E ₁ is applied to the ticking sound generating circuit 38 via the AND gate 42, and the clocking sound generating circuit 3
8 outputs a striking sound signal _E5 . In this embodiment, the number of strokes counter 20, the comparison circuit 22,
The nighttime noise reduction circuit 26, the hour striking sound generating circuit 38, and the AND gate 42 constitute an hour striking signal generating circuit.

44 is a sound generation circuit, which generates a striking sound signal E ₅ inputted via an OR gate 46, and a correction switch 2.
It is output for each operation of 8 and 30 and the AND gate 48
and signal D ₁₅ applied via OR gate 46
Alternatively, a confirmation sound is generated in response to a signal _D7 outputted by simultaneous operation of the correction switches 28 and 30 and applied via an AND gate 49 and an OR gate 46.

The outline of the time-hitting correction operation in this embodiment is as follows.

By operating the correction switches 28 and 30 separately,
From the simultaneous operation detection circuit 36, a correction switch 28,
Signals D ₈ and D ₉ are output individually in response to each operation of 30.

The signals D ₈ and D ₉ each prompt the output of the time correction signal D ₁₃ from the time correction signal generation circuit 34, and the stored contents of the counting counter 24 are corrected by this signal D ₁₃ . be done.

Further, when the correction switches 28 and 30 are operated simultaneously, the simultaneous operation detection circuit 36
Detects that 8 and 30 are operated at the same time and sends a signal
D ₁₉ is output, and the memory contents of the counting counter 24 are cleared by this signal D ₁₉ .

In this way, in this embodiment, when an erroneous operation is made, by operating the correction switches 28 and 30 at the same time, it is possible to quickly clear the memory contents of the counting counter 24, which stores the number of strokes at the time of the erroneous operation. It is.

Next, the detailed configuration and operation of each circuit shown in FIG. 1 will be explained using FIG. 2 and subsequent figures.

Figure 2 shows the timing start signal generation circuit 1 shown in Figure 1.
4, FIG. 3 is a time chart at the start of normal timing, and FIG. 4 is a diagram showing a time chart at the start of timing in the monitor mode.

The timing start signal generating circuit 14 is activated by the signal _A2 output from the OR gate 50. This signal _A2 is output by OR gate 50 inputting and combining the signal _A1 outputted by the reference circuit 12 on the hour and the signal _B9 outputted from the monitor signal generation circuit 18 when the monitor mode is entered. This is a signal to

This signal _A2 is sent to the timer circuit 1 before starting the timer.
6 and the counter in the stroke counter 20 are reset.

Flip-flops 52, 54, and 56 input a signal ₁ obtained by inverting a clock signal φ ₁ (for example, with a frequency of 32 Hz) at an inverter 58 to their respective clock inputs φ, and input the output signal A ₂ of the OR gate 50 to their respective sets. I am typing into the input.

Therefore, when the timing or monitor mode is entered and one pulse signal _A2 is output from the OR gate 50, the flip-flops 52, 54, and 56 are set by the rise of this signal _A2 , and the outputs of the flip-flops 52, 54 are set. Signals A ₃ and A ₄ output from Q rise to H level, and signals output from the outputs of flip-flops 54 and 56.
_A5 and _A6 fall to L level.

The flip-flop 52 changes the output Q to _{the L level in synchronization with the fall of the clock signal 1 after} the signal A2 becomes the L level. When the signal A ₃ becomes L level, the flip-flop 54 which inputs this signal A ₃ to the input D switches the output Q and the state of the output in synchronization with the fall of the clock signal ₁ , and changes the signal A ₄ to L level, Set signal _A5 to H level.

The flip-flop 56, which inputs this signal _A4 to its input D, switches its output state in synchronization with the fall of the clock signal ₁ when the signal _A4 goes to L level, and sets the signal _A6 to H level.

The NOR gate 60 inputs the signals A ₃ and A ₅ , and when the signal A ₃ falls from the H level to the L level, it becomes H.
level, and when the signal _A5 rises to the H level, it outputs a one-pulse signal _A7 which becomes the L level.

This signal _A7 is applied to the monitor signal generating circuit 18, stroke counter 20, and number counter 24 shown in FIG. 1 to determine the initial state of each circuit.

The NOR gate 62 inputs the signals φ ₁ , A ₄ , and A ₆ , and outputs the clock signal φ between the time when the signal A ₄ falls to the L level and the time when the signal A ₆ rises to the H level.
A ₁ -pulse signal _A8 having the same pulse width as that of 1 is output.

This signal _A8 is for generating the first hour striking sound.

The latch circuit consisting of the NAND gates 64 and 66 inputs the signal A ₉ which is obtained by inverting the signal A ₇ outputted from the NOR gate 60 by the inverter 68, and makes the output signal A ₁₀ H level.
When _A10 becomes H level, it is instructed to each circuit in the next stage that timing has started.

This signal A ₁₀ returns to the L level by the signal B ₁₄ output from the timer circuit 16 after a certain period of time has elapsed after the last ticking sound was generated.

In this way, when the time-hitting start signal generating circuit 14 receives the signal _A1 or the signal _B9 , it immediately outputs the signal _A2 to reset the timer circuit 16 and the number-of-strokes counter 20, and then outputs the signal _A7 . This determines the initial states of the monitor signal generation circuit 18, the number of strokes counter 20, and the number counter 24, and further outputs the first stroke signal _A8 .

FIG. 5 is a circuit diagram of the timer circuit 16 and monitor signal generation circuit 18 shown in FIG. 1, FIG. 6 is a time chart during normal timing operation, and FIG.
The figure is a diagram showing a time chart during a time correction operation and a monitor operation.

A counter 70 is provided in the timer circuit 16, and during normal timing (see FIG. 6), it is reset by the signal _B4 output from the OR gate 72 to which the signal _A2 is input, and its clock input φ The clock signal φ1 input to the clock signal _φ1 starts counting.

When the counter 70 starts counting, its outputs Q ₁ to _{Q 6} successively become H level, and each H level signal is applied to the input terminal of the NAND gate 74 .

The NAND gate 74 outputs the output Q ₃ of the counter 70
In addition to inputting the signals from ~ _Q6 , it also inputs the output signal _B1 of the AND gate 76, which inputs the signal _A10 and the coincidence signal _C18 from the comparator circuit 22. The signal A ₁₀ becomes H level when the time striking operation starts, and the coincidence signal C ₁₈ also becomes H level at the start of the time striking operation due to the action of the signal A ₂ (details will be described later). Therefore, the AND gate 76 sets the output signal _B1 to H level at the start of the timing operation.

For this reason, the input terminal of the NAND gate 74 sequentially goes to the H level with the start of the timing operation, and when all the inputs reach the H level, the output goes to the L level.

When the output signal B ₂ of this NAND gate 74 becomes L level, the output of NAND gate 78 to which this signal B ₂ is input rises to H level. When the output signal B ₃ of this NAND gate 78 becomes H level, this signal B ₃ resets the counter 70 via the OR gate 72 . When the counter 70 is reset, the output signal _B2 of the NAND gate 74 rises to the H level again, so that the signal _B2 becomes a trigger pulse as shown in FIG. this signal
Output signal B ₃ of NAND gate 78 inputting B ₂
When the signal _B2 goes to the L level, it becomes a pulse signal having the same pulse width as the pulse width of the clock signal ₁ inputted to the negative input terminal of the NAND gate 82 via the inverter 80. On the other hand, counter 70
Every time it is reset to signal B ₃ , it counts again from the beginning, and as a result, NAND gate 7
4 outputs a trigger pulse at regular intervals, and in synchronization with this, the output signal of the NAND gate 78
_B3 is also output. This signal _B3 is applied to each circuit in the next stage as a time striking signal for the second and subsequent timing strikes.

When the comparator circuit 22 detects that the predetermined number of strokes has been reached, the signal _C18 goes to the L level, and at the same time the AND gate 76 is closed. Therefore, the output signal B ₁ of the AND gate 76 also goes to the L level, and the output signal B ₂ of the NAND gate 74 is fixed to the H level. As a result, Nand Gate 78
The output signal _B3 is fixed at L level, and the counter 70 counts up without being reset.

A NAND gate 84 inputting the outputs Q ₆ and Q ₈ of the counter 70 changes its output to the L level when the counter 70 counts up and brings the outputs Q ₆ and Q ₈ to the H level.

The signal B12 output by this NAND gate ₈₄ is L
When the signal B ₁₂ falls to the level, the NAND gate 86 inputting this signal B 12 outputs a one-pulse signal B ₁₃ having the same pulse width as the pulse width of the clock signal ₁ inputted to the NAND gate 88 . This signal B ₁₃
is inverted by the inverter 90, becomes a signal _B14 indicating that the time-beating has ended, and is applied to the time-beating start signal generation circuit 14, which brings the signal _A10 to the L level and returns to the initial state. In addition, when the AM time correction switch 28 or the PM time correction switch 30 shown in FIG. 1 is operated, or when the correction switches 28 and 30 are operated at the same time, the number of times the switch is operated as shown in FIG. signal D with a number of pulses according to ₂₄
is applied to the timer circuit 16.

This signal _D24 is applied to the clock inputs φ of OR gate 72, NOR gate 92, NAND gate 94, and flip-flop 96 in timer circuit 16.

When the NAND gate 94 receives the signal D ₂₄ , it immediately outputs a pulse signal B ₁₆ that falls from the H level to the L level. This signal _B16 is later used to reset the stored value of the counting counter 24.

On the other hand, the OR gate 72 inputting the signal _D24 is
A signal _B4 is output to reset the counter 70 each time the correction switch is operated.

The counter 70 starts counting again after being temporarily reset, but at this time, the output of the AND gate 76 is fixed at L level due to the action of the signal _A10 , so the outputs Q ₃ to _{Q 6} of the counter 70 become H level.
Even if it reaches the level of Nando Gate 74, 78
The output state of will not change. Therefore, the counter 70 is reset by the last pulse of the signal D ₂₄ , and then the counter 70 counts up, or the pulse interval of the signal D ₂₄ is changed so that the counter 70 can count up (about 5 seconds in this embodiment). When opened, outputs Q ₁ to Q ₈ become H level.

When the outputs Q ₆ and Q ₈ of the counter 70 go to the H level, the output signal of the NAND gate 84 falls from the H level to the L level.

As a result, the NAND gate 86 outputs one pulse, and the signal _B13 output from the NAND gate 86 is applied to the OR gate 98 as a modification end signal.

Before the correction end signal _B13 is output, the flip-flop 96 which inputs the signal _D24 to the clock input φ sets the output Q to H level in synchronization with the first falling edge of the signal _D24 , and also outputs is set to L level. Since the output of the NAND gate 94 is fixed at the H level when the signal B ₁₅ goes to the L level, only the first pulse of the signal D ₂₄ is passed through, and the pulses following this pulse are cut off. Also,
The signal _B6 outputted from the output Q of the flip-flop 96 is applied to the monitor signal generation circuit 18, and the flip-flop 100 which inputs this signal _B6 to the input D causes the output Q to rise to the H level. The flip-flop 102, which inputs the signal _B7 from the output Q of the flip-flop 100 to its input D, changes its output to the L level in synchronization with the fall of the clock signal _φ1 due to the rise of the signal _B7 . In this state, the signals B ₇ ,
The output signal _B9 of the NOR gate ₁₀₄ inputting B8 remains at L level. In this state, the signal _B13 goes high due to the operation described above.
When the level is reached, flip-flop 96 is reset via OR gate 98, and its output Q becomes L.
become the level. As the signal _B6 falls, the flip-flop 100 brings its output Q to the L level. When the signal _B7 goes to the L level, the flip-flop 102 switches its output to the H level in synchronization with the fall of the clock signal _φ1 .

While the output Q of flip-flop 100 goes to L level and the output of flip-flop 102 goes to H level, NAND gate 104 outputs one pulse. The signal _B9 outputted from the NAND gate 104 is applied as a monitor signal to the timing start signal generating circuit 14 to start the modified timing timing monitoring operation. At this time, signal B ₉ is inverter 1
06 to a latch circuit consisting of NAND gates 108 and 110, and further to an inverter 112.
A signal that instructs the stroke counter 20 and the night silencer circuit 26 that the monitoring operation has started via the
It is output as B ₁₁ . This signal B ₁₁ is equal to the signal B ₉
The signal B14 becomes L level at the same time as it is output, and rises to H level when the signal _B14 that is output when the monitor operation is completed is applied to the NAND gate 110.

In this way, the timer circuit 16 in the present invention
In the normal time-beating operation, it outputs the second and subsequent time-beating signal _B3 , and also outputs the signal _B14 indicating that the time-beating has ended, and in the time-beating correction operation, it first outputs the memorized value. outputs a signal B ₁₆ for resetting the monitor, then outputs an instruction signal B ₆ for causing the monitor signal generating circuit 18 to output a monitor signal, and also outputs a signal B ₁₄ indicating that the monitor operation has ended. It is.

Note that the timer circuit 16 during monitor operation
The operation is almost the same as normal operation. On the other hand, the monitor signal generating circuit 18 does not operate during normal timing operation, but is activated by the signal B ₆ outputted when the correction is completed, and outputs the monitor signal B ₉ indicating that the monitor operation is in progress. This outputs the signal _B11 .

FIG. 8 is a circuit diagram of the number of strokes counter 20, number counter 24, and night noise reduction circuit 26 shown in FIG. 1, and the configuration and operation of these circuits will be explained below in several states.

First, based on the time chart shown in FIG. 9, a description will be given of the time striking operation at 11:00 pm when the nighttime sound is turned off.

When the time-beating operation starts, the time-beating start signal generation circuit 1
4 outputs a signal _A2 and applies it to the stroke counter 20. This signal A ₂ is applied to the OR gate 114 within the stroke counter 20 . The output of this OR gate 114 is applied to each reset input of flip-flops 116-122 constituting the counter, and these flip-flops are reset via the OR gate 114 when the pulse signal _A2 is output.

The signal A ₇ is applied to the stroke counter 20 following the signal A ₂ . This signal A ₇ is inverted via the inverter 124 in the stroke counter 20,
Furthermore, it is applied to NOR gates 126 and 128.

Normally, these NOR gates 126 and 128 each input an H level signal B ₁₁ and an L level signal B ₁₁ inverted by an inverter 130 to other input terminals, and when a pulse signal A ₇ is applied,
Only the output signal _C3 of the NOR gate 128 becomes H level, and the flip-flop 118 is set.
The number of strokes counter 20 when this state is a normal time stroke
is the initial state.

The hourly stroke signal _B3 is applied to the stroke number counter 20 whose initial state has been determined in this way. This timing signal _B3 is a pulse signal output at intervals determined by the counter 70 in the timer circuit 16, and the flip-flop 116 that inputs this signal _B3 to the clock input φ is synchronized with the falling edge of the signal _B3 . to switch the state of output Q. When flip-flop 116 switches the state of output Q, flip-flops 118, 120, and 122 also sequentially switch their output states and start counting. Each output Q of these flip-flops 116 to 122 is a signal
It is applied to the comparator circuit 22 as the count number _B3 .

On the other hand, the output signal of the timing start signal generation circuit 14
A ₇ is also applied to an AND gate 132 in number counter 24 which is normally open due to signal B ₁₁ . This signal A ₇ is generated at the output signal C ₁₀ of AND gate 132 and is applied via OR gate 134 to the clock input φ of flip-flop 136. This flip-flop 136 constitutes a counter together with flip-flops 138, 140, and 142, and stores the number of strokes at a time preset by the signal _D13 . The output states of these flip-flops 136-142 are determined by a signal at the clock input φ of flip-flop 136.
It is switched by applying the one-pulse signal _C11 generated by _A2 , and this switched output state becomes the current number of strokes. The respective outputs Q of these flip-flops 136-142 are also applied to a comparison circuit 22, where they are compared with the count values of flip-flops 116-122 in the stroke counter 20.

Flip-flop 116 in stroke counter 20
-122 and flip-flops 136-142 in the counting counter 24 are flip-flops 12
0,122 and the outputs of the flip-flops 140, 142 are connected to the NAND gate 146 and the NAND gate 14, respectively.
The output of the flip-flop 11 is connected to the input terminal of the flip-flop 8, and the output of the flip-flop is connected to the input terminal of the flip-flop 11, which is connected to the input terminal of the flip-flop 8, and the output of the flip-flop is connected to the input terminal of the flip-flop 11.
6-122 or flip-flop 136-14
2. Therefore, flip-flops 116-122 and flip-flops 136-142 each constitute a hexadecimal counter. In addition, in normal time striking operation, each count value of these decimal counters is changed to AM/PM in the counting counter 24.
During the hour striking operation, it is necessary to instruct the night sound silencing circuit 26 in advance to switch between morning and afternoon and to start and cancel the night sound muffling, so it is advanced by one step in advance, and the number of strokes counter 20 also outputs a signal.
_B3 is the time signal for the second and subsequent times, and it is advanced by "2" in advance, taking into account that the count of the number counter 24 is advanced by one. In addition, during the monitor operation described later, the number counter 24
Therefore, the count value of the stroke counter 20 is set to be advanced by "1".

These stroke counter 20 and number counter 24
Comparison circuit 2 that compares the count values of each counter of
2 is flip-flop 1 in the stroke counter 20
When the flip-flops 16 to 122 are reset by the signal _A2 , their output signals _C18 are set to H level, and when the output states of flip-flops 116 to 122 and the output states of flip-flops 136 to 142 match, the output signal _C18 is set to L level. level. As described above, this signal C ₁₈ determines whether to output or stop the timing signal B ₃ output from the timer circuit 16.

The night noise reduction circuit 26 first passes the signal A ₁₀ which has become H level to the NAND gate 1 in the night noise reduction circuit 26.
It is input to the negative input terminal of 58. This NAND gate 158 receives a signal C ₁₇ from the NAND gate 154 in the counting counter 24 and a flip-flop 16 in the night noise reduction circuit 26 that discriminates between morning and afternoon.
It also inputs the signal C ₂₁ from the output Q of 0 to the other input terminal. The signal A ₁₀ input to this NAND gate 158 becomes H level at the start of striking, the signal C ₂₁ indicating afternoon is at H level at 11 p.m., and the signal C ₁₇ indicates that the number counter 24 is at 11 o'clock. It becomes H level when the time hit state is reached or when time hit correction is performed. Therefore, the output signal _C23 of the NAND gate 158 is normally H.
When the time striking operation starts at 11:00 pm, it goes to L level for a duration equal to the pulse width of signal _C17 . This signal C ₂₃ is applied to the NAND gate 162 and output as a pulse signal C ₂₅ rising from the L level to the H level. This signal C ₂₅ is applied via an inverter 164 to the clock input φ of a flip-flop 166 which determines nighttime muffling;
Flip-flop 166 outputs the inverted signal ₂₅
The output state is switched from L level to H level in synchronization with the falling edge of . This results in signal C ₃₂ and signal
The output of the NAND gate 168 which inputs B ₁₁ to its input terminal becomes L level, and the AND gate 42 shown in FIG. 1 is closed and the sound is muted at night. Therefore, the striking sound signal _E4 is not outputted from the striking sound generating circuit 38, and no striking sound is generated.

Next, based on the time chart shown in FIG. 10, a description will be given of the time striking operation at 6 a.m. when the nighttime mute state is released.

The time-beating operation starts, and the time-beating start signal generation circuit 1
The point that the signal _A7 is outputted from 4 to determine the initial state of the number-of-strokes counter 20 and the number-of-strokes counter 24 is exactly the same as the time-striking operation at 11:00 pm described above.

Flip-flop 116 in stroke counter 20
.about.120 and the count values of the flip-flops 136-142 in the counting counter 24 are naturally different from those at 11 p.m. In particular, the count values of the flip-flops 136 to 142 in the counting counter 24 are incremented by "1" every time the ticking operation is performed except for the monitor operation, and when the clocking operation starts at 6 a.m., they are set to "1" again. You can proceed. At this time, the NAND gate 170 in the night silencing circuit 26, which receives C ₁₂ , C ₁₃ , and C ₁₄ from the outputs Q of the flip-flops 136 , 138 , and 140 , receives an H-level signal C ₂₂ indicating morning. Therefore, when the signals C ₁₂ , C ₁₃ , and C ₁₄ change, the output is set to L level. The output signal of this NAND gate 170
The NAND gate 162 that inputs C ₂₄ has a signal C ₂₄ of L
In response to this level, its output signal C ₂₅
to H level. This signal C ₂₅ is inverter 1
Since the signal C25 is applied to the clock input φ of the flip-flop 166 via the signal _C25 , the output Q of the flip-flop 166 falls to the L level when the signal C25 rises. Therefore, the output of the NAND gate 168 which receives the H level signal B ₁₁ and the signal C ₃₂ rises to the H level, and the AND gate 42 shown in FIG. 1 is opened and the nighttime mute state is canceled.

In this embodiment, the night sound is muted at 11 p.m. and is turned off at 6 a.m., but the outputs of the flip-flops 136 to 142 in the number counter 24 can be changed to various combinations. By applying this to the nighttime noise reduction circuit 26, it is also possible to silence the noise at night at other times.

Next, the operations at 12:00 a.m. and 12:00 a.m. will be explained using time charts shown in FIGS. 11 and 12, respectively.

When striking at 12:00 am and 12:00 pm, the stroke counter 20 is first activated by the signals A ₂ and A ₇ from the striking start signal generating circuit 14 in the same manner as described above.
The initial state of the counting counter 24 is determined.

The difference between the 12:00 am and 12:00 pm clock operations is that the output state of the flip-flop 160, which determines morning and afternoon in the night silencer circuit 26, changes at the same time as the clock starts.

The clock input φ of this flip-flop 160
The output signal C ₂₀ of the AND gate 172 is applied to. A signal D ₁₁ from the time correction signal generation circuit 34 is applied to the − input terminal of this AND gate 172 via an inverter 174, and an output signal C ₁₉ of the NOR gate 176 is applied to the other input terminal.
is applied. Since signal D ₁₁ is normally at the L level, AND gate 172 is normally open, and when a pulse occurs in output signal C ₁₉ of NOR gate 176, it is generated in signal C ₂₀ .

The NOR gate 176 receives the output of the flip-flop 136 in the counting counter 24 and the outputs Q of the flip-flops 138-142, and also receives the output of the NOR gate 178.

When all the signals input to these NOR gates 176 go to L level, this NOR gate 176 sets its output to H level. flipflop 136
The signals applied from the flip-flops 136 to 142 to the NOR gate 176 are all set to go to L level when the count value corresponding to 12 o'clock is reached by the flip-flops 136 to 142. noah gate 1
The output signal C ₃₅ of the AND gate 180 is normally fixed at H level, and when the output signal C ₃₄ of the AND gate 180 becomes H level or the signal D ₂₅ from the time correction signal generation circuit 34 becomes H level. It is set so that it sometimes goes to L level. When the timing operation is started, the signal A ₈ is applied to the AND gate 180 . This signal A ₈ immediately appears on signal C ₃₄ . At this time, the signal _C34 becomes a pulse signal that rises from L level to H level, so NOR gate 1
The output signal _C35 of 78 becomes a pulse signal falling from H level to L level. At this time, all other inputs of the NOR gate 176 are at the L level, so the output signal _C19 of the NOR gate 176 is generated as a pulse signal rising from the L level to the H level.

This signal C ₁₉ is applied to the clock input φ of the flip-flop 160 via an AND gate 172, and the flip-flop 160 receives the input signal C ₂₀
The output state is switched in synchronization with the falling edge of .
As is clear from FIGS. 11 and 12, the output state of the flip-flop 160 at this time changes from the H level to the L level when the afternoon changes to the morning.
level, and the output changes from L level to H level, and vice versa when the time shifts from morning to afternoon.

The output signal C ₂₁ of this flip-flop 160,
C ₂₂ is applied to the NAND gates 158 and 170 for setting and canceling the nighttime sound deadening state, respectively, and determining which of these NAND gates 158 and 170 is to be enabled to set and release the nighttime sound deadening. used for. In this embodiment, the flip-flop 160, AND gates 172 and 180, inverter 174, and NOR gates 176 and 178 constitute an AM/PM discrimination circuit.

Next, using the time chart shown in FIG. 13, we will explain the operation when the number counter 24 and the night silencer circuit 26, which are set to strike 3:00 a.m., are modified to strike 3:00 p.m. explain.

When the PM time correction switch is operated, a signal _D13 is applied to the OR gate 134 in the number counter 24, which generates the same number of pulses as the number of times the PM time correction switch 30 is operated.

When this signal D ₁₃ is applied to the OR gate 134, a signal C ₁₁ that generates the pulses of the signal D ₁₃ is applied to the clock input φ of the flip-flop 136, and the flip-flops 136-142 count the number of pulses. This flip-flop 136-1
42 is the NAND gate 154 of the number counter 24 before the signal D ₁₃ is applied to the OR gate 134.
The pulse signal C ₁₇ caused by the signal D ₁₉ applied to
The number of strokes when going is corrected by counting the signal _C11 sequentially from 1.

On the other hand, the flip-flop 16 of the night silencing circuit 26
Set input S of 0 is set to PM time correction switch 3.
A pulse signal _D21 indicating that 0 has been operated is applied, and the output Q of the flip-flop 160 is brought to an H level. In this way, when the output signal C ₂₁ of the flip-flop 160 becomes H level, the night noise muffling circuit 26
The state changes from morning to afternoon.

Further, the signal D ₂₅ is also applied to the NOR gate 178 of the nighttime muffling circuit 26 from the time correction signal generation circuit 34 . This signal D ₂₅ also makes the output signal C ₃₅ of the NOR gate 178 pulse-like, and the NOR gate 17
6. flipflop 136~14
2 is the signal D. By counting one pulse of the signal D ₁₃ , the input signal of the NOR gate 176 becomes the signal
Since all signals except C ₃₅ go to L level, during this time the signal C ₃₅
The first pulse of passes through NOR gate 176 and is generated on signal _C19 .

At this time, the signal _D11 indicating that the switch is operated is at the H level, and when the PM time correction switch 30 is operated, the signal _D5 is at the L level.
It's getting to the level. Therefore, AND gates 184 and 186, which input this signal _D5 via the inverter 182 and further input the signal _D11 , are in an open state.

The signal C ₁₉ from the Noah gate 176 mentioned above is
It is applied to the reset terminal of flip-flop 166 through AND gate 186 and OR gate 188 to reset flip-flop 166. This flip-flop 166 was in a silent state at night, so its output Q was at H level.
It is reset by signal _C31 to cancel the nighttime mute state.

In contrast to the above operation, the time chart shown in FIG. 14 shows the operation when the counting counter 24 and the night noise muffling circuit 26, which are set to the hour striking state of 3:00 pm, are corrected to the striking state of 3:00 am. I will explain using

The operation of the counting counter 24 when changing from 3:00 pm to 3:00 am is the same as when changing from 3:00 am to 3:00 pm described above.

The difference from the operation described above is that the night noise silencing circuit 26
This is the switching operation of the output states of the flip-flops 160 and 166.

The signals D ₂₀ and D ₂₁ determine the output state of the flip-flop 160, and when the AM time correction switch 28 is operated, a pulse is generated only in the signal D ₂₀ . Therefore, flip-flop 160 is reset by operation of AM time correction switch 28. When the flip-flop 160 is reset and its output goes to H level, the nighttime muffling circuit 26 is set to the morning state.

On the other hand, the signals D ₅ and D ₁₁ rise to the H level with the operation of the correction switch, and the AND gates 190 and 192 to which these signals D ₅ and D ₁₁ are input are in an open state. At this time, a pulse signal is output from the NOR gate 176 by the action of the signal _D25 .
C ₁₉ is AND gate 190 and OR gate 19
4 to the set input S of flip-flop 166. As a result, the flip-flop 166 is set, and its output Q goes to H level, instructing the nighttime mute state.

In this way, when the time is corrected between the nighttime sound-off time period and the normal time period, the count value of the number counter 24 is corrected, and
flip-flop 160 in the night silence circuit 26;
By setting or resetting 166, setting/cancelling of morning, afternoon, and night muting is determined.

Next, a case where the hour striking state at 4 a.m. is corrected to 8 a.m., that is, a case where only the hour striking number and the night sound muting state are canceled without being corrected in the morning and afternoon will be explained using FIG. In this case as well, the correction of the count value of the counting counter 24 is the same as in other cases. Additionally, a flip-flop 160 in the nighttime muffling circuit 26 is connected to the AM hour correction switch 28.
A signal D ₂₀ that generates a pulse by being manipulated
However, since this flip-flop 160 has already been set to AM, its output state shows no change.

In this example, only the output state of the flip-flop 166 is switched from the nighttime mute state to the normal hourly sound state. i.e. signal
D ₁₁ and D ₅ become H level by operating the AM time correction switch 28, and therefore, the AND gate 19
2,190 is in the open state. These AND gates 192 and 190 sequentially receive pulse signals C ₁₇ ,
C ₁₉ is applied. Therefore, flip-flop 1
66 is reset once and immediately returns to the set state. At this time, the count value in the counting counter 24 is reset in advance and counts the number of switch operations sequentially from 1, and when this count value reaches 7, the output of the NAND gate 170 goes to L level. The output of the flip-flop 166 is switched to the H level, and the nighttime mute state is canceled.

In such a correction from morning to afternoon, since the sound is muted at night from 1 o'clock to 5 o'clock, unless the output state of the flip-flop 166 is changed according to the count value of the counting counter 24, it will not be possible to change the sound at 3 o'clock etc. Even if it is set, the sound may not be muted. Therefore, as in the above-described operation, the output state of the flip-flop 166 is switched based on the count value of the counting counter 24. On the other hand, if the timing is changed from 11:00 a.m. to 3:00 a.m., as shown in the time chart shown in FIG.
The output state of is determined by the output signals of AND gates 190 and 192. This is because the output of the NAND gate 170 does not change at all because the corrected count value of the counting counter 24 is within the nighttime sound-off period.

FIG. 17 is a diagram showing a time chart in monitor mode. As described above, the monitoring operation is started when the counter 70 in the timer circuit 16 counts up after the correction operation is completed. When in monitor mode,
The signal _B11 goes to L level, indicating that the monitor mode has been entered. At this time, the number of strokes counter 2
Flip-flop 116 in zero is set by signal _C2 to advance the count by one. This is the signal
When B ₁₁ becomes L level, the AND gate 132 in the counting counter 24 is closed, and the count value of the counting counter 24 can be advanced by the signal A ₇ outputted at the start of monitoring. This is because there is no

Also, the AND gate 180 in the nighttime noise reduction circuit 26
Since the output state of the flip-flop 160 is also in the closed state, the output state of the flip-flop 160 will not be changed to AM or PM during the monitoring operation.

Further, when the signal B ₁₁ goes to L level, the signal C ₃₃ , which is used to mute the sound at night, is fixed to H level. Therefore, even if the timing is corrected during the nighttime mute time period, the mute state is temporarily canceled due to the monitor operation and the monitor sound is generated. The other operations are the same as the above time hitting example.

In addition, the time chart for normal hitting is the first one.
The time chart is as shown in Figure 8, and this time chart was taken when striking at 4 o'clock.

FIG. 19 is a circuit diagram of the AM time correction switch 28, PM time correction switch 30, correction confirmation sound generation circuit 32, time correction signal generation circuit 34, and simultaneous operation detection circuit 36 shown in FIG.

FIG. 20 is a diagram showing a time chart when the correction switches 28 and 30 are operated individually or simultaneously.

The AM time correction switch 28 and the PM time correction switch 30 are switches 196, 200 and one shot multivibrators 198, 202, respectively.
It consists of.

When these correction switches 28 and 30 are operated individually, pulses are generated in the output signals D ₁ and D ₂ according to the number of operations, and when they are operated simultaneously, the signals D ₁ and D ₂ are generated.
A pulse occurs almost simultaneously. This signal D ₁ , D ₂
is the AND gate 2 in the correction confirmation sound generation circuit 32.
04 and 206, respectively, and the signals D ₃ and D ₄
occurs in

These signals D ₃ and D ₄ are both sent to the simultaneous operation detection circuit 3.
The voltage is applied to the NAND gate 208 in 6, and also applied to each input terminal of the NAND gates 210 and 212.

Each output signal of these NAND gates 210 and 212
D ₈ and D ₉ are applied to the NAND gate 214 in the time correction signal generation circuit 34 . The output signal D ₁₀ of the NAND gate 214 is sent to the flip-flop 21
It is applied to each set input S from 6 to 224.

A clock signal _φ1 is applied to each clock input φ of these flip-flops 216-224 via an inverter 226. When the correction switches 28 and 30 are operated individually, pulses corresponding to the switch operations are generated in the output signals D ₈ and D ₉ of the NAND gates 210 and 212, and accordingly, the output signal D ₁₀ of the NAND gate 214 is also generated. A pulse is generated.

Flip-flops 216 to 224, which input such a signal _D10 to a set input S, are set each time a switch is operated, and output a pulse signal having a pulse width widened by one period of the clock signal _φ1 from each output Q. Output.

From among the flip-flops 216 to 224 that output pulses in this way, signals D ₁₄ , D ₁₆ , D ₁₇ ,
D ₁₈ , D ₂₂ , D ₂₃ are taken out, and signals D ₁₄ and D ₁₆ are applied to the input terminal of the NOR gate 228, and the signals
D ₁₇ and D ₁₈ are applied to the input end of NOR gate 230, and signals D ₂₂ and D ₂₃ are applied together with clock signal _φ1 to the input end of NOR gate 232 and combined.

The signal _D12 output from the NOR gate 228 is applied to the reset input of the counter 70 of the timer circuit 16 via the OR gate 234 in the simultaneous operation detection circuit 36, and the counter 7 is reset every time the switch is operated.
0, and when the interval between pulses generated in this signal _D12 exceeds a certain value (approximately 5 seconds), the counter 70 counts up and instructs a monitoring operation.

In addition, the signal output from the NOR gate 230
_D13 is applied to the clock input φ of the flip-flop 136 of the counting counter 24 to correct the count value of the counting counter 24.

Furthermore, the output signal D ₂₅ of the NOR gate 232 is
It is applied to the NOR gate 178 of the nighttime silencing circuit 26, and is used to determine the output timing of the NOR gate 176. On the other hand, the signal from the output of the flip-flop 224 is generated as a signal D ₁₁ through an inverter 236, which informs the night sound deadening circuit 26 that the time is being corrected, and the AND gates 184, 186 in the night sound deadening circuit 26, 19
The open/close state of 0.192 is determined.

In addition, a signal _A10 from the timing start signal generation circuit 14 is applied to each reset input R of the flip-flops 216 to 224, and each correction signal is outputted by a switch operation during the timing operation or monitor operation. This prevents

At this time, the output signal from the stroke correction signal generation circuit 34
D ₁₂ is also applied to the set inputs of the flip-flops 238 and 240 of the correction confirmation sound generation circuit 32, and a confirmation sound signal D ₁₅ is output every time each switch is operated, and the clock is clocked by the OR gate 48 shown in FIG. After being combined with the signal φ ₂ , it is applied to the sound generation circuit 44 via the OR gate 46 .

This signal _D15 is applied to the AND gates 204 and 206 via the inverter 242, and invalidates the switch operation while the confirmation sound is being generated.

The operation of the time-hitting correction signal generating circuit 34 is common to the individual operations of the correction switches 28 and 30.

On the other hand, the simultaneous operation detection circuit 36 applies the output signals D ₈ and D ₉ of the NAND gates 210 and 212, which input the pulse signals D ₃ and D ₄ corresponding to the operation of the switch, to the NAND gates 244 and 246, respectively.
It is output as _D5 .

This signal _D5 becomes H level when the AM correction switch 28 is operated, and becomes L level when the PM correction switch 30 is operated.

Therefore, when the AM correction switch 28 is operated, the AND gate 248 is opened and the signal D ₁₃ applied to its - input terminal is generated as its output signal D ₂₀ , which is output as the AM signal. Furthermore, when the PM correction switch 30 is operated, the signal D ₅ that has reached the L level is inverted by the inverter 250 and applied to the AND gate 252 to open it, generating the signal D ₁₃ as the output signal D ₂₁ . Then, it is output as the afternoon signal. In this embodiment, the NAND gates 210, 212, 244
and 246, AND gates 248 and 252, and an inverter 250 constitute an AM/PM correction discrimination circuit.

When the correction switches 28 and 30 are operated at the same time,
Pulses are generated in the signals D ₃ and D ₄ at the same time. The NAND gate 208 to which these signals D ₃ and D ₄ are input is
In this way, when the signals D ₃ and D ₄ become H level at the same time, the output signal D ₆ becomes L level.

This signal D ₆ is inverted by the inverter 254 and becomes a pulse signal D ₇ that rises from the L level to the H level. This signal D ₇ is transmitted to the correction switch 28,
This signal indicates that 30 is operated simultaneously, and is applied to AND gate 49 shown in FIG. 1 and combined with clock signal _φ4 .

The output signal _E4 of the AND gate 49 is applied to the sound generation circuit 44 via the OR gate 46, and a simultaneous operation confirmation sound is generated. Also, this signal D ₇
is generated on signal D ₁₉ via OR gate 256,
Applied to number counter 24 to reset it.

In this way, the signal D ₁₉ for resetting the counting counter 24 is obtained by converting the signal B ₁₆ outputted from the timer circuit 16 by the first operation of the correction switches 28 and 30 to the OR gate 256 via the inverter 258. It may also be generated as an H level signal at the output.

Note that when the AM time correction switch 28 and the PM time correction switch 30 are operated at the same time, there may be some deviation in operation, so the pulse width output from the one-shot multivibrators 198 and 202 should be increased to some extent. The influence of deviation in lever operation can be eliminated.

Note that when the correction switches 28 and 30 are operated at the same time, the output signal D ₆ of the NAND gate 208
Since the output signals of the NAND gates 210 and 212 are fixed, the time correction signal generation circuit 34 does not output a time correction signal. In this example,
The NAND gate 208, the OR gates 234 and 256, the inverter 254, and the inverter 258 described later constitute a clear signal generating circuit.

Next, based on FIG. 1 again, the operation when the time ticking sound and confirmation sound are generated will be explained using the time charts shown in FIGS. 21 and 22. In normal timing (see FIG. 21), the signal _A8 and the signal _B3 are applied to the OR gate 40, and the timing signal _E1 is output. This signal E ₁ is generated as the output signal E ₂ of the AND gate 42 which is open when the sound is not muted at night.

This signal E ₂ is applied to the tapping sound generating circuit 38 having a capacitor etc.
8 outputs the hour striking signal _E5 . At this time, as shown in the figure, the tapping signal _E5 is a signal that slowly converges after being output, but any other signal may be used.

This signal _E5 is applied to the sound generating circuit 44 via the OR gate 46 to generate a ticking sound.

On the other hand, when the correction switches are operated individually (see FIG. 22), a correction confirmation sound signal _D15 is output every time the switch is operated, and this signal _D15 is synthesized with the clock signal _φ2 by the AND gate 48. signal
Output as E ₃ .

Since this signal E ₃ is directly applied to the sound generation circuit 44 via the OR gate 46, it is a different signal from the signal E ₅ arranged by the ticking sound generation circuit 38, and the generated sound is also different, so the user must check It is possible to easily determine whether it is a sound or not. Furthermore, when the correction switches 28 and 30 are operated simultaneously, the signal _D7 is applied from the simultaneous operation detection circuit 36 to the negative input terminal of the AND gate 49, and is combined with the clock signal _φ4 and output as the signal _E4 . Ru. This signal E ₄ is also directly applied to the sound generation circuit 44 via the OR gate 46 .

When the switch operation is completed and a predetermined time (approximately 5 seconds) has elapsed, the monitor operation is started, and the signal E ₁ is passed through the AND gate 42 to generate a ticking sound, just like the normal ticking described above. It is applied to the circuit 38 to output a ticking signal _E5 .

According to the present invention, even if a switch is operated incorrectly, the memory contents of the counting counter can be quickly cleared by operating two correction switches at the same time, and the operation error can be reliably and quickly corrected. be able to.

Also, by hitting the time as a monitor, you can confirm that the correcting action for the time has been completed, and recognize that if you operate the switch after hitting the monitor time, the set number of times will be cleared. You can also do that. Further, when the two correction switches are operated simultaneously, a sound indicating simultaneous operation is generated, so that the user can also recognize from this operation sound that the number of strokes for the hour has been cleared.

Furthermore, it is possible to clear the number of strokes by simultaneously operating the correction switch during monitor operation, etc., and even if you realize that you have made an incorrect operation during monitor operation after setting the hour stroke, you can immediately clear the number of strokes. It is something that can be corrected.

According to the present invention, operational errors can be corrected reliably and quickly.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the time-beat start signal generation circuit shown in FIG. 1, and FIG. 3 is a time-beat correction signal generation circuit during normal time-beat operation. Figure 4 showing the time chart of each signal of
The figure shows a time chart of each signal of the timer start signal generation circuit during monitor operation, Figure 5 is a circuit diagram of the timer circuit and monitor signal generation circuit shown in Figure 1, and Figure 6 shows the normal timer start signal generation circuit. FIG. 7 is a diagram showing a time chart of each signal of the timer circuit and monitor signal generation circuit during operation. FIG. 7 is a diagram showing a time chart of each signal of the timer circuit and monitor signal generation circuit during time correction operation. FIG. Figure 1 is a circuit diagram of the stroke counter, comparison circuit, number counting counter, and night silencer circuit shown in Figure 1.
Figure 10 shows a time chart of each signal of the stroke counter, comparison circuit, number counting counter, and night silence circuit when striking the hour. Figure 11 shows the time chart of each signal of the stroke counter and the night silencer circuit, and Figure 11 shows the time chart of the signals of the stroke counter, comparison circuit, number counter, and night silencer circuit when striking 12:00 a.m. Figure 12 is a diagram showing the time chart of each signal of the stroke counter, comparison circuit, count counter, and night silencer circuit when striking 12:00 p.m., and Figure 13 is a diagram showing the time from 3:00 a.m. to 3:00 p.m. A diagram showing a time chart of each signal of the number of strokes counter, comparison circuit, number counter, and night silencer circuit when performing stroke correction,
Figure 14 is a diagram showing the time chart of each signal of the stroke counter, comparison circuit, number counting counter, and night silence circuit when the time is corrected from 3:00 pm to 3:00 am, and Figure 15 is a diagram showing the time chart of each signal from 4:00 am. The number of strokes counter, comparison circuit, when correcting the number of strokes at 8 a.m.
Figure 16 shows the time chart of each signal of the number counter and the night noise reduction circuit.
FIG. 17 is a diagram showing a time chart of each signal of the comparison circuit, number counting counter, and night silencing circuit. FIG. 17 is a diagram showing a time chart of each signal of the stroke counter, comparison circuit, number counting counter, and night silencing circuit during monitor operation. , FIG. 18 is a diagram showing a time chart of each signal of the number of strokes counter, comparison circuit, number counter, and night silence circuit during normal striking operation.
Figure 9 shows the modification confirmation sound generation circuit shown in Figure 1;
A circuit diagram of the AM/PM correction discrimination circuit and the time correction signal generation circuit, Fig. 20 shows the circuit diagram of the AM/PM correction signal generation circuit when the AM time correction switch and the PM time correction switch are operated.
FIG. 21 is a diagram showing a time chart of each signal of the circuit shown in the figure. FIG. 21 is a diagram showing a time chart of a striking sound signal. FIG. 22 is a diagram showing a time chart of a striking sound signal and a confirmation sound signal during a correction operation. It is a diagram. 14...Timer start signal generation circuit, 16...Timer circuit, 18...Monitor signal generation circuit, 20
...Blow counter, 22...Comparison circuit, 24...
Counter, 26...Night silencer circuit, 28...
...AM time correction switch, 30...PM time correction switch, 32...Correction confirmation sound generation circuit, 34...
... Time striking correction signal generation circuit, 36... Simultaneous operation detection circuit, 38... Time striking sound generation circuit, 44... Sound generating circuit.

Claims (1)

[Claims] 1. A clock start signal generation circuit that outputs a clock start signal every hour on the hour; a counting counter circuit that counts the clock start signals and outputs a time signal corresponding to the time; an AM/PM discrimination circuit that switches between and outputs the AM signal and the PM signal in response to a specific time signal from the counting counter circuit; An electronic hourly clock comprising: a hourly striking signal generation circuit that outputs a preset number of hourly striking signals based on a signal; and a sound generating circuit that generates a striking sound based on the hourly striking signal; A correction switch, a PM hour correction switch, and an AM setting signal by operating the AM hour correction switch, and a afternoon setting signal by operating the PM hour correction switch, to the AM/PM discriminating circuit, and making the determination. an AM/PM correction discrimination circuit that sets the output state of the circuit to the AM signal or the afternoon signal, respectively; and an AM/PM correction discrimination circuit that outputs a time correction signal in response to the operation of either one of the above-mentioned double time correction switches; A time-hitting correction signal generation circuit that increments the contents of the number-taking counter circuit; and a clear signal generation circuit that outputs a clear signal in response to simultaneous operation of the both-time-hitting correction switch and clearing the contents of the number-taking counter circuit. An electronic timepiece characterized by having a circuit and the following.