JPS6237550B2 - - Google Patents
Info
- Publication number
- JPS6237550B2 JPS6237550B2 JP53048944A JP4894478A JPS6237550B2 JP S6237550 B2 JPS6237550 B2 JP S6237550B2 JP 53048944 A JP53048944 A JP 53048944A JP 4894478 A JP4894478 A JP 4894478A JP S6237550 B2 JPS6237550 B2 JP S6237550B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- insulating film
- gate
- high concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
Landscapes
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し特に、絶縁ゲート電
界効果半導体装置におけるゲート絶縁膜の絶縁破
壊を防止するための保護装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a protection device for preventing dielectric breakdown of a gate insulating film in an insulated gate field effect semiconductor device.
近来、高性能の集積回路が要求され絶縁ゲート
電界効果半導体集積回路に関してはゲート絶縁膜
がきわめて薄くなり500Å以下の膜も実用されつ
つあり、保護装置の重要性は大きくなつている。
保護装置の効果的なものとして、第１図に示され
る如く、入力端子１と入力トランジスタ２の間に
拡散抵抗３と、ドレイン耐圧（BVDS）を利用し
て電圧をクランプするために用いられる保護トラ
ンジスタ４が設けられているものがある。保護ト
ランジスタ４の断面を第２図に示す。以下の説明
において半導体基板はＮ型とするがＰ型の場合も
同様に説明できる。 In recent years, high performance integrated circuits have been required, and gate insulating films for insulated gate field effect semiconductor integrated circuits have become extremely thin, with films of 500 Å or less being put into practical use, and the importance of protection devices has increased.
As an effective protection device, as shown in Fig. 1, a diffused resistor 3 is placed between the input terminal 1 and the input transistor 2, and a drain breakdown voltage (BV DS ) is used to clamp the voltage. Some devices are provided with a protection transistor 4. A cross section of the protection transistor 4 is shown in FIG. In the following explanation, the semiconductor substrate is assumed to be of N type, but the same explanation can be applied to the case of P type.
Ｎ型半導体基板５の表面に入力拡散層となるド
レイン６と基板に接続されるソース７が設けら
れ、両拡散層の間にフイールド絶縁物９よりも薄
いゲート絶縁膜８の上にゲート電極１１が設けら
れ、かつ上記電極１１が基板５に接続されてい
る。図中１０はコンタクト孔である。 A drain 6 serving as an input diffusion layer and a source 7 connected to the substrate are provided on the surface of an N-type semiconductor substrate 5, and a gate electrode 11 is provided on a gate insulating film 8 which is thinner than a field insulator 9 between both the diffusion layers. is provided, and the electrode 11 is connected to the substrate 5. In the figure, 10 is a contact hole.
前述の保護トランジスタ４はクランプ能力が大
きい事から広く用いられているが、次の欠点があ
る。すなわちドレインとゲート、ソースで発生す
るドレイン近傍の強い電界のため、ドレイン近傍
で電子−正孔対が生じ正孔はドレインにひきつけ
られ削減するが基板に流れ出た電子は基板の電位
を局部的に下げ、ソースと基板局部が順方向とな
りドレイン−基板−ソースがＰ−Ｎ−Ｐのトラン
ジスタとなり過大電流が流れ保護トランジスタ４
又はゲート絶縁膜が破壊する事がある。 The protection transistor 4 described above is widely used because of its large clamping ability, but it has the following drawbacks. In other words, due to the strong electric field near the drain generated by the drain, gate, and source, electron-hole pairs are generated near the drain, and the holes are attracted to the drain and reduced, but the electrons flowing into the substrate locally increase the potential of the substrate. When the source and the local part of the substrate are in the forward direction, the drain-substrate-source becomes a P-N-P transistor, and an excessive current flows through the protection transistor 4.
Or the gate insulating film may be destroyed.
上述の点を改良したものとして、第３図に示さ
れるソース拡散相のないトランジスタすなわち、
ゲートコントロールダイオード１２を用いたもの
がある。ゲートコントロールダイオード１２の断
面は第４図に示される。かかるダイオード１２に
より、Ｐ−Ｎ−Ｐ現象は防止されるが、ドレイン
に過大電圧が印加されて、ブレークダウンしたあ
との電流の抵抗が大きくなり、従つて、ドレイン
のクランプ電圧が高くなつてしまうという欠点が
あつた。 As an improvement on the above point, a transistor without a source diffusion phase as shown in FIG.
There is one using a gate control diode 12. A cross section of gated diode 12 is shown in FIG. Such a diode 12 prevents the P-N-P phenomenon, but an excessive voltage is applied to the drain, which increases the resistance of the current after breakdown, and therefore increases the drain clamp voltage. There was a drawback.
本発明の目的は上述の欠点を改良した優れたゲ
ート保護機能を有する半導体装置を提供すること
にある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having an excellent gate protection function that overcomes the above-mentioned drawbacks.
本発明による半導体装置は、一導電型の半導体
領域に設けられ、入力信号が印加される逆導電型
領域と、一導電型の高濃度領域と、上記逆導電型
領域上の一部から上記高濃度領域上にまで延在さ
れた薄い絶縁膜上に設けられ、一部が高濃度領域
に接続された電極とを含むゲートコントロールダ
イオードを保護素子としたことを特徴とする。 A semiconductor device according to the present invention includes a semiconductor region of one conductivity type, an opposite conductivity type region to which an input signal is applied, a high concentration region of one conductivity type, and a part of the opposite conductivity type region extending from the high concentration region. The protection element is a gate control diode provided on a thin insulating film extending over the high concentration region and including an electrode partially connected to the high concentration region.
本発明によれば保護されるべきトランジスタの
前段に保護抵抗となるべき、半導体基板と反対の
導電型を有する第一の領域が設けられ、上記第一
の領域の少くとも一部に相対する半導体基板表面
の位置に、基板と同一の導電型を有し、かつ高濃
度の第二の領域を設け、さらに上記第一、第二の
領域の一部を含みその間の基板表面に、フイール
ド絶縁膜よりもうすい絶縁膜が設けられ上記絶縁
膜は導電性電極によつておおわれ、かつこの電極
が第二の領域に接続されている半導体装置が得ら
れる。 According to the present invention, a first region to serve as a protection resistor and having a conductivity type opposite to that of the semiconductor substrate is provided in front of the transistor to be protected, and a semiconductor substrate facing at least a part of the first region is provided. A second region having the same conductivity type as the substrate and having a high concentration is provided on the surface of the substrate, and a field insulating film is further provided on the surface of the substrate between the first and second regions. A semiconductor device is obtained in which a thinner insulating film is provided, the insulating film is covered with a conductive electrode, and this electrode is connected to the second region.
以下に本発明の一実施例を第５図および第６図
を用いて説明する。 An embodiment of the present invention will be described below with reference to FIGS. 5 and 6.
第５図に示すように入力信号は端子１に印加さ
れ、この端子１から抵抗３を介して絶縁ゲート型
電界効果トランジスタ２のゲートに入力される。
この抵抗３の所定部に接続されたゲートコントロ
ールダイオード１３を設け、このダイオードのゲ
ート電極下に基板と同一の導電型を有する高濃度
不純物領域を吸収抵抗R1として形成する。すな
わち、第６図のように、Ｎ型半導体基板５にはド
レインとしてのＰ型領域６と、このＰ型領域６の
一部をおおうように設けたゲート絶縁膜８上に延
在されたゲート電極１１によつてゲートコントロ
ールダイオード１３を形成する。このゲート電極
１１にその主要部が重なるようにして設けられた
抵抗R1としてのｎ型の高濃度領域１４が設けら
れ、この領域１４は保護膜９に設けられた開口１
０を介してゲート１１と接続する。不純物領域１
４がある事によりＰ型領域６近傍のブレークダウ
ンにより発生したブレークダウン電流はほとんど
不純物領域１４に吸収され、ブレークダウン抵抗
は小さくでき又Ｐ−Ｎ−Ｐのトランジスタ作用も
防止する事ができる。さらに、電極１１は絶縁膜
８を介してドレイン領域６の一部をオーバーラツ
プしているのでブレークダウン電圧を小さくする
ことができ、保護効果を確実なものとすることが
できる。 As shown in FIG. 5, an input signal is applied to a terminal 1, and is inputted from this terminal 1 via a resistor 3 to the gate of an insulated gate field effect transistor 2.
A gate control diode 13 connected to a predetermined portion of this resistor 3 is provided, and a high concentration impurity region having the same conductivity type as the substrate is formed as an absorption resistor R 1 under the gate electrode of this diode. That is, as shown in FIG. 6, an N-type semiconductor substrate 5 has a P-type region 6 serving as a drain, and a gate extending over a gate insulating film 8 provided so as to partially cover this P-type region 6. A gate control diode 13 is formed by the electrode 11 . An n-type high concentration region 14 as a resistor R 1 is provided so that its main portion overlaps with this gate electrode 11 , and this region 14 is connected to the opening 1 provided in the protective film 9 .
0 to the gate 11. Impurity region 1
4, most of the breakdown current generated by breakdown near the P-type region 6 is absorbed by the impurity region 14, the breakdown resistance can be reduced, and the P-N-P transistor action can also be prevented. Furthermore, since the electrode 11 partially overlaps the drain region 6 via the insulating film 8, the breakdown voltage can be reduced, and the protective effect can be ensured.
以上の説明により本発明による保護装置を用い
れば外部異変電圧に対する半導体装置の破壊強度
を強くできる事がわかる。また本発明は上述の実
施例に限定されるものではなく、他のゲート保護
回路と併用しても良いことも勿論である。 From the above explanation, it can be seen that by using the protection device according to the present invention, the breakdown strength of the semiconductor device against external abnormal voltage can be increased. Further, the present invention is not limited to the above-described embodiment, and it goes without saying that it may be used in combination with other gate protection circuits.
第１図および第２図は従来の第１の例の半導体
装置を示す回路図、第３図および第４図は、従来
の第２の例の半導体装置を示す回路図および断面
図、第５図および第６図は本発明による第１の実
施例を説明するそれぞれ回路図である。図中の記
号は、以下に示す。
１……入力端子、２……入力トランジスタ、３
……入力保護抵抗、４……保護トランジスタ、５
……半導体基板、６……ドレイン拡散層、７……
ソース拡散層、８……薄い絶縁膜、９……フイー
ルド酸化膜、１０……コンタクト孔、１１……金
属電極、１２……保護ゲートコントロールダイオ
ード１、１３……保護ゲートコントロールダイオ
ード２、１４……基板と同一導電型高濃度不純物
領域。
1 and 2 are circuit diagrams showing a first example of a conventional semiconductor device, FIGS. 3 and 4 are a circuit diagram and a cross-sectional view of a second example of a conventional semiconductor device, and FIG. FIG. 6 is a circuit diagram illustrating a first embodiment of the present invention. The symbols in the figure are shown below. 1...Input terminal, 2...Input transistor, 3
...Input protection resistor, 4...Protection transistor, 5
...Semiconductor substrate, 6...Drain diffusion layer, 7...
Source diffusion layer, 8... Thin insulating film, 9... Field oxide film, 10... Contact hole, 11... Metal electrode, 12... Protective gate control diode 1, 13... Protective gate control diode 2, 14... ...High concentration impurity region of the same conductivity type as the substrate.
Claims (1)
が印加される逆導電型領域と、一導電型の高濃度
領域と、前記逆電型領域の一部をおおい前記高濃
度領域上にまで延在された薄い絶縁膜と、該薄い
絶縁膜上に設けられ一部が前記逆導電型領域上に
位置し、かつ前記高濃度領域に接続されている電
極とを有する保護素子を含むことを特徴とする半
導体装置。1. An opposite conductivity type region provided in a semiconductor region of one conductivity type and to which an input signal is applied, a high concentration region of one conductivity type, and a part of the opposite conductivity type region extending over the high concentration region. a protective element having a thin insulating film formed on the thin insulating film; and an electrode provided on the thin insulating film, a part of which is located on the opposite conductivity type region, and connected to the high concentration region. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4894478A JPS54140880A (en) | 1978-04-24 | 1978-04-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4894478A JPS54140880A (en) | 1978-04-24 | 1978-04-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54140880A JPS54140880A (en) | 1979-11-01 |
| JPS6237550B2 true JPS6237550B2 (en) | 1987-08-13 |
Family
ID=12817379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4894478A Granted JPS54140880A (en) | 1978-04-24 | 1978-04-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54140880A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0474464A (en) * | 1990-07-16 | 1992-03-09 | Matsushita Electron Corp | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4952467U (en) * | 1972-08-15 | 1974-05-09 |
-
1978
- 1978-04-24 JP JP4894478A patent/JPS54140880A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54140880A (en) | 1979-11-01 |
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