JPS6238800B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor memory element.

In semiconductor integrated circuits (hereinafter abbreviated as IC),
RAM (random access) that forms an array structure
Memory), PROM (programmable read-only memory), etc. are becoming more and more highly integrated and bit-rich due to advances in the development of circuits and process technology. Electrically writable AIM (Avalance
PROM and FPLA (Field Programmable Logic Array) based on semi-fixed memory elements (hereinafter referred to as cells) using the Induced Migration method
etc. also have a similar tendency. Recently, in ICs with array structures that are becoming more highly integrated and have higher bits, as a remedy for ICs that contain defects in part of the array or in blocks, it is necessary to clearly identify the block containing the defective area at the time of product production, and to remove only the other blocks. The so-called redundancy method involves creating a partially non-defective product into a product by using a defective part in the design process, and by setting up a block for a substitute bit for a defective part in advance, and when a defective bit occurs, eliminating that part and switching to this substitute bit, treating the entire product as a non-defective part. We are using a circuit system with a certain degree of accuracy. Similarly, defects in parts or blocks can be easily detected in a short time during the inspection process as early as possible in the IC manufacturing process, providing smooth feedback to the manufacturing process, avoiding trouble in subsequent processes, and reducing man-hours. However, it is becoming increasingly important for manufacturers to improve yield and reduce costs.

AIM type PROM and FPLA currently being developed
etc., generally have a common write terminal and read terminal in order to avoid increasing the size of the IC case. For example, consider the case of a 16-word 2-bit PROM.
The conventional circuit configuration is as shown in FIG. In the figure, the digit line selection decoder includes first and second write decoders 1 and 2 and first and second read decoders 3 and 4, which are separately provided. Switching between write decoder and read decoder is done from CE terminal 5.
Through NAND logic 6, O _B1 circuit 7, O _B2 circuit 8
It is carried out by killing (active state and non-active state). In addition, since the write operation requires high power, the first and second write decoders 1 and 2 have _S11 circuits 9 to _S14 circuits 12 as amplification functions and sense circuits.
The S ₂₁ circuit 13 to the S ₂₄ circuit 16 and the high power drive circuit 17 with row line selection decoder are provided with a function to cut off paths other than the write path. The unwritten cells C on the array in this circuit consist of transistors with open bases, as shown in FIG. Referring to FIGS. 1 and 2, a write operation involves writing one digit line 20 on the array to outputs 21, 22 and inputs 25, 26.
, select one row line 27 while input 2
3 and 24, and a higher voltage and higher current than the output are applied to the cell C on the intersection.
In addition, in a normally written cell, the junction between the emitter and the base is destroyed and consists of a resistance component 30 of several ohms and a base-collector diode component 28 for preventing interference between adjacent bits.
That is, this is the case where the value of the resistor 30 is small in FIG. 3b. When voltage resistance defects in unwritten cells that normally occur due to various manufacturing reasons are modeled using equivalent circuits, the cases shown in FIGS. 3a to 3d can be considered.
Among these, the cell in FIG. 3a has column line 20 and row line 2.
It has only a resistor 30 between it and 7. No.
30b consists of a resistor 30 of several tens of ohms or more and a diode 28 connected in series. In the cell of FIG. 3c, a series body of a base-collector diode 28 and a base-emitter Zener diode 29 is connected between the column line 20 and the row line 27, and a resistor is connected in parallel to the diode. 32 and 31 are connected. FIG. 3d shows a circuit configuration in which the resistor 32 is removed from the configuration shown in FIG. 3c. The difficulty in detecting defects in cell voltage resistance is mainly determined by the resistance values of the resistors 30, 31, and 32. Among these types of defects, Fig. 3a and Fig. 3b
In this case, most of the detection is done by scanning the cells on the array bit by bit as seen from the output terminals 21 and 22.
By performing a binary scan from inputs 3 and 24 and inputs 25 and 26, it is possible to use the analog level when the first and second write decoders 1 and 2 are used, and the logic level when the first and second read decoders 3 and 4 are used. be. However, in the cases of FIGS. 3c and 3d, it is difficult to detect defects. The reason for this is that when using the write first and second digit line selection decoders 1 and 2, the decoders 1 and 2 are equipped with current amplification latch circuits, so the output latch may be affected by AC noise etc. during read actual use. This is because it is difficult to design the first and second write decoders 1 and 2 in such a way that they can meet the characteristic standards, including prevention, and also detect minute leakage currents present in the write path including voltage-resistant defective cells. Furthermore, when using the readout digit line selection decoders 3 and 4, a high-voltage cut-off decouple is required for all write paths because a large amount of power is used during writing.
This is because it is difficult to design a highly sensitive sense circuit that is sensitive to cell voltage defect bits, has wide process variations, and has operating margin tolerances. Therefore, voltage-resistant defective cells that can be reliably detected from the output of the external terminal are limited to most of the modes shown in FIGS. 3a and 3b. Also, AIM method PROM.FPLA
etc. are high-voltage circuits, and on the other hand, they aim to achieve low power consumption and high speed, which determines the quality of the product during actual use.
Since it is an IC, the operating amplitude of each part should be kept as small as possible with respect to the load inside the circuit.
It is designed to reduce the time constant. Therefore, in terms of direct current, in chips with cell voltage resistance defect bits shown in Figures 3c and 3d, even if the output is within the standard logic level due to the overdrive current for speeding up when viewed from the external terminal. , in terms of alternating current, it may only be seen as a speed delay. In such a case, detection in the wafer state is greatly influenced by floating elements in the measurement system, making it difficult to measure in AC real time. Of course, it is also difficult to detect unwritten products in the inspection process after the product is assembled and enclosed in a case. Furthermore, it may cause a decrease in the writing yield for the user, and the greatest advantage of PROM.FRLA etc. will be lost, leading to a decrease in product reliability. From the above, the AIM method
It is difficult to detect all defect modes in the wafer state for arrays such as PROM.FPLA that contain voltage-resistant defective bits.

The purpose of the present invention is to achieve higher integration and higher bits.
In PROM.FPLA, etc., for voltage resistance defects in some of the cells on the array that occur due to various manufacturing reasons, the entire array can be scanned by binary scan using only the row line selection input, or by connecting the detection terminal at once. The object of the present invention is to provide a circuit that does not need to be provided separately and can be easily detected on a wafer.

A first aspect of the present invention provides a semiconductor device in which a memory element is connected between each digit line and each row line, and an external terminal for selecting the digit line is provided. One end of each diode is connected, the other end of the diode is connected in common, one end of a series body of a constant voltage diode and a resistor having a Zener voltage higher than the normal operating voltage is connected to the other end, and the other end of the diode is connected in common. The other end of the series body is connected to the external terminal.

A second aspect of the present invention is that a memory element is connected between each column line and each row line, and a row selection decoder for selecting the column line and a first decoder for selecting the column line are provided. and a semiconductor device provided with a second external terminal, one end of each first diode is connected to the girder line, the other end of the first diode is commonly connected, and a normal operating voltage is applied to the other end. One end of a first series body of a first constant voltage diode having a higher Zener voltage and a first resistor is connected, one end of each second diode is connected to the row line, and the second The other ends of the diodes are commonly connected, and a first transistor is connected to the other end to set the other end to a predetermined potential when the transistor is turned on. One end of a second series body of a second constant voltage diode having a voltage and a second resistor is connected, and the other end of the second series body is connected to the second external terminal and the row line A second transistor is connected to the selection decoder, which deselects all the row lines when turned on, and a third constant voltage diode having a Zener voltage higher than the normal operating voltage is connected to the base of the second transistor. 3rd with resistor
One end of the third series body is connected, and the other end of the third series body is connected to the second external terminal.

According to the present invention, there is a high degree of integration and a high bit rate.
It is possible to easily detect voltage resistance defects in some cells on arrays such as AIM-based PROMs and FPLAs.

A schematic circuit diagram of an embodiment of the present invention is shown in FIG.
The present invention will be described in detail with reference to this. In this case as well, the case of a PROM having an array structure of 16 words and 2 bits will be taken as an example, as in the conventional case of FIG. In the circuit of this embodiment, a base-collector diode 42 having a common base is connected to the digit line selection input 25 via a resistor 40 and a Zener diode 41 having a Zener voltage higher than the normal operating voltage of the base-collector short circuit. , 43, 44, 45 and base-collector diodes 46, 47, 4
It has a circuit block (hereinafter referred to as A-block) in which the collectors of 8 and 49 are connected to each digit line, and a transistor is connected to the digit line selection input 26 via a resistor 50 and a Zener diode 51 shorted between the base and collector. Zener diode 51 on the base of 52
base-collector diodes 53, 54, 55, which connect the collectors of the transistors 52 and 52, ground the emitters of the transistors 52, and have this collector as a common collector.
56, and connect the diodes to input 2, respectively.
It has a circuit block (hereinafter abbreviated as B-block) connected to the row selection output line of the high power drive circuit 17 with a row line selection decoder determined by 3 and 24, and further has a resistor 57 and a base-collector short circuit connected to the input 26. Transistor 59 through a Zener diode 58 having a Zener voltage higher than the normal operating voltage of
A circuit block (hereinafter abbreviated as C-block) is connected to the base of the transistor 59, the emitter of the transistor 59 is grounded, the collector is connected to the input stage of the drive circuit 17, and the drive circuit 17 is activated or killed.
Note that the resistors 60, 61, and 62 and the base-collector diode 63 on the upper right are added to stabilize the circuit operation. In addition, to simplify the explanation, the potential difference based on the impedance in the direction from the column line, ie, the emitter, to the row line, ie, the collector, of a normal cell is Vc, and the Zener diodes 41, 51,
The potential difference based on the impedance seen from the inputs 25 and 26 of the Vz transistors 52 and 59 and the base-collector diodes 52 to 45, 4
Let the forward voltages of 6 to 49 and 53 to 56 be V _F1 and V _F2 , respectively.

An embodiment corresponding to the first aspect of the present invention includes an array of semi-fixed memory elements (cells) consisting of a plurality of electrically writable open-base transistors, and the array includes a plurality of cells. The emitters are connected by one column line and the collectors are connected by one row line, and a plurality of column lines and row lines form a lattice, and a base collector diode (hereinafter referred to as D ₁ ), connect the bases of the D ₁ as a common connection, connect the base of a Zener diode (hereinafter abbreviated as D ₂ ) to the base, connect the emitter of the D ₂ to one side of the resistive element,
The circuit configuration is such that the other element is connected to the digit line selection external terminal, and according to this embodiment, voltage resistance defects in unwritten cells on the array can be corrected by applying a predetermined constant voltage to the terminal, It can be easily detected by scanning the row lines. The operation in this case will be explained. First, in FIG. 4, the operation of this embodiment is performed by killing the OB ₁ circuit 7 and the OB ₂ circuit 8 (inactive state) by using the write state, that is, the terminal 5.

Now, when viewed from the input terminal 25, the impedance of the circuit that runs through the A block, the 8-digit line, the cell C, and one row line selected to be at a low level (hereinafter abbreviated as V _WL ) by the drive circuit 17 is determined. The underlying potential difference is
It is given by V _Z +V _F2 +V _C +V _WL (hereinafter collectively referred to as V _S ). That is, the lowest breakdown voltage of the eight cells interposed between the first row line and all eight digit lines in the V _WL state is found. During actual detection, a precision resistance element (hereinafter abbreviated as R _S ) is connected to the outside of the input 25, and its open terminal is connected to a voltage of about 1 ^V (approximately depending on the miniaturization process conditions of the elements inside the IC, etc.) than the V _S mentioned above. (determined) Apply a low constant voltage,
While scanning each output line of the drive circuit 17 by binary input to terminals 23 and 24, the potential drop (hereinafter abbreviated as ΔV _C ) from the voltage on the open side of precision resistance element R _S is monitored at 25 terminals. Bye. That is, one selected row line (V _WL level)
If there is a breakdown voltage abnormality in the eight intervening cells, a current of ΔV _C /R _S is detected at 25 terminals. Further, if it is normal, ΔV _C becomes zero and the current becomes zero. Therefore, there are no restrictions on inspection conditions,
Even minute leakage currents can be easily detected in the wafer state.

An embodiment based on the second invention of the present invention is
Including the main circuit block of the above embodiment, the bases of the bases, collectors, and diodes are connected to the plurality of row lines, and the collectors are commonly connected, and the collectors are the collectors of transistors (hereinafter abbreviated as _T1 ); The emitter of T ₁ is grounded, and the T ₁
The circuit configuration includes a circuit block in which the base of D2 is connected to the base of a Zener diode such as _D2 , the emitter of the diode is connected to one of the resistor elements, and the other is connected to the external terminal for selecting the digit line. For example, a breakdown voltage defect in an unwritten cell on the array can be easily detected by applying a constant voltage to each of the terminals.

This embodiment is a modification of the above-mentioned embodiment to enable a simpler inspection. That is, terminal 26
By applying (V _Z +V _F1 ) or more to the input terminal, the transistors 52 and 5 of the B and C blocks
9 is activated to the saturation region, and when the transistor 59 is turned on, the operation of all the drive circuits 17 is stopped, that is, all the row line outputs are set to a non-selected high level, and at the same time, the
When the transistor 52 of the block is at the on level, all row line outputs are pseudo-selected to be turned on via the diodes 53 to 56. In this state, by monitoring the potentials at 25 terminals under the same conditions as in the previous embodiment, cell voltage resistance defects in the entire array can be detected at once. However, in this case, the forward voltage V _F2 of the diodes 53 to 56 is
It is better to measure in addition to the constant voltage on the open terminal side of _S.
Minute currents can be detected with higher precision.

Therefore, by using the present invention to detect defects in cell withstand voltage, all defects can be known regardless of the types of defects that occur due to various manufacturing reasons, and it is possible to detect defects in diodes 42 to 49. and 53-5
6 separates signals during normal operation applied to each digit line and each row line, respectively, for each digit line and each row line, and each Zener diode 41, 51, 5
Since each circuit block A to C is separated from the signal during normal operation by 8, there is no problem with normal write operation, and there is no influence on read operation.
Since no separate measurement terminal is provided, there are no restrictions on the inspection process, and detection can be easily performed both in the wafer state and after assembly.

Further, according to the present invention, leakage current through the detection path shown in FIG. 4, for example, leakage between the collector and the substrate can be simultaneously detected.

The present invention is not limited to the PROM of the above embodiment,
It is also applicable to AIM-based FPLA, etc.

The effects of the present invention are that cell voltage resistance defects can be easily detected in the wafer state, making measurement easy, reducing assembly man-hours, and increasing reliability. Furthermore,
The larger the array size, the higher the rate of occurrence of cell breakdown defects, and the present invention is particularly effective in such cases.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a conventional AIM type 16-word, 2-bit PROM. Figure 2 is
FIG. 2 is a circuit diagram showing a cell in an unwritten state using the AIM method. Figure 3a, Figure 3b, Figure 3c, Figure 3d
Both are equivalent model diagrams of voltage resistance defects in AIM cells. FIG. 4 is a circuit diagram of an embodiment of the present invention. In the figure, 1...first write decoder,
2... Second write decoder, 3... First read decoder, 4... Second read decoder, 5... CE terminal, 6... NAND circuit, 7...
O _B1 circuit, 8...O _B2 circuit, 9...S ₁₁ circuit, 1
0...S ₁₂ circuits, 11...S ₁₃ circuits, 12...S ₁₄
Circuit, 13...S ₂₁ circuit, 14...S ₂₂ circuit, 15
...S ₂₃ circuits, 16...S ₂₄ circuits, 17...High power drive circuit with row line selection decoder, 20...digit line, 2
1... Output (O ₁ ) terminal, 22... Output (O ₂ ) terminal, C... Cell, 23... Input (AX ₁ ) terminal, 2
4...Input (AX ₂ ) terminal, 25...Input (AY ₁ ) terminal, 26...Input (AY ₂ ) terminal, 27...Row line,
28...Base-collector diode, 29...
...Base-emitter diode, 30, 31...
...Base-emitter resistance, 32...Base-collector resistance, 40, 50, 57, 62...Resistor, 41, 51, 58...Zener diode,
42, 43, 44, 45, 46, 47, 48, 4
9, 53, 54, 55, 56... Base-collector diode, 52, 59... Transistor,
60, 61, 62... Auxiliary resistor, 63... Auxiliary base-collector diode.

Claims (1)

[Scope of Claims] 1. In a semiconductor device in which a memory element is connected between each digit line and each row line, and an external terminal for selecting the digit line is provided, one end of each diode is connected to the digit line. are connected, the other ends of the diodes are commonly connected, one end of a series body of a constant voltage diode and a resistor having a Zener voltage higher than the normal operating voltage is connected to the other end, and the other end of the series body is connected. is connected to the external terminal. 2 A memory element is connected between each column line and each row line, and a row line selection decoder for selecting the column line and first and second external terminals for selecting the column line are provided. In the semiconductor device, one end of each first diode is connected to the girder line, and the other end of the first diode is commonly connected,
One end of a first series body of a first voltage regulator diode and a first resistor having a Zener voltage higher than the normal operating voltage is connected to the other end, and the other end of the first series body is connected to the first series body. one end of each second diode is connected to the first external terminal, and one end of each second diode is connected to the row line;
The other ends of the second diodes are commonly connected, and a first transistor is connected to the other end, which brings the other end to a predetermined potential when turned on, and a normal operating voltage is applied to the base of the first transistor. One end of a second series body of a second constant voltage diode having a higher Zener voltage and a second resistor is connected, and the other end of the second series body is connected to the second external terminal. , a second transistor that deselects all the row lines when turned on is connected to the row line selection decoder, and a third constant voltage having a Zener voltage higher than a normal operating voltage at the base of the second transistor. A semiconductor device, wherein one end of a third series body of a diode and a third resistor is connected, and the other end of the third series body is connected to the second external terminal.