JPS6238892B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency dividing circuit having an input pulse frequency shifting function suitable for MOS integrated circuits. Recently, digital tuning FM,
AM radio is being developed. In such a tuning radio, a PLL frequency synthesizer is used, and a prescaler at the front stage thereof is provided with a frequency dividing circuit having a frequency shifting function. FIG. 1 is a block diagram of the conventional frequency dividing circuit having a frequency shifting function. In the figure, an input pulse signal f _IN having a frequency of 200 MHz is supplied to the input terminal of the binary counter 11 at the front stage of two binary counters 11 and 12 connected in series, and the Q output signal Q ₂ of the binary counter 12 at the rear stage is It is supplied to the clock input terminals of an inverter 13 and two 1-bit shift registers 14 and 15 connected in series. A switching signal whose level is inverted every predetermined period is supplied to the D input terminal of the 1-bit shift register 14 via an inverter 16.
Output signal _Q3 and 1-bit shift register 15
Both output signals ₄ are supplied to a NAND gate 17. Furthermore, a shift signal that becomes "0" is supplied to the NAND gate 17 via an inverter 18 when a frequency shift is requested.
The output signal X of the NAND gate 17 is supplied to the NAND gate 19 together with the output signal of the inverter 13, and the output signal Y of the NAND gate 19 is further supplied to the input terminal of the binary counter 20. FIG. 2 is a timing chart showing the operation of the above circuit. Next, using this timing chart, the operation will be briefly explained. First, when the shift signal is "1", the NAND gate 17 is activated regardless of the level of the switching signal. Output signal
becomes “1”, the NAND gate 19 following this opens, and the 50 MHz signal Q ₂ frequency-divided by the two binary counters 11 and 12 is supplied to the binary counter 20. As a result, binary counter 2
0 divides Q ₂ by 1/2, and the frequency of the Q output signal Q ₅ becomes 50/2MHz as shown in FIG. on the other hand,
When a frequency shift request occurs and the shift signal becomes "0", and after that, when the switching signal becomes "0", in synchronization with the next rising edge of the Q output signal _Q2 of the binary counter 12,
The Q output signal _Q3 of the 1-bit shift register 14 becomes "1", and the output signal ₄ of the 1-bit shift register 15 becomes "1" at the same time as the next rising edge of _Q2 .
becomes “0”. At this time it is still “0”
, the output signal X of the NAND gate 17 becomes "0" for one bit period _of Q ₂ as shown in FIG. Become.
As a result, the Q output signal of the binary counter 20
The frequency of Q ₅ is 1/2 of the signal 1 Hz lower than the frequency of Q ₂ , 50 MHz, that is, 25 MHz -
It becomes 0.5Hz. Conventionally, ultra-high-speed elements such as ECL have been used for high-speed operating circuits such as prescalers, but ECL has drawbacks in terms of power consumption and integration. On the other hand, MOS transistors that can operate at several 100 MHz have now been developed, and frequency synthesizers can be made into single frequency synthesizers using CMOS transistors.
The situation is such that it can be turned into chips. However, when the conventional frequency dividing circuit having the frequency shifting function of _input pulses shown in FIG.
Since it passes through the gate of the stage, that is, the inverter 13 and the NAND gate 19, the input signal f
When the frequency of _IN is made extremely high, there is a drawback that the binary counter 20 may malfunction due to the influence of the signal transmission delay time due to the two-stage gate. This invention was made in consideration of the above circumstances, and its purpose is to provide an input pulse frequency shifting function that enables high integration, low power consumption, and high-speed operation. The object of the present invention is to provide a frequency dividing circuit with An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of one embodiment of the present invention, and parts corresponding to those of the conventional circuit are given the same reference numerals, and the explanation thereof will be omitted. Therefore, to explain the differences from the conventional circuit, the Q of the binary counter 12 is
The output signal Q ₂ is the input terminal T of the binary counter 21
In addition to being supplied directly to NAND gate 17
The output signal S of is supplied to the shift control signal input terminal S of this binary counter 21. Here, the binary counters 11 and 12, shift registers 14 and 15, inverters 16 and 18, and NAND gate 17 control the level change of the switching signal whose level is inverted every predetermined period when the frequency shift of the input pulse f _IN is requested. A circuit is constructed which generates a shift control signal S whose level is inverted during a predetermined bit period of the input pulse f _IN by detection. FIG. 4 shows in detail the binary counter 21 in which the shift control signal output terminal S is added in addition to the input terminal T, and is a falling synchronization in which the state of the output signal changes at the falling edge of _Q2 . The case of a binary counter of Eq. The circuit in Figure 4 is
Broadly divided into master flip-flop circuits 41
and a slave flip-flop circuit 42 . That is, the master flip-flop circuit 41
Here, the CMOS consists of an N-channel type MOS transistor 43 and a P-channel type MOS transistor 44.
P-channel type MOS transistors 45 _, 46 _, 47 (first to third MOS
Create a CMOS circuit by inserting a parallel circuit (transistor)
48 , and an N-channel MOS transistor 49 and a P-channel MOS transistor 50.
There is a P between the CMOS inverter main body _consisting of
Channel type MOS transistors 51, 52, 53
A CMOS circuit 54 is formed by inserting a parallel circuit of (fourth to seventh MOS transistors). The input and output terminals of the CMOS circuit 48 and the output and input terminals of the CMOS circuit 54 are connected in phase, thereby forming a flip-flop element 55 . Also
_N -channel MOS transistors 56 , 57, 58 (seventh
N-channel MOS transistors 59 and 6 are connected in series and are connected between the output terminal Q _M of the CMOS circuit 54 and the ground.
0 and 61 (10th to 12th MOS transistors) are connected in series. In the slave flip-flop circuit 42 , a P channel type MOS transistor 62, an N channel type MOS transistor 62,
A parallel circuit of P-channel type MOS transistors 64 and 65 (the 13th and 14th MOS transistors) is inserted between the CMOS inverter body consisting of the MOS transistor 63 and the ground to form the CMOS circuit 66.
Also, between the CMOS inverter main body consisting of a P channel type MOS transistor 67 and an N channel type MOS transistor 68 and the ground, an N
Channel type MOS transistors 69, 70 (No.
15, 16th MOS transistor) are inserted in parallel to form a CMOS circuit 71 . and
The input and output terminals of the CMOS circuit 66 and the output and input terminals of the CMOS circuit 71 are connected in phase, thereby forming a flip-flop element 72 . Also CMOS circuit
Between the output terminal of 66 and _VDD , there is a P channel type
MOS transistors 73, 74 (17th, 18th
MOS transistors) are connected in series, and a P-channel type transistor is connected between the output terminal Q of the CMOS circuit 71 and _VDD .
MOS transistors 75 and 76 (19th and 20th
MOS transistors) are connected in series. Also, transistors 46, 51, 58, 61, 6
The gates of 5, 69, 73, and 75 are connected to the _Q2 output terminal of the binary counter 12, and the CMOS circuit 4
The output terminal _M of the CMOS circuit 54 is connected to the gates of the transistors 64 and 74, and the output terminal _M of the CMOS circuit 66 is connected to the gates of the transistors ₄₅ and 76. 56, and the output terminal of CMOS circuit 71 .
Q ₆ is connected to the gates of transistors 53 and 59. Further, the gates of the transistors 46, 52, 57, and 60 are connected to the output terminal of the NAND gate 17. That is, the binary counter 21 is configured as follows. N-channel type MOS transistor 43 and P-channel type MOS transistor 44
A CMOS inverter body consisting of P channel type first, second and third MOS transistors 45,
The first one is formed by inserting 46 and 47 parallel circuits.
Input and output terminals of CMOS circuit and N-channel MOS
A second CMOS circuit is constructed by inserting a parallel circuit of fourth, fifth, and sixth P-channel MOS transistors 51, 52, and 53 into a CMOS inverter body consisting of a transistor 49 and a P-channel MOS transistor 50. A first flip-flop element is formed by connecting the output terminal and the input terminal, and N-channel type seventh, eighth, and ninth MOS transistors 56, 5 are connected between the output terminal of the first CMOS circuit and the ground.
7, 58, N-channel type 10th, 11th, and 12th circuits are connected between the output terminal of the second CMOS circuit and the ground.
A master flip-flop 41 having first and second series circuits each having MOS transistors 59, 60, and 61 inserted in series, and a CMOS inverter comprising a P channel type MOS transistor 62 and an N channel type MOS transistor 63. A third transistor is formed by inserting a parallel circuit of N-channel type 13th and 14th MOS transistors 64 and 65 into the main body.
Input and output terminals of CMOS circuit and P channel type MOS
A CMOS inverter body consisting of a transistor 67 and an N-channel MOS transistor 68 includes 15th and 16th N-channel MOS transistors 6.
4th CMOS with 9.70 parallel circuits inserted
a second flip-flop element connected to the output and input terminals of the circuit; 17th and 18th P-channel type flip-flop elements connected between the output terminal of the third CMOS circuit and _VDD ;
The MOS transistors 73 and 74 are connected to the fourth
A slave flip-flop which has third and fourth series circuits formed by connecting P-channel type 19th and 20th MOS transistors 75 and 76 in series between the output terminal of the CMOS circuit and _VDD . 42, the input pulse Q ₂ is the 3rd, 4th, 9th, 12th,
14th, 15th, 17th, 19th MOS transistor 4
7, 51, 58, 61, 65, 69, 73, 75
The output signal of the first CMOS circuit is connected to the gate of the first CMOS circuit.
16. The output signal of the second CMOS circuit is applied to the gates of the 13th and 18th MOS transistors 70 and 76.
The output signal of the third CMOS circuit is applied to the gates of the MOS transistors 64 and 74 of the first and seventh MOS transistors.
A fourth transistor is connected to the gates of the transistors 45 and 56.
The output signal of the CMOS circuit is applied to the gates of the sixth and tenth MOS transistors 53 and 59, and the shift control signal S is applied to the gates of the second, fifth, eighth and eleventh MOS transistors 46, 52, 57 and 60. It is configured by supplying each. Next, the operation of the circuit connected as above is explained in the fifth section.
This will be explained using the timing chart shown in the figure. First, an input signal f _IN of 200 MHz is supplied to the binary counter 11 in advance, for example, as in the conventional case. As a result, a 50 MHz signal whose frequency has been sequentially divided by the two binary counters 11 and 12 is input to the input terminal of the binary counter 21. In this state, when the shift signal is "1", the output signal S of the NAND gate 17 is independent of the level of the switching signal.
becomes “1”. Here, in FIG. 4, Q ₂ = “0”, Q ₆ = “1”,
Assume that Q _M =“1” (t ₀ in FIG. 5). S=“1”
At this time, transistors 57 and 60 are turned on, and transistors 46 and 52 are turned off. In this state, next
When Q ₂ changes from “0” to “1”, transistor 61 turns on, and transistor 59 is on because Q ₆ is “1”, so Q _M
changes from “1” to “0”. Therefore, transistor 74 is turned on, but since Q ₂ is "1", transistor 73 is turned off, so
₆ holds “0” and Q ₆ holds “1”. Next, when Q ₂ changes from “1” to “0”, transistor 7
3 turns on, ₆ changes from “0” to “1”,
Since _M changes from "0" to "1" via transistors 45 and 44 when Q ₂ changes to "1", transistor 70 is on, and transistor 68 also changes when ₆ changes to "1". ”, _Q6 changes from “1” to “0”. If the same operation is repeated thereafter, the timing chart as shown in FIG. 5 will be obtained, and therefore the circuit of FIG.
When “1”, 50MHz signal is halved as before.
The frequency will be divided. On the other hand, when a frequency shift request occurs and the shift signal becomes "0", and then the switching signal becomes "0", as in the conventional case, in synchronization with the next rising edge of the Q output signal _Q2 of the binary counter 12, Q of 1-bit shift register 14
The output signal _Q3 becomes "1", and in synchronization with the next rising edge of _Q2 , the output signal ₄ of the 1-bit shift register 15 becomes "0". If it still holds “0” at this time, NAND gate 17
The output signal S becomes "0" for one bit period of _Q2 as shown in FIG. Here, in Fig. 4, Q ₆ = “0”, Q _M = “0”
Assuming that S=“0”, the transistors 57 and 60 that have been on until now are turned off, and the transistors 46 and 52 that have been off until now are turned on.
At this time, transistor 44 is turned on due to Q _M = “0”, and transistor 49 is turned on due to _M = “1”, so even if Q ₂ changes, _M is held at “1” by transistors 46 and 44. , and further Q
_M is held at "0" by transistor 49. That is, when S="0", the master flip-flop circuit 41 maintains the previous state regardless of _Q2 , so the binary counter 21 does not count _Q2 during this period. As a result, the frequency of the output Q ₆ , ₆ of the binary counter 21 is Q ₂
The signal whose frequency is 1 Hz less than the frequency of 50 MHz is divided by 2, that is, 25 MHz - 0.5 Hz, and the frequency of the input signal of the binary counter 21 is shifted. In this way, in the above embodiment, the output signal _Q2 of the binary counter 12 can be directly used as an input to the binary counter 21, so there is no signal transmission delay time caused by the gate as in the conventional case, and therefore, Even if the frequency of the input signal f _IN is made extremely high, there is no risk that the binary counter 21 will malfunction. Also, Q ₂ is binary counter 2
By directly inputting 1, all the circuits shown in FIG. 3 can be implemented as CMOS, and higher integration and lower power consumption can be achieved. FIG. 6 shows another embodiment of the invention. In the embodiments described above, the binary counter 21 was of the fall synchronous type, but in this example, it is of the rise synchronous type. Since this embodiment corresponds in principle to the above-mentioned embodiment, the same reference numerals and dashes will be attached to corresponding parts, and the explanation thereof will be omitted. The feature of this case is that since the data changes at the rising edge of Q ₂ , Q ₂ is supplied to each gate of the N-channel MOS transistors 73' and 75', and the N-channel MOS transistor 4
6', 52' and the gates of P channel type MOS transistors 57', 60' are supplied with S through an inverter 77. In this example circuit, since the binary counter 21 is of the rising synchronization type, the seventh
As shown in the timing chart in the figure, Q _M changes in synchronization with the rise of signal Q ₂ , and Q ₆ changes later than Q _M by half a bit of signal Q ₂ . FIG. 8 shows still another embodiment of the present invention, in which the circuit is simplified. That is, the transistors 45, 46, 47, 51, 52, 53 and 64, 65, 69, 70 are omitted from the binary counter in FIG. That is, the binary counter 21 is an N-channel type MOS
The input and output terminals of a first CMOS inverter consisting of a transistor 43 and a P-channel MOS transistor 44 are connected to an N-channel MOS transistor 4.
9 and a P-channel MOS transistor 50, a first flip-flop element is connected to the output and input terminals of a second CMOS inverter consisting of a P-channel MOS transistor 50;
N-channel type first, second, and third MOS transistors 56, 57, and 58 are connected between the output end of the CMOS inverter and the ground, and N-channel type MOS transistors 56, 57, and 58 are connected between the output end of the second CMOS inverter and the ground. 4th, 5th, and 6th MOS transistors 59, 6 of type
0 and 61 in series, respectively.
Master flip-flop 4 with a series circuit of
The input and output terminals of a third CMOS inverter consisting of 1 and P channel type MOS transistors 62 and N channel type MOS transistors 63 are connected to P channel type MOS transistors 67 and N channel type MOS transistors.
a second flip-flop element connected to the output and input ends of a fourth CMOS inverter consisting of a transistor 68; a P-channel type seventh flip-flop element connected between the output end of the third CMOS inverter and _VDD 8's
The MOS transistors 73 and 74 are connected to the fourth
P-channel type ninth and tenth MOS transistors 75 are connected between the output terminal of the CMOS inverter and _VDD ,
It consists of a slave flip-flop 42 having third and fourth series circuits formed by inserting MOS transistors 58 and 61 in series, respectively, and transmits the input pulse Q ₂ to the third, sixth, seventh and ninth MOS transistors 58 and 61. ,73,75
The output signal of the first CMOS inverter is connected to the gate of the 10th MOS transistor 76, and the output signal of the second CMOS inverter is connected to the gate of the 8th MOS transistor 76.
The output signal of the third CMOS inverter is connected to the gate of the transistor 74 to the first MOS transistor 5.
6, the output signal of the fourth CMOS inverter is connected to the gate of the fourth MOS transistor 59,
The shift control signal S is supplied to second and fifth MOS transistors 57 and 60, respectively. In this case, although it is not a complete CMOS configuration, an operation corresponding to the timing chart in FIG. 5 can be obtained. It goes without saying that the circuit of the binary counter shown in FIG. 6 can be simplified in the same way as the case shown in FIG. 8. As described in detail above, according to the present invention, it is possible to provide a frequency dividing circuit that is capable of high integration, low power consumption, and has an input pulse frequency shifting function that allows high-speed operation.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional frequency divider circuit with an input pulse frequency shifting function, Fig. 2 is a timing chart showing the operation of the circuit, and Fig. 3 is an input pulse frequency according to an embodiment of the present invention. FIG. 4 is a detailed diagram of a part of the above-mentioned embodiment circuit, FIG. 5 is a timing chart showing the operation of the above-mentioned embodiment circuit, and FIG. FIG. 7 is a timing chart of the circuit shown in FIG. 3 having the circuit shown in FIG. 6, and FIG. 8 is a construction diagram of still another embodiment of the present invention. 11, 12, 21...Binary counter, 1
4, 15...1 bit shift register, 16, 1
8...Inverter, 17...Nand gate, 41
...Master flip-flop circuit, 42...Slave flip-flop circuit, 48, 54, 6
6,71...CMOS inverter, 55,72...
flipflop element.

Claims (1)

[Claims] 1. A frequency dividing circuit that divides the frequency of an input pulse, and a first circuit that is supplied with the output of the frequency dividing circuit as a clock and that is supplied with a switching signal whose level is inverted every predetermined period as an input signal. a D-type flip-flop circuit; a second D-type flip-flop circuit to which the output of the frequency divider circuit is supplied as a clock and the output signal of the first D-type flip-flop circuit as an input signal; a gate circuit which is supplied with the output signal of the second D-type flip-flop circuit and a shift signal set to a predetermined level when a frequency shift is requested, and generates a shift request signal whose level is inverted for a predetermined bit period of the input pulse; Connect the input and output terminals of the CMOS inverter to the second
a first flip-flop element connected to the output and input terminals of the CMOS inverter; A fourth, fifth, and sixth MOS transistor of the first channel type are respectively inserted in series between the output terminal of the second CMOS inverter and the first potential supply terminal. 1. A second flip-flop element comprising a master flip-flop having a second series circuit and input and output terminals of a third CMOS inverter connected to output and input terminals of a fourth CMOS inverter; The seventh and eighth MOS transistors of the second channel type are connected between the output terminal of the CMOS inverter No. 3 and the second potential supply terminal;
The third and fourth MOS transistors are each formed by inserting second channel type ninth and tenth MOS transistors in series between the output end of the CMOS inverter and the second potential supply end.
It consists of a slave flip-flop having a series circuit of
The output of the first CMOS inverter is connected to the gates of the seventh and ninth MOS transistors.
The output of the second CMOS inverter is connected to the gate of the eighth MOS transistor, and the output of the third CMOS inverter is connected to the gate of the first CMOS transistor.
A fourth CMOS transistor is connected to the gate of the MOS transistor.
The output of the inverter is applied to the gate of the fourth MOS transistor, and the shift request signal is applied to the gate of the second MOS transistor.
1. A frequency dividing circuit having an input pulse frequency shifting function, comprising a binary counter circuit supplied to each gate of a fifth MOS transistor. 2. a frequency dividing circuit that divides the frequency of an input pulse; a first D-type flip-flop circuit to which the output of the frequency dividing circuit is supplied as a clock and a switching signal whose level is inverted at predetermined intervals as an input signal; a second D-type flip-flop circuit to which the output of the frequency divider circuit is supplied as a clock and the output signal of the first D-type flip-flop circuit is supplied as an input signal; and the first and second D-type flip-flop circuits. A gate circuit is provided with an output signal of the CMOS inverter and a shift signal which is set to a predetermined level when a frequency shift is requested, and which generates a shift request signal whose level is inverted during a predetermined pit period of the input pulse; The input and output terminals of a first CMOS circuit formed by inserting parallel circuits of first, second, and third MOS transistors, and the fourth, fifth, and sixth MOS transistors of the first channel type are connected to the CMOS inverter body. A first flip-flop element formed by connecting the output and input terminals of a second CMOS circuit formed by inserting a parallel circuit of transistors, and between the output terminal of the first CMOS circuit and the first potential supply terminal. the 7th, 8th, and 9th channels of the second channel type.
A first MOS transistor formed by inserting second channel type 10th, 11th, and 12th MOS transistors in series between the output end of the second CMOS circuit and the first potential supply end, respectively; A master flip-flop with a second series circuit and a second channel type 13th and 14th
The input and output terminals of a third CMOS circuit are formed by inserting a parallel circuit of MOS transistors, and the fourth CMOS circuit is formed by inserting a parallel circuit of 15th and 16th MOS transistors of the second channel type into the CMOS inverter body.
a second flip-flop element connected to the output and input terminals of the CMOS circuit; Third and fourth MOS transistors are formed by inserting first channel type 19th and 20th MOS transistors in series between the output end of the fourth CMOS circuit and the second potential supply end, respectively. It consists of a flave flip-flop with a series circuit, and the output of the frequency dividing circuit is applied to the gates of the third, fourth, ninth, 12th, 14th, 15th, 17th, and 19th MOS transistors. , the output of the first CMOS circuit is connected to the gates of the 16th and 20th MOS transistors, and the output of the second CMOS circuit is connected to the gates of the 13th and 18th MOS transistors.
Shift the output of the third CMOS circuit to the gate of the first and seventh MOS transistors, and the output of the fourth CMOS circuit to the gates of the sixth and tenth MOS transistors. The request signal is sent to the second, fifth, eighth, and eleventh
A frequency dividing circuit having an input pulse frequency shifting function, characterized by comprising a binary counter circuit supplied to each gate of a MOS transistor.