JPS623915B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses a timer that turns a switch on (conducting) or off (blocking) for a preset period of time and variably sets the on or off time.

Conventionally, a timer circuit in an LSI (Large Scale Integrated Circuit) for electronic watches consists of a timekeeping circuit, a memory circuit that stores the set time, a coincidence detection circuit that detects whether the times of the above two circuits match, and a coincidence detection circuit that detects coincidence of the times of the above two circuits. It has a flip-flop that inverts the output depending on the output.

In this timer circuit, the following two methods have conventionally been used to control the on-time of the switch and turn it off again after a certain period of time after the switch is turned on.

In addition to the above-mentioned timer circuit, a down counter whose time can be set is provided, and when the remaining time of this down counter reaches "0", the output flip-flop is inverted again.

In addition to the above-mentioned timer circuit, a memory circuit for storing the off time is provided, and when the off time and the measured time match, the output flip-flop is inverted again.

An example of a block diagram of the timer shown in FIG. 1 is shown. Reference numeral 1 denotes a timekeeping circuit that measures normal time. A time memory 2 stores the time at which the timer is turned on. Reference numeral 3 denotes a coincidence detection circuit, which detects coincidence of times between the clock circuit 1 and the time memory 2, starts a down counter 4 whose on time is set, and simultaneously sets a flip-flop 5 for timer output control. The down counter 4 resets the flip-flop 5 when the set time has elapsed after the start of time counting and the remaining time reaches "0".

1 of the block diagram of the circuit shown in Figure 2.
Give an example. 2 ₁ and 2 ₂ are memories for storing the on time and off time of the timer, respectively. The coincidence detection circuit 3 includes a clock circuit 1 and an on-time memory 2.
When the times in the clock circuit ₁ and the off-time memory 22 match, the flip-flop 5 for controlling the timer output is set, and when the times in the clock circuit 1 and the off-time memory ₂₂ match, the flip-flop is reset. Although not shown, the down counter 4, memories 2 ₁ , 2 ₂
It goes without saying that a time setting switch mechanism is provided in the device, etc.

As is clear from these examples, the configuration of , required a down counter or an off-time storage circuit in addition to the usual timer circuit, and had the disadvantage of increasing the number of circuits in the LSI.

The present invention has been developed in view of this problem, and is configured to variably set the on/off time of the timer by selecting the digit of the comparison data.

The present invention will be explained in more detail below using the drawings.

Although FIG. 3 is not the invention, it is a block diagram for understanding the invention. 11 is a normal clock circuit. 12 is a time memory for setting the timer on time. Reference numeral 13 denotes a coincidence detection circuit, which sets the set priority type flip-flop 14 for timer control when the data of all digits of the time memory 12 matches the clock circuit output, and only the digits selected by external input are clocked. When the circuit output matches, the flip-flop 14
Reset.

FIG. 4 shows an example of a circuit that is a more specific version of FIG. 3. 11 ₁ , 11 ₂ , and 11 ₃ are memory sections for 1 minute, 10 minute, and hour digit data of the timekeeping circuit 11, respectively. 12 ₁ , 12 ₂ , and 12 ₃ are memory portions for 1 minute, 10 minute, and hour digit data of the time memory 12, respectively. 15 ₁ , 15 ₂ 15 ₃ are exclusive NOR (coin dent OR) circuits for coincidence detection, and are connected to a clock circuit 11 and a time memory 1, respectively.
"1" when the 1 minute, 10 minute, and hour digit data of 2 match.
Outputs a level signal (high level). Reference numeral 16 is a selection switch, and the on time is varied by selecting the digit to be compared. 17 is an OR gate, which always outputs the "1" level when the switch 16 is connected to the "1" level, and outputs the "1" level when the switch 16 is connected to the "0" level.
When the minute digits match, a "1" level is output.
18 is an AND gate which resets the flip-flop 14 when only the one-minute digit matches when the switch 16 is connected to the "1" level, and when the switch 16 is connected to the "0" level, it resets the flip-flop 14 to a "1" level. When both the minute and tenth digits match, the flip-flop 14 is reset. 19 is an AND gate which sets the flip-flop 14 when all the hour and minute digits match. At this time, the reset input to the flip-flop 14 is also established, but since the flip-flop 14 is of the set priority type, only the set input is valid.

As is clear from the above, when the external switch 16 is connected to the "1" level, the timer will be turned off 10 minutes after the timer is turned on, and when the external switch 16 is connected to the "0" level,
The timer will turn off one hour after it is turned on.
In this way, it is possible to variably set the timer on time using only a few elements without using the counter 4 and memory ₂₂ shown in FIGS. 1 and 2.

FIG. 5 is an example of an implementation circuit according to the present invention. The illustrated adder 21 is a clock circuit 1 which is kept in circulation.
A unit clock pulse is added to the time data of 1, and the addition result is output. The clock circuit 11 has a configuration in which 16-bit shift registers are serially connected.
Contains timekeeping information for hours and minutes. Although not shown, it is a matter of course that a circuit necessary for timekeeping, such as a carry correction circuit, is added to this timekeeping section. Adder 2
2 adds the time setting input to the time memory contents when setting the data contents of the time memory 12,
Output the addition result. Reference numeral 12 denotes a 16-bit time memory similar to the clock circuit 11, in which the contents of the time at which the timer should be turned on are set. 23 is an exclusive NOR circuit, which becomes "1" when the contents of corresponding bits in memories 11 and 12 are equal.
Output the level. 24, 25, and 26 are an OR circuit, a clocked NAND circuit, and a clocked inverter, respectively, and a comparison start signal a (=D ₁ t ₁ )
memory 11, 12 after reaching the "1" level.
While the outputs of 2 and 2 are in agreement, the output b maintains the "1" level. In addition, the clocked NAND circuit 25,
Each clocked inverter 26 has a clock φ
₁ and _φ2 are established, NAND and inverter operations are performed, both of which are well known. The above-mentioned clocked NAND circuit is divided into an AND circuit section and a clocked inverter section connected in cascade thereto. 27 and 28 are 1-bit delay latches. The latch 27 outputs the "1" level at the timing D ₄ t ₂ when all the minute digits match in registers 11 and 12. This means that when all the minute digits in registers 11 and 12 match, the output of the 1-bit shift register consisting of the clocked NAND circuit 25 that holds the output of the exclusive NOR circuit 23 and the clocked inverter 26 _{is D4.} This is because it is “1” at the timing of t ₂ . The output d of the latch 27 is held from the timing of D ₄ t ₂ to the timing of D ₄ t ₁ 4 digits later, so it can be used for output control at an appropriate timing in between, such as timing signal D ₄ t ₃ . Set the flip-flop 14. AND gates 29, 30 and OR gate 31 are inverter 32
When the selection input C is at the "1" level, the timing signal D ₂ t ₁ is supplied as the timing signal to the latch 28, and when the selection input C is at the "0" level, the timing signal D ₃ t ₁ is supplied as the timing signal to the latch 28. When the input C is at the "1" level, the latch 28 outputs the "1" level at timing D ₂ t ₁ when the one-minute digits of the clock circuit 11 and the time memory 12 match, and the input C is at the "0" level. 1 when
When the minute and 10 minute digits match, a "1" level is output at the timing D ₃ t ₁ . This means that when input C is "0" and the 1 minute digit and 10 minute digit of registers 11 and 12 match, the exclusive NOR circuit 2
a clocked NAND circuit 25 that holds the output of 3;
The output of the 1-bit shift register from the clocked inverter 26 becomes "1" at the timing of D ₃ t _1.
, and input C is "1" and register 11
When the digits of 12 and 12 match, exclude
The output of the 1-bit shift register that holds the output of the sibnor circuit 23 is "1" at the timing of D ₂ t _1.
By being. Then, the output control flip-flop 14 is reset for the output e at an appropriate timing, for example _{, D4t3} . Flip-flop 14 is of the set priority type.

In this way, the flip-flop 14 is set when the hour and minute digits of the clock circuit 11 and the time memory 12 match, and is set by the input C after 10 minutes when the input C is at the "1"level; When it is at the "0" level, it is reset after one hour. The switch is driven by the output f of the flip-flop 14. FIG. 6 shows a timing distribution format for explaining the operation of FIG. 5. Moreover, the above φ ₁ ,
_φ2 is a basic timing pulse (clock pulse) corresponding to the bit signal.

The circuit configuration in FIG. 5 includes a first shift register circuit (for example, 11 in FIG. 5) consisting of a loop that holds time data in a circular manner, and a second shift register circuit (for example, 12), one coincidence detection circuit (for example, 23) that sequentially compares the data of the first and second shift register circuits, and an AND circuit (for example, an AND portion of 25) that receives the output of this circuit as an input. ), a 1-bit shift register provided on the output side of this circuit (clocked inverter and clocked inverter 26, which are a part of the clocked inverter 25 in the notation), and a start signal for comparing the output of this shift register and data ( For example, an OR circuit (for example, 24) whose input is D ₁ t ₁ ) and whose output is one input of the AND circuit; a first latch (e.g. 27) that performs a read operation with a timing signal (e.g. D ₄ t ₂ );
A second latch (e.g. 28) whose input is the output of the 1-bit shift register, and a bistable circuit (e.g. 14 ₎ and _a selection circuit (for example _{, 29} -32). In a timer with such a dynamic configuration, compared to a timer with a static configuration as shown in FIG. You only need one piece at a time.

In the above embodiment, the timer on time is divided into two stages, but it is also possible to obtain more stages of the timer on time, for example, by selectively comparing the bit digits obtained by further subdividing the digital pulse. be. Furthermore, although the on-time is varied in the description of the present invention, it is clear that varying the off-time is also included in the gist of the present invention.

As explained above, according to the present invention, the timer on time or off time can be selected with a small number of elements, so it is suitable for LSI implementation.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the configuration of a conventional timer, FIG. 3 is a block diagram for understanding the present invention although it is not related to the present invention, and FIG. 4 is a block diagram showing the same embodiment. A concrete example of the circuit, FIG. 5 is an example of an implementation circuit according to the present invention, and FIG. 6 is a diagram showing a timing distribution format for explaining the operation of FIG. 11...Clock circuit, 12...Time memory, 1
3... Match detection circuit, 14... Flip-flop (bistable circuit), 16... Digit selection switch.

Claims (1)

[Claims] 1. A first shift register circuit consisting of a loop that cyclically holds time data, a second shift register circuit consisting of a loop that cyclically holds set time data, and data in the first and second shift register circuits. One coincidence detection circuit that sequentially compares, an AND circuit that receives the output of this circuit as input,
A 1-bit shift register provided on the output side of this circuit, an OR circuit which inputs the output of this shift register and a start signal for data comparison, and whose output is one input of the AND circuit, and the 1-bit shift register. a first latch that receives the output of the shift register as an input and performs a reading operation based on the end timing signal of the hour and minute digits of time data; a second latch that receives the output of the 1-bit shift register as an input; A bistable circuit that is stabilized in one direction by the output of the latch and stabilized in the other by the output of the second latch, and a comparison end signal of the 1 minute digit and 10 minute digit of the time data is selectively transferred to the data of the second latch. A timer characterized by comprising a selection circuit that provides a reading signal.