JPS6239560B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-density multilayer wiring board for LSI mounting used in electronic devices such as computers.

Conventionally, in the manufacturing method of this type of multilayer wiring board, a pattern is formed two-dimensionally on the surface of a smooth substrate or an insulating layer by a thick film method or a thin film method to form multiple layers. For this reason, the pattern packaging density is naturally limited in terms of pattern line width and pattern spacing (pitch) from an electrical standpoint such as crosstalk or migration, and from an area standpoint. This has the disadvantage that it is extremely undesirable from the standpoint of high-density integration of patterns.

An object of the present invention is to form grooves in an insulating layer with predetermined dimensions on the surface of a substrate or an insulating layer, and to form wiring patterns on the side surfaces of these grooves by a thin film method. That is, the object of the present invention is to provide a method for manufacturing a high-density multilayer wiring board that eliminates the above-mentioned drawbacks by forming a three-dimensional pattern and forming multiple layers.

The manufacturing method of the present invention includes a first step of forming grooves in the insulating layer so that predetermined pattern grooves are formed on the surface of the heat-resistant insulating substrate; a second step of forming a metal thin film by vapor deposition or sputtering; a third step of applying a photoresist to the surface of the metal thin film; and oblique irradiation of light through a mask having a desired pattern on the photoresist. a fourth step of exposing and developing to remove the photoresist on the side surface portions of the insulating layer; a fifth step of plating the removed photoresist portions with metal; a sixth step of peeling off and etching the resist and the metal thin film; a seventh step of forming an insulating layer on the entire surface of the substrate other than the desired portion of the metal plating;
The eighth step of forming a VIAFILL conductor is repeated at least once to form a multilayer structure.

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIGS. 1 to 8 show cross-sectional views of the process for manufacturing the high-density multilayer wiring board of the present invention. Further, FIG. 9 shows a comparison of the degree of integration per layer between the high-density multilayer wiring board of the present invention and a conventional plane mounting board.

Figure 1 shows a heat-resistant insulating substrate 1 whose main component is alumina (Al ₂ O ₃ ), and a dielectric material whose main component is glass, alumina, etc., is insulated in advance so that grooves are formed as designed. A state in which layer 2 is formed is shown.
In fact, the shape of this groove determines the line width and pitch of the pattern. In other words, sufficient design is required because the degree of high-density integration is determined.
The insulating layer 2 can be easily formed by a screen printing method using an insulating paste.

Figure 2 shows that Ti (titanium) and Cu are deposited on the entire surface of Figure 1 by vapor deposition or sputtering.
(copper), Pd (palladium), Mo (molybdenum), Ni
(nickel), W (tungsten), Al (aluminum), etc. alone or in combination of two or more,
A metal thin film 3 with a thickness of 500 Å to 10,000 Å is formed as a plating base metal to be described later, and a photoresist 4 is formed on it.
Shows the state in which it has been applied.

FIG. 3 shows a mask 5 so that a predetermined area is exposed on the surface of the photoresist 4.
A state in which light energy 6 is irradiated through is shown. As a feature of the present invention, since the pattern is formed on the side surface of the insulating groove, the irradiation angle of the light energy 6 is determined by the shape of the groove. Assuming that the base of the groove cross section is a, the height is b, and the angle of light energy irradiation with respect to the base is θ, the following equation (1) is given.

tanθ=a/b...(1) This takes advantage of the straightness of light, and the mask 5
The position of the pattern with respect to the substrate is determined from the relationship with the gap. That is, the larger the gap, the farther away it is from the normal position. Letting l be the deviation of the groove cross section from the side surface, d be the gap between the mask 5 and photoresist 4, and θ be the irradiation angle of the light energy, the following equation (2) is given.

l=d/tanθ (2) In the embodiment, a region 7 irradiated with light energy 6 is shown using a positive type photoresist 4. FIG. 4 shows the formation of a portion 8 in which the irradiated area 7 has been removed by development. By performing exposure and development twice, both sides of the groove are removed.

FIG. 5 shows that the portion 8 from which the photoresist has been removed is filled with Au (gold), Cu (copper), Ni (nickel), and Pd.
This shows a state in which partial plating 9 is applied using a metal such as (palladium) alone or in combination of two or more.

FIG. 6 shows a state in which the photoresist 4 and the metal thin film 3 other than the partial plating 9 are removed by peeling and etching, and a pattern 10 is formed. By this step, the shape of one layer of wiring pattern is completed. As can be seen from FIG. 6, it has a structure similar to that of a conventional wiring pattern, and close contact with the insulating layer 2 is achieved.

FIG. 7 shows a state in which the first insulating layer 11 is formed so that predetermined through holes 12 in the pattern 10 pass through. Here, there is no problem even if the first insulating layer 11 does not enter the inside of the groove. On the contrary, it is better to prevent crosstalk and migration from occurring. But the first
Since the surface of the insulating layer 11 is multilayered, it may be considered that the surface of the insulating layer 11 is polished or the like to reduce unevenness.

FIG. 8 shows Au (gold) in the through hole 12.
A state in which a via fill conductor (VIAFILL) conductor 13 such as Ag/Pd (silver/palladium) is formed is shown. If the via fill conductor is formed a little thicker from the surface of the first insulating layer 11, there will be no problem with electrical contact for subsequent multilayering.

Let us now consider a comparison of the degree of integration per layer between the high-density multilayer wiring board of the present invention and a conventional multilayer board.
As explained above with reference to FIG. 6, in the shape of the wiring pattern of the present invention, the width in the vertical direction corresponds to the line width of the conventional pattern, and the width in the horizontal direction corresponds to the film thickness.

FIG. 9 shows a comparison of pattern mounting densities per layer when the cross-sectional areas of the wiring patterns are the same, in other words, the conductor resistances are the same. From FIG. 9, when the pattern line width is 40 μm and the pattern spacing is 40 μm, the degree of integration per layer is about 1.8 times that of the conventional wiring board mounting. However, the film thickness is 5μ for both.
It was assumed that

As explained above, the present invention forms wiring patterns on both sides of the groove in the insulating layer, so it has an extremely high density compared to the conventional plane mounting wiring board, and also has electrical problems such as crosstalk and migration. This has the effect of making it possible to manufacture a high-density multilayer wiring board with few defects.

[Brief explanation of the drawing]

1 to 8 are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 9 is a diagram showing the effects of the present invention. In the figure, 1... heat-resistant insulating substrate, 2...
...Insulating layer, 3...Metal thin film, 4...Photoresist, 5...Mask, 6...Light energy, 7...Irradiation area, 8...Removed portion, 9...Partial plating, 10... ...Pattern, 11...First insulating layer, 1
2... Through hole, 13... Via film conductor.

Claims (1)

[Claims] 1. A first step of forming an insulating layer on the surface of a heat-resistant insulating substrate so that predetermined pattern grooves are formed, and forming a metal thin film by vapor deposition or sputtering on the surface of the heat-resistant insulating substrate and the surface of the insulating layer. a second step of applying a photoresist to the surface of the metal thin film; and a third step of applying a photoresist to the surface of the metal thin film, and irradiating the photoresist with oblique light through a mask having a desired pattern to form a side surface of the groove in the insulating layer. exposure to remove the photoresist,
a fourth step of developing, a fifth step of metal plating the removed photoresist portion, a sixth step of peeling off and etching the photoresist and metal thin film other than the metal plating portion, and the metal plating. The seventh step of forming an insulating layer on the entire surface of the substrate other than the desired portion, and the eighth step of forming a via fill conductor on the desired portion of the metal plating are repeated at least once to form a multilayer structure. A method for manufacturing a high-density multilayer wiring board.