JPS6239569B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binary counting circuit having the simplest configuration.

Binary counting circuits are used in digital transmission systems, etc.
It is often used in signal processing that counts two pulses and outputs one pulse. 2 like this
Conventionally, a base counting circuit constructed using two flip-flops has been widely used.

FIG. 1 is a circuit diagram showing the configuration of such a conventional counting circuit. In the figure, 1 is an input terminal,
2 and 3 are D-type flip-flops, 4 is a NOR circuit, 5 is a capacitor, 6 is a resistor, 7 is an OR circuit, 8 is an output terminal, and 9 is a reset input terminal.

Further, FIG. 2 is a time chart showing signals of various parts in the circuit of FIG. 1. In the figure, A is the input signal a at terminal 1, B is the output signal b from the Q terminal of flip-flop 2, C is the output signal c from the same terminal, D is the output signal d from the terminal of flip-flop 3, and E is the output signal from the NOR circuit 4. Output signals e and F are the output side signal f of the capacitor 5, G is the output signal g of the OR circuit 7, and H is the reset input h of the terminal 9.

Prior to the start of counting in the circuit of FIG. 1, a reset input h is applied to terminal 9 (H of FIG. 2). As a result, the Q output of flip-flop 2 becomes low level, the output of flip-flop 2 becomes high level, and the output of flip-flop 3 becomes high level (FIG. 2B, C, D). Next, when two pulses a ₁ and a ₂ are sequentially given as the input signal a at the terminal 9, the first pulse a ₁ causes the Q output of the flip-flop 2 to go high, and the output goes low (the second Figures A, B, C). Next, when the second pulse _a2 is input, the Q output of flip-flop 2 becomes low level, the output becomes high level, and at the same time, the output of flip-flop 3 also becomes low level (Fig. 2 A, B, C, D). . As a result, the output e of the NOR circuit 4 changes from low level to high level (Fig. 2E). The capacitor 5 and the resistor 6 form a differential circuit, and a differential waveform is generated on the output side of the capacitor 5 by the rise of the output e (FIG. 2F). OR circuit 7
shapes this differential waveform to generate a pulse signal g having the same pulse width as the input signal (FIG. 2G).

In this way, the counting circuit shown in FIG. 1 is initialized by applying a reset input every time counting starts, so that it can count two pulses and count one pulse.
generates pulses.

However, the counting circuit shown in Figure 1 has two flip-flops as well as a NOR
It requires one circuit, one differential circuit, and one OR circuit, resulting in a complicated configuration and an increase in price.

The present invention aims to eliminate these drawbacks of the prior art, and its purpose is to provide a counting circuit that has a simpler configuration and is capable of counting two pulses and outputting one pulse. There is a particular thing. In order to achieve this purpose, in the counting circuit of the present invention,
In a counting circuit that counts two input pulses and generates one pulse with the same time width as the input pulse, there is a flip-flop circuit that inverts the output state at each change point in the same direction of the input signal pulse, and an input signal pulse. a delay circuit that delays the flip-flop circuit by a time longer than the delay time of the flip-flop circuit; and a delay circuit that fixes the output when the flip-flop circuit is in one output state and adjusts the output pulse of the delay circuit when the flip-flop circuit is in the other output state. It is characterized by comprising a gate circuit that outputs a corresponding pulse.

Examples will be described below.

FIG. 3 is a circuit diagram showing the configuration of one embodiment of the counting circuit of the present invention. In the figure, 11 is an input terminal, 12 is a D-type flip-flop, 13, 14,
15 and 16 are NOR circuits, 17 is an output terminal, 18
is the set input terminal.

Further, FIG. 4 is a time chart showing signals of various parts in the circuit of FIG. 3. In the same figure, A
is the input signal a, B is the output signal b of the NOR circuit 15, C is the output signal c of the terminal of the flip-flop 12, and D is the output signal d of the NOR circuit 16.

In the circuit shown in FIG. 3, by applying a set input for initialization to terminal 18, the output c of flip-flop 12 is initially set to a low level. In this state, when two pulses a ₁ and a ₂ are sequentially applied to the input terminal 11 as the input signal a, the first pulse a ₁ causes the output c of the flip-flop 12 to go high, and the second pulse Due to a ₂ , the output c becomes low level again (FIG. 4C). At this time, the change in state in the flip-flop 12 has a delay time τ ₁ compared to the input signal a.

On the other hand, the input signal a is the NOR circuit 13, 14, 1
5 to produce an inverted signal b having the same pulse width. Two pulses in input signal a
Output pulses b ₁ and b ₂ are generated by a ₁ and a ₂ , but each
Based on the delay of the NOR circuit, the output pulses b ₁ , b ₂
are the respective delay times τ compared to the input pulses a ₁ and a ₂
It has ₂ . The NOR circuit 16 integrates the output c of the flip-flop 12 and the output b of the NOR circuit to generate an output signal pulse d. At this time, the output pulse d
appears only for output pulse b ₂ and does not appear for output pulse b ₁ . At this time, by selecting the delay time τ ₁ <τ ₂ , the pulse width of the output signal d becomes equal to that of the input signal a. The circuit shown in FIG. 3 thus operates as a counting circuit that counts two input pulses and produces one output pulse of the same pulse width as the input pulses.

In this way, by using the circuit according to the embodiment of the present invention shown in FIG. 3, it is possible to more easily realize a counting circuit that generates one output pulse from two pulse inputs. . In this case, the required components are one flip-flop in the case of Figure 3;
It is extremely effective because it requires only four NOR circuits and is much simpler than the conventional circuit shown in FIG.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the configuration of a conventional counting circuit.
2 is a time chart showing the signals of various parts in the circuit of FIG. 1, FIG. 3 is a circuit diagram showing the configuration of an embodiment of the counting circuit of the present invention, and FIG. 4 is a time chart showing the signals of each part of the circuit of FIG. 3. This is a time chart. 1... Input terminal, 2, 3... D-type flip-flop, 4... NOR circuit, 5... Capacitor, 6... Resistor, 7... OR circuit, 8... Output terminal, 9... Reset input terminal, 11... Input terminal, 12... D-type flip-flop, 13, 14, 15, 16...NOR
Circuit, 17...output terminal, 18...set input terminal.

Claims (1)

[Claims] 1. In a counting circuit that counts two input pulses and generates one pulse with the same time width as the input pulse, there is a flip circuit that inverts the output state at every change point in the same direction of the input signal pulse. a flop circuit; a delay circuit that delays an input signal pulse for a time longer than the delay time of the flip-flop circuit; A counting circuit comprising: a gate circuit that outputs a pulse corresponding to the output pulse of the delay circuit.