JPS623957B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a display information erasing method in a display device using an AC-driven plasma display panel.

AC-powered plasma display panels are
As is already well known from various literatures, a plurality of X electrodes and Y electrodes supported on a pair of glass substrates are each covered with a dielectric layer and placed facing each other, and discharge gas is injected into the facing gap. It has a configuration in which a matrix arrangement of discharge cells is defined at each electrode intersection point. An X-side write voltage supply circuit, a Y-side write voltage supply circuit, an X-side sustain voltage supply circuit, and a Y-side sustain voltage supply circuit are connected to the X electrodes and Y electrodes, which are orthogonal to each other, respectively, and are connected to the By applying a half-selective write voltage to the selected X and Y electrodes, the combined selective write voltage is applied to the selected discharge cell at the intersection of these electrodes, thereby generating a first discharge spot and an associated wall charge. Thereafter, discharge accompanied by the generation of wall charges continues due to sustain voltage pulses applied alternately from the X-side and Y-side sustain voltage supply circuits, and the display information is maintained.

On the other hand, in order to erase information displayed in the form of discharge spots as described above, a narrow erase pulse voltage is applied to the discharge cells to cause an erase discharge, and a new wall is created. It is common to use a method in which the erasing pulse is caused to fall before charges are formed, thereby causing the existing wall charges to disappear in the gas space. Conventionally, as an erasing method using such a narrow erasing pulse, one of the methods related to the discharge cell to be erased is as described in "Nikkei Electronics" November 3, 1975 issue, pages 58 to 76. A selective sustain voltage pulse is applied from the electrode to selectively reverse the polarity of the wall charge of the cell corresponding to the electrode containing the discharge cell to be erased, and in this state, the other electrode related to the discharge cell to be erased is A so-called inversion erasing method has been used in which selective erasing is performed by applying a narrow erasing pulse at a sustain voltage level. This conventional inversion erasing method allows the erasing operation to be performed by manipulating the voltage at the sustain voltage level, so it has a higher operating margin than a method that performs selective erasing by simply arithmetically combining the half-selective voltages of the X and Y electrodes. However, on the other hand, it is necessary to configure the sustaining voltage supply circuit, which may be common to each of the X and Y electrodes, to be addressable. It is difficult to avoid the maintenance voltage supply circuit becoming more complicated.

Here, the present invention is based on the above-mentioned inversion erasing method, and uses a selective sustaining voltage for inverting the polarity of wall charges in advance and a narrow erasing pulse at the sustaining voltage level to generate a discharge to be erased. It is intended to provide the most efficient and economical method for selectively supplying the X and Y electrodes associated with a cell.

According to this invention, in order to achieve such an object,
Focusing on the fact that the write voltage supply circuit is configured to be able to address individual discharge cells, the selection operations of the write voltage supply circuit and the sustain voltage supply circuit are combined to provide the required inversion for the discharge cells to be erased. A new erasing method is proposed that adds an erasing operation. More specifically, in this invention, when a sustain voltage pulse for wall charge reversal is supplied from a single sustain voltage supply circuit on one electrode side, a write voltage supply circuit on the other electrode side supplies a sustain voltage pulse to an unselected cell. When supplying a pulse voltage for inversion cancellation that cancels out the reversal effect of , and subsequently supplying a narrow erase voltage pulse from the sustain voltage supply circuit on the other electrode side, the write voltage supply circuit on the opposite electrode side. A selective sustaining voltage pulse and a subsequent erasing pulse are effectively applied to the discharge cells to be erased by supplying an erasing canceling pulse voltage that cancels the erasing effect to non-selected cells. This is a characteristic feature. By adopting such a new erasing method, the cell selection operation by the sustain voltage supply circuit alone becomes unnecessary, and the inversion erasing method can be realized with a simple circuit configuration.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing an example circuit configuration of a plasma display device for carrying out the erasing method according to the present invention, and shows a part of a plasma display panel (PDP) 10, its X side drive circuit 20, and its Y side. A portion of the drive circuit 30 is shown.
The X-side drive circuit 20 has address driver units 21, 22, and 23 shown as representatives, and each unit has, for example, 16 line drivers XD each corresponding to one of the X electrodes X1 to Xn.
01 to XD16 and shift registers SRX1 to SRX3 for addressing these line drivers
Contains. Here each line driver XD above
01 to XD16 are composed of two transistors Qu, Qd, diodes _D1 , _D2 , and a resistor R as shown in Fig. 2, and have an input terminal I that receives an address signal from the shift register SRX, and each electrode of the PDP. The output terminal 0 is connected to the output terminal 0 to supply a driving voltage, and the terminals LH and LG are connected to the two high and low voltage pulse supply lines XLH and XLG. High level side pulse supply line XLH
is a transistor Qw for writing voltage pulse generation.
and the down-side transistor Qsd of the X-side sustaining voltage supply circuit XSU and the canceling pulse generation transistor Qec are connected. In addition, the low level side pulse supply line XLG has an X side maintenance voltage supply circuit.
The up-side transistor Qsu of XSU is connected to two clamping transistors Qcg and Qcs.

On the other hand, the Y-side drive circuit 30 is also provided with address driver units 31 and 32 including line drivers YD01 to YD16 and address shift registers SRY1 and SRY2, respectively, as on the X side. In addition, the high level side pulse supply line YLH of each line driver has a Y side maintenance voltage supply circuit.
The down side transistor Qsd' of YSU and the transistor Qec' for generating cancellation pulses are connected, and the sustain voltage up side transistor Qsu' and the ground clamping transistor Qcg' are connected to the low level side pulse supply line YLG. There is.

In the circuit configuration as described above, an information write operation will first be described prior to an information erase operation according to the present invention. For example, if information is to be written to a cell at the intersection of electrodes X16 and Y16, the voltage waveform of VXa in Figure 3 is applied to the selection electrode x16 on the X side, and the voltage waveform VXa in Figure 3 is applied to the selection electrode y16 on the Y side. Add a voltage waveform. At this time, voltage waveforms such as VXna and VYna are applied to each non-selected electrode on the X side and the Y side, respectively. In this Figure 3, the sustaining voltage pulses Psx, which are applied alternately to the X-side and Y-side electrodes,
Psy is the sustaining voltage generating circuit XSU and
It was generated by YSU. Following the application of the X-side sustaining voltage pulse Psx, the selection electrode 16
The normally on transistor Qd in the line driver XD16 connected to the write power supply Vw is selectively turned off by the address signal from the shift register SRX1, and at the same time, the transistor Qw connected to the write power supply Vw is turned on. As a result, the selected X electrode x16 has a high level side pulse supply line XLH and a line driver.
A write pulse Pw at the write voltage level Vw is applied through the boosting transistor Qu of the XD16, and during this time the remaining unselected X electrodes are clamped to the sustaining voltage level Vs by the clamping transistor Qcs. On the other hand, in accordance with such selection operation on the X side, in the line driver YD16 connected to the selection electrode y16 on the Y side, the transistor Qd is selectively turned on by the address signal from the shift register SRY1. The selection electrode is clamped to the ground potential through the pulse supply line YLG and the ground clamping transistor Qcg'. During this time, the unselected Y electrode is a transistor.
It is held at a sustaining voltage level by Qec'. Thus, the cells at the intersections of these selected and non-selected electrodes have [Xa・Ya], [Xa・Yna] and [Xna・
Combined voltage waveforms as shown in [Ya] and [Xna/Yna] are added, and a discharge based on the address information will occur in the selected cell.

Now, the present invention relates to an operation for erasing the information written as described above, and the procedure will be explained below in connection with FIG. 4. Referring to FIG. 4, the erasure period TE is divided into two periods T1.
and T2, and in the first period T1, a wall charge reversal pulse Pts is applied to all the selected and non-selected electrodes Ya, Ynab on the Y side, and at the same time, a pulse Pts for wall charge reversal is applied to the non-selected electrode Xna on the X side. Add pulse Ptc to cancel the pulse. Here, the wall charge reversal pulse Pts is generated from the Y-side sustaining voltage generation circuit YSU in FIG.
Commonly applied to electrodes. In addition, the inversion canceling pulse Ptc is supplied to the transistor Qec connected to the high level side pulse supply line XLH via the up side transistor Qu of the line driver connected to the non-selected electrode Xna on the X side. can be added selectively with . However, the voltage level may be changed as long as it cancels out the inversion effect of the inversion pulse Pts. In this way, a pulse for wall charge reversal is applied to the cells on the selected
Pts is added, but the effect of the inversion pulse is canceled in the remaining cells.

In the next period T2, a narrow erase pulse Pes is applied to all the selected and unselected electrodes on the X side, and at the same time, an erase cancellation pulse Pec is applied to the unselected electrodes Yna on the Y side. In the case of the present invention, the erase pulse Pes is commonly applied from the X-side sustaining voltage supply circuit XSU shown in FIG. In addition, the pulse for canceling the erasure
Pec is the transistor of the high level side pulse supply line YLH through the up side transistor Qu of the line driver connected to the Y side non-selected electrode Yna.
It is selectively applied with a voltage Vs at a maintenance level from Qec'. In this way, the narrow erase pulse Pes from the X side is applied to each cell on the selected Y electrode Ya to which the erase cancellation pulse Pec is not applied, but among these cells, the wall charges have been reversed by the above first stage operation. As a result, the erase operation is performed only in the cell at the selected electrode intersection of [Xa and Ya].

In addition, in the erasing operation shown in FIG. 4 above, the period T2
Since the erasure cancellation panel Pec applied to the unselected Y electrode Yna during this period is supplied through the relatively high impedance transistor Qu of the line driver, the rise is gradual, and this pulse causes a sustain discharge. In cells [Xna/Yna] at non-selected electrode intersections, the amount of wall charge generated tends to decrease. Therefore, it is preferable to prevent the sustaining discharge caused by such an erase canceling pulse, and for this purpose, a discharge blocking pulse Pds is applied to the non-selected X electrode Xna as shown by the broken line in FIG. 4 during the second stage operation period T2. is desirable. This discharge blocking pulse Pds is applied to the power supply through the line driver on the X side.
It can be selectively supplied from the transistor Qec connected to Vs, thereby canceling out the effect of the erase cancellation pulse on unselected cells. Moreover, this discharge blocking pulse Pds is applied during the first stage period T1.
may be added as a continuous single wide pulse to the inverted cancellation pulse Ptc applied to the unselected X-electrode Xna.

As is clear from the above description, according to the present invention, the inversion erasing method can be achieved using the address function of the write voltage supply circuit without providing the sustain voltage generation circuit with an address function.
The circuit configuration can be made extremely simple and economical. In this case, it may be possible to apply an erase pulse directly from the line driver to the selected electrode or cell to erase.
The erase pulse is required to have a rapid rise,
In order to supply such pulses, the line driver requires a high-speed, high-voltage transistor with low output impedance, which makes it difficult to integrate the circuit. In this regard, according to the erasing method of the present invention, the line driver is used simply to generate a pulse that cancels the erasing effect of the narrow erasing pulse on non-selected electrodes, so the rise is gradual, and therefore high Integration with high packaging density is possible using a line driver with an output impedance.

Note that the essence of this invention is not limited to the embodiments described above with reference to the drawings.
Various other modifications are possible. For example, in the circuit configuration of FIG. 1, a single sustaining voltage generating circuit is provided for all electrodes, but it may be divided into a plurality of circuits in order to distribute the load. Further, the write voltage supply circuit is not limited to the configuration in which the line driver is addressed by a shift register as shown in the figure, but may be configured by appropriately combining a drive circuit with a resistor-diode matrix configuration, a decoder, etc.

[Brief explanation of the drawing]

FIG. 1 shows one of the driving circuits of a plasma display device used to achieve the erasing method of the present invention.
FIG. 2 is a diagram showing the circuit configuration of the line driver, FIG. 3 is a waveform diagram for explaining the write operation, and FIG. 4 is for explaining one embodiment of the erase operation according to the present invention. FIG. 20: X side drive circuit, 21-23: Address driver unit, XD01-XD16: Line driver, SRX1-SRX3: Shift register,
XSU: X-side sustaining voltage supply circuit, 30: Y-side drive circuit, YSU: Y-side sustaining voltage supply circuit, Pts: Wall charge reversal pulse, Ptc: inversion cancellation pulse,
Pes: Erase pulse, Pec: Erase cancellation panel,
Pds: Discharge blocking pulse.

Claims (1)

[Claims] 1. A plasma display panel having a configuration in which a plurality of X electrodes and Y electrodes, each covered with a dielectric layer, are arranged facing each other with a gas-filled space in between so as to define discharge cells at their respective intersections. A method for erasing displayed information, which comprises (a) supplying a pulse voltage for wall charge reversal to all of the Y (or X) electrodes from a Y-side sustaining voltage supply circuit connected thereto; or Y) the wall charge reversal pulse is applied to the X electrodes excluding at least one electrode associated with the discharge cell to be erased among the electrodes through an addressable X side write voltage supply circuit connected to those X electrodes; (b) an X-side sustaining voltage supply circuit connected to all of the X (or Y) electrodes; At the same time, an addressable electrode connected to the Y (or X) electrodes other than at least one electrode related to the discharge cell to be erased among the Y (or NaY
a second step of selectively supplying an erase cancellation pulse voltage for canceling the erase effect of the erase pulse through a side write voltage supply circuit;
A method for erasing display information on a plasma display device, characterized by adding two steps of operations.