JPS6239866B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a pulse trio detection circuit.

The pulse trio is a pulse train that is made up of three pulses (positive electrode, negative electrode, and positive electrode) and is sent out continuously in the RZ method, and is used for fault point location in the PCM relay transmission method using bipolar signals. Then, when locating the fault point of the transmission line, as shown in Figure 1, pulse trios are sent from the monitoring station _T1 to the E-W transmission line by reversing the polarity of every _n set (negative pole - positive pole - negative pole).
Send. Then, at each relay station, the low frequency component is sent back via an intervening line _L1 via a bandpass transmitter having frequencies _f1 , . . . , _fi , which are specific to each relay station. For example, when the frequency f ₁ is returned from the first relay station, the monitoring station T ₁ can thereby know that the pulse trio signal has been transmitted to the first relay station. Next, the pulse trio is sent out with the polarity reversed every n ₂ sets, and if the low frequency current of frequency f ₂ is returned from the second relay station, the signals up to the second relay station are normal. Then, low frequency f is applied to the pulse trio whose polarity is reversed for each n _i side.
When there is no return of _i , the i-th relay station is determined to be a failure. Due to the above, E-
Although it is possible to locate faults on the W transmission line, in order to locate faults on the W-E transmission line, it is _necessary to
A pulse trio signal must be sent to the transmission line. Therefore, it is necessary to have a maintenance person stationed at the receiving end station T ₂ or to visit the receiving end station in the event of a failure.
This has become a bottleneck for unmanned _T2 . It is also possible to provide a control line between the monitoring station _T1 and the receiving end station _T2 , and to connect the E-W transmission line back to the W-E transmission line at the receiving end station _T2 using the control line. However, in this case, extra control lines etc. are required. It is desirable that the receiving end station _T2 detects the pulse trio signal itself and uses this to loop back the transmission path, but the pulse trio signal train is not a constant pulse train, but has polarity inversion as described above. This method has not been put into practical use yet because it is impossible to detect a pulse trio signal train with a fixed pattern because the pulse trio signal train is transmitted with different inversion cycles.

SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, an object of the present invention is to provide a pulse trio detection circuit that can perform loopback of a transmission path by detecting a pulse trio sent from a monitoring station.

The pulse trio detection circuit of the present invention separates a pulse train of a bipolar signal into a positive pulse and a negative pulse, and generates a first signal train corresponding to the inverted state of the positive pulse and a second signal train corresponding to the inverted state of the negative pulse. a polarity separation circuit that outputs a signal train; and a clock pulse generation circuit that outputs a clock pulse train that is a binary pulse train corresponding to each pulse of the input bipolar signal and is delayed by approximately 1/2 the width of the input pulse. , a three-stage shift that outputs the logic state of the first signal train at the time when the first signal train is inputted and the clock pulse is inputted to a first stage output terminal, and is shifted every time the clock pulse is inputted. register and one of the shift registers
a first AND circuit to which the output terminals of the first and third stages, the negative output terminal of the second stage, and the second signal string are input; the negative output terminals of the first and third stages of the shift register; a second AND circuit into which the second stage output terminal and the first signal train are input; and the output of the first AND circuit is connected to the clock input terminal, and the output of the second AND circuit a first counter to be reset; and a first counter to be reset;
a second counter whose output of the AND circuit is connected to a clock input terminal and which is reset by the output of the first AND circuit; and an OR circuit which receives the outputs of the first counter and the second counter. It is characterized by having the following.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. That is, for example, the input signal A from the E-W transmission line is separated and extracted into a positive polarity pulse and a negative polarity pulse by the polarity separation circuit 1, and the respective negative signals B (first signal string) and C ( (second signal string) is input to the input terminal D of the three-step shift register 5 and the first AND circuit 6, respectively. The signal B is also input to the second AND circuit 7. For example, when input signal A is a pulse trio signal as shown in FIG. 3a, signals B and C become as shown in FIGS. b and c, respectively. On the other hand, the signals B and C are converted through the adder circuit 2 and the inverter circuit 3 into a signal A' whose logic state becomes "1" in response to either positive or negative input pulses, as shown in FIG. 3 a'. , a signal further delayed by approximately 1/2 of the pulse width via delay circuit 4.
D' (see FIG. 3 d') is applied to the clock terminal CLK of the shift register 5. The signal D' is used as a clock pulse. In this embodiment, the adder circuit 2, the inverter circuit 3, and the delay circuit 4
This constitutes a clock pulse generation circuit. The shift register 5 outputs the logic state of the terminal D at the time of input of the clock pulse D' to the terminal 1Q, and sequentially outputs the logic state to the terminals 2Q and 3Q by shifting the logical state by one step each time the clock pulse D' is input.
Further, terminals 1, 2, and 3 are terminals that output the aforementioned negative signals, respectively. It is assumed that the output signals of terminals 1Q, 2Q, 3Q, 1, 2, and 3 of the shift register 5 are E, F, G, . . . , respectively. The above-mentioned signal C and the above-mentioned signals E, . The inputs of the second AND circuit 7 are the aforementioned signals B and F,
is input and its output is connected to the clock terminal CLK of the second counter 9 and the reset terminal R of the first counter 8. Then, the output signals of the counters 8 and 9 are outputted as a pulse trio detection signal J via an OR circuit 10. Since the pulse trio detection signal J is a signal that is inverted every time a certain number of sets of pulse trio signals are counted, as will be described later,
For example, by detecting a predetermined number of inversions within a predetermined time using an auxiliary detection circuit (not shown), it is possible to know that the pulse trio signal has been sent and to perform loopback connection of the transmission line. By increasing the number of bits in the counters 8 and 9, it is possible to detect a pulse trio signal using the output signal J without using an auxiliary detection circuit.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 and 3. When a pulse trio signal as shown in FIG. 3a is input to the polarity separation circuit 1, it is separated into a positive pulse and a negative pulse, and correspondingly signals B and C as shown in FIG. 3b and c are generated. is output. On the other hand, when a clock pulse train D' delayed by approximately 1/2 of the pulse width from each input pulse as shown in FIG. 3 d' is input to the clock terminal CLK of the shift register 5, As shown in FIG. 3e, a signal E having the same logic state as the logic state of the terminal D at the time of input is outputted to the terminal 1Q every time the clock pulse D' is inputted, as shown in FIG. 3e. The logic state of shift register 5 is then shifted by one step for each clock pulse D' input to terminals 2Q and 3.
Q is sequentially output. Therefore, Fig. 3 f and g
Signals F and G as shown in are output, respectively. Therefore, since each input signal of the first AND circuit 6 is the above-mentioned signals C, E, , G, its output signal H is a negative pulse of the first pulse trio, as shown in FIG. It is output from the trailing edge to the rising edge of the third clock pulse D', and is in a non-output state thereafter. Then, the second counter 9 is reset by the output signal H. Next, the output signal I of the second AND circuit 7 is
As shown in , the signal is output during the period in which the logic states of the signals F, , and B are all "1". That is, it is output for a period from the trailing edge of the second positive pulse of each pulse trio to the leading edge of the first positive pulse of the next pulse trio. In other words, the signal I is
This is a pulse train in which one pulse is output every time one set of pulse trio signals is completed. The pulses of the signal I are counted by a second counter 9, and the output state of the counter 9 is inverted every time a certain number is counted, and an output signal J is outputted via an OR circuit 10. Although FIG. 3J shows a state in which the pulse is inverted every two pulses, it goes without saying that if the number of bits in the counter 9 is increased, the inversion occurs every time the corresponding number of pulses is counted, for example, ^2.sup.n. As described above, the operation of inverting the logic state of the signal J is repeated in accordance with the number of received pulse trios.

Next, when the polarity of the pulse trio is reversed and a negative-positive-negative pulse trio train is received, the output of signal I is now shifted from the trailing edge of the first positive pulse by the same operation as described above. By the leading edge of the third clock, the logic state "1" is reached and the first counter 8
After that, the logic state of the signal H becomes "1" at the end of each pulse trio, and the counter 8 counts this. As described above, the counter 8 inverts the output state every certain number of counts. Therefore, the output signal J of the OR circuit 10
is a signal that is inverted every time a certain number of sets of pulse trios are received, regardless of the polarity inversion of the pulse trios. That is, even when a pulse trio signal is sent from the monitoring station _T1 and the polarity is reversed at an arbitrary period, the pulse trio signal can be detected at the receiving end station _T2 . At the receiving end station _T2 , the signal J
It is possible to count the number of inversions of the signal J by means of an auxiliary detector (not shown) and, for example, to connect the transmission line back when a predetermined number of inversions or more are detected within a predetermined period of time.

When a signal other than the pulse trio signal, for example, for general telephone calls, is input, the above-mentioned signal I may become a logic state "1" depending on the combination of pulse trains included in the signal. Immediately after that (because the pulse trio state is broken), the signal H is output and the counter 9 is reset, so that the output state of the counter 9 is not inverted. In other words, the counter 9 is not inverted because there is a very small chance that the same pulse state as the pulse trio train will occur consecutively during a call signal. By increasing the number of bits in the counter 9, it is possible to easily eliminate the occurrence of inversion in normal call signals. Further, the count number of the counter 8 due to the signal H is determined by the signal I due to the positive-negative-positive pulse combination present in the input signal.
It is reset by the output of
Similarly to the above, the output state of the counter 8 is not inverted. That is, signal J is not output.
In other words, the call signal will not be erroneously determined to be a pulse trio signal and the call will not be cut off by performing a loopback operation on the transmission path or the like. Therefore, the pulse trio detection circuit can be connected to the transmission line that is always in use.

Note that if the pulse trio signal train sent from the monitoring station _T1 is erroneous or extra pulses are inserted due to noise in the transmission path, for example, the logic state of the signal H described above may be changed to "1'' and resets the counter 9, so the counter 9 counts the set of pulse trios again. Therefore, the inversion of the output signal J is delayed accordingly. In other words, depending on the reception error rate of the pulse trio train,
Since the inversion of the output signal J is delayed, it is also possible to measure the error rate, for example, by counting the number of inversions of the signal J in a unit time. By putting these together, it is possible to realize a detection circuit with detection accuracy that meets the transmission quality standards required for transmission. Of course, this detection accuracy improves as the number of count stages of the counters 8 and 9 increases.

The receiving end station _T2 detects the pulse trio signal and sends E
- If the W transmission line is connected back to the W-E transmission line, the low frequency component of the pulse trio signal sent from the monitoring station _T1 will be routed through the band filter assigned to each repeater on the W-E transmission line. Since the signal can be transmitted to the existing line _L2 , the faulty repeater on the W-E transmission line can be located in the same way as described above. As a result, it becomes possible to quickly take appropriate measures and quickly restore the transmission path. Furthermore, since there is no need for a worker to go to the receiving end station, the receiving end station can be completely unmanned.

FIG. 4 shows an example of a specific circuit of the above embodiment. In the figure, a polarity separation circuit 1 is composed of a transformer TR, NAND circuits IC ₁ and IC ₂ , and the like. The midpoint of the transformer TR is grounded via a capacitor, and a bias voltage VR is applied. Then, a positive pulse above a certain value is sent to the NAND circuit IC _1.
The output voltage of the NAND circuit IC 2 is set to 0 potential, and the negative pulse sets the output voltage of the NAND circuit IC ₂ to 0 potential. NAND circuit IC ₁
The output of 3-bit shift register 5 and the second
is applied to the AND circuit 7. On the other hand, NAND circuit
The output of IC ₂ is input to the first AND circuit 6.
Furthermore, both terminals of the transformer TR are connected to an OR circuit IC ₃
and the output of OR circuit IC ₃ is input to inverter IC ₄ .
Inversion and delay are performed by . In this circuit, OR circuit IC ₃ and inverter IC ₄ constitute a clock pulse generation circuit. And inverter IC ₄
The output signal is input to the clock terminal CLK of the 3-bit shift register 5. shift register 5
The output of each step is connected to each input of the AND circuit 6 or 7 as described above, and the outputs of the AND circuits 6 and 7 are connected to the clock terminal and reset terminal of the counters 8 and 9, respectively, as shown. . Counters 8 and 9 are, for example, 3-bit counters, but by increasing the number of bits, the detection accuracy can be improved as described above. The outputs of the counters 8 and 9 are connected to an output terminal via an OR circuit 10. In the above circuit, the transformer
All except the TR are composed of integrated circuits (ICs). Therefore, it can be configured extremely compactly and requires no space at the receiving end station. Also, commercially available
Easy to configure using IC. Moreover, the various logic circuits described above can be equivalently converted, and the present invention is not limited to the above-mentioned circuits. In short, the input pulse is separated into a positive pulse and a negative pulse, and the AND circuit 7
outputs one pulse, and when the polarity of the pulse trio is reversed or when a signal other than the pulse trio is received, the AND circuit 6 outputs an output signal, and the output pulses of both the AND circuits are sent to the counters 8 and 9. It is only necessary to configure the counters so that they each count and mutually reset the counters on the other side.

As described above, in the present invention, when a pulse trio signal train is input, the logic circuit outputs one pulse for each set of pulse trios received, and the output state is inverted every time a certain number of pulses are counted. Since the counter is provided with a counter and is configured to reset the counter when a signal other than the pulse trio is input due to noise or the like, it is possible to detect that a certain number of pulse trios have been input. I can do it. Furthermore, since the same operation as described above is performed even when the polarity of the pulse trio is reversed, the pulse trio can be detected continuously even if the polarity of the pulse trio signal train sent from the monitoring station is reversed at an arbitrary period. I can do it. By detecting the pulse trio, the transmission line can be looped back and connected, which is convenient for locating the point of failure in the intermediate repeater.
Unlike in the past, there is no need for maintenance personnel to go to the receiving end station to turn back the transmission path, reducing labor and making the receiving end station unmanned. Furthermore, by increasing the number of bits in the counter, a high quality and stable test of the bit error rate can be performed, and the range of applications is wide.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining failure point locating using a pulse trio, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing the logical state of each main part in the above embodiment. FIG. 4 is a circuit diagram showing an example of a specific circuit of the above embodiment. In the figure, 1...polarity separation circuit, 2...addition circuit, 3...inversion circuit, 4...delay circuit, 5...
3-stage shift register, 6...first AND circuit, 7...second AND circuit, 8...first counter, 9...second counter, 10...OR circuit, A...input Signal, B...First signal, C...
Second signal, D'...clock pulse, 1Q, 2
Q, 3Q: output terminals of the first, second and third stages of the shift register 5; 1, 2, 3: negative output terminals of the above.

Claims (1)

[Claims] 1 Polarity separation for separating a pulse train of a bipolar signal into positive pulses and negative pulses and outputting a first signal train corresponding to the inverted state of the positive pulse and a second signal train corresponding to the inverted state of the negative pulse a clock pulse generating circuit that outputs a clock pulse train which is a binary pulse train corresponding to each pulse of the input bipolar signal and is delayed by approximately 1/2 the width of the input pulse; a three-stage shift register which outputs the logic state of the first signal train at the time of input of the clock pulse to a first stage output terminal, and which shifts each time the clock pulse is input; and one of the shift registers. 2nd and 3rd stage output terminals
a first AND circuit to which a negative output terminal of the stage and the second signal string are input; a negative output terminal of the first and third stages of the shift register; an output terminal of the second stage; a second AND circuit to which the signal sequence of the second AND circuit is input; an output of the first AND circuit is connected to a clock input terminal and a first counter is reset by the output of the second AND circuit; a second counter whose output from the second AND circuit is connected to a clock input terminal and which is reset by the output from the first AND circuit; and an OR circuit which inputs the outputs of the first and second counters. A pulse trio detection circuit characterized by comprising a circuit.