JPS6240871B2 - - Google Patents
Info
- Publication number
- JPS6240871B2 JPS6240871B2 JP57145987A JP14598782A JPS6240871B2 JP S6240871 B2 JPS6240871 B2 JP S6240871B2 JP 57145987 A JP57145987 A JP 57145987A JP 14598782 A JP14598782 A JP 14598782A JP S6240871 B2 JPS6240871 B2 JP S6240871B2
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- pinhole
- film
- semiconductor
- pinholes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】
本発明は、太陽電池等の構成層のピンホールを
不活性化する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for inactivating pinholes in constituent layers of solar cells and the like.
一般に、太陽電池、コンデンサ等の製作に於
て、前者は半導体を、後者は誘電体を電極で挾ん
だサンドイツチ構造となつている。この場合、半
導体や誘電体等の層にピンホールが存在するとピ
ンホールを通して短絡が起るので、これらのデバ
イスや部品は働らかない。半導体膜や誘電体膜に
はピンホールの発生が容易に起るので、このピン
ホールを介しての電圧の短絡効果によるデバイス
の機能低下は大きな問題である。 Generally, when manufacturing solar cells, capacitors, etc., the former uses a semiconductor and the latter uses a sandwich structure in which a dielectric is sandwiched between electrodes. In this case, if a pinhole exists in a semiconductor or dielectric layer, a short circuit will occur through the pinhole, so these devices and components will not work. Since pinholes are easily generated in semiconductor films and dielectric films, deterioration of device functionality due to the short circuit effect of voltage through these pinholes is a serious problem.
従来、ピンホールによる短絡効果の除去には、
太陽電池に於ては半導体膜を厚く成膜することに
より、またコンデンサに於ては電極に高圧を印加
することによりピンホール部分の電極を溶かして
飛ばしてしまう方法等が行ななわれていた。 Traditionally, to eliminate the short circuit effect caused by pinholes,
Methods used in solar cells include forming a thick semiconductor film, and in capacitors, applying high voltage to the electrodes to melt and blow away the electrodes in the pinhole area. .
しかし、半導体を不必要に厚く成膜することは
材料と製作時間の無駄であり金属箔を用いたコン
デンサに於ての高電圧印加によるピンホール効果
の除去は半導体膜には熱破壊を起す危険性がある
等の問題点があつた。 However, forming an unnecessarily thick semiconductor film is a waste of materials and manufacturing time, and removing the pinhole effect by applying high voltage to a capacitor using metal foil may cause thermal damage to the semiconductor film. There were problems such as gender.
本発明は、上述の問題点を解決するために、フ
オトレジストが電気的絶縁物であることを利用す
る、即ち、フオトリソグラフイの技術を積極的に
採用することにより、ピンホールをフオトレジス
トで充填し、ピンホールでの短絡効果を除去する
ことによりデバイス及び部品の性能と製造歩留り
を向上させる方法を提供する目的でなされたもの
である。以下、本発明の実施例を太陽電池の製作
にとり図に基づき説明する。 In order to solve the above-mentioned problems, the present invention takes advantage of the fact that photoresist is an electrical insulator, that is, actively employs photolithography technology to eliminate pinholes using photoresist. The objective is to provide a method for improving the performance and manufacturing yield of devices and components by filling and eliminating pinhole shorting effects. EMBODIMENT OF THE INVENTION Hereinafter, embodiments of the present invention will be explained based on the drawings for manufacturing a solar cell.
第1図は太陽電池の構成層のピンホールを不活
性化する方法の工程を説明するための図である。 FIG. 1 is a diagram for explaining the steps of a method for inactivating pinholes in the constituent layers of a solar cell.
第1図aに示すように、ガラス基板1上にネサ
膜あるいは薄い金属膜2を堆積する。ネサ膜2は
光透過性を有し、かつ、導電性を有するIn2O3、
SnO2等を用いる。また、金属膜2は金(Au)、
銀(Ag)、アルミニウム(Al)等を用いるが光に
対して半透明にするために膜厚を100Å程度に薄
く形成する。さらにネサ膜あるいは金属膜2の上
に半導体3を形成する。第1図aはこの半導体層
3中のピンホール4の状態を示す。 As shown in FIG. 1a, a NESA film or a thin metal film 2 is deposited on a glass substrate 1. The Nesa film 2 is made of In 2 O 3 which has optical transparency and conductivity.
Use SnO 2 etc. Further, the metal film 2 is made of gold (Au),
Silver (Ag), aluminum (Al), etc. are used, but the film thickness is made as thin as about 100 Å to make it translucent to light. Further, a semiconductor 3 is formed on the NESA film or the metal film 2. FIG. 1a shows the state of pinholes 4 in this semiconductor layer 3.
次いでピンホール4がある半導体層3の上にフ
オトレジスト5を塗布すると共にピンホール4内
にフオトレジストが充填された状態が第1図bに
示されている。ネサ膜または薄い金属膜2を通し
て図示矢印方向に露光を与える。露光して現像、
リンス及びフオトレジスト焼成を行うと光が当つ
たレジスト部分は残り、光の当らない部分のレジ
ストは除去されて第1図cの状態となる。即ち、
第1図cのフオトレジスト5はピンホール部分4
にフオトレジスト5が充填されると同時に、尚か
つ、ピンホール4上部にもフオトレジストが残
り、かつ、これらは硬化する。他の部分のフオト
レジストは除去されて半導体層3の表面が露出し
ている状態を示している。半導体層3及びフオト
レジスト5の上に導電性(金属膜)膜6を形成す
ると第1図dに示す状態となり、次いで、予めネ
サ膜あるいは金属膜2に設けたリード電極7とオ
ーム性電極6上にリード電極8を設けることによ
り第1図eの太陽電池が構成される。ガラス基板
1の太陽光を当てる側の表面上に反射防止膜(図
示せず)を被膜して太陽電池は完成する。 Next, a photoresist 5 is applied onto the semiconductor layer 3 in which the pinhole 4 is located, and the pinhole 4 is filled with the photoresist, as shown in FIG. 1b. Exposure is applied through the Nesa film or thin metal film 2 in the direction of the arrow shown. Expose and develop,
When rinsing and photoresist baking are performed, the resist portions exposed to light remain, and the resist portions not exposed to light are removed, resulting in the state shown in FIG. 1c. That is,
The photoresist 5 in FIG.
At the same time that the photoresist 5 is filled, the photoresist also remains above the pinhole 4 and is cured. The photoresist in other portions is removed to expose the surface of the semiconductor layer 3. When a conductive (metallic) film 6 is formed on the semiconductor layer 3 and the photoresist 5, the state shown in FIG. By providing a lead electrode 8 on top, the solar cell shown in FIG. 1e is constructed. The solar cell is completed by coating an antireflection film (not shown) on the surface of the glass substrate 1 on the side exposed to sunlight.
なお、本実施例に用いるフオトレジストはn型
のレジスト、即ち、光が照射されると重合する型
のものである。 The photoresist used in this example is an n-type resist, that is, a type that polymerizes when irradiated with light.
第1図の太陽電池に於て、2のネサ膜が、例え
ばn型半導体In2O3の場合、半導体層3はP型で
ネサ膜2の方の禁制帯幅は半導体層3の禁制帯幅
より大きく取る様にすると高効率の窓効果を利用
したヘテロ接合太陽電池が得られる。極めて薄い
金属膜2、例えば金(Au)膜の場合には、半導
体層3はn型またはP型何れを用いてもよく、こ
の様にするとシヨツトキーバリヤ太陽電池が得ら
れる。フオトレジストを塗布した半導体膜等の反
対側即ち図中1,2等が光に対して不透明な基板
の場合は光の代りにX線の照射露光を行う。 In the solar cell shown in FIG. 1, when the NESA film 2 is, for example, an n-type semiconductor In 2 O 3 , the semiconductor layer 3 is a P type, and the forbidden band width of the NESA film 2 is the same as the forbidden band of the semiconductor layer 3. By making it larger than the width, a highly efficient heterojunction solar cell utilizing the window effect can be obtained. In the case of a very thin metal film 2, for example a gold (Au) film, the semiconductor layer 3 may be either n-type or p-type, and in this way a Schottky barrier solar cell is obtained. If the opposite side of the semiconductor film coated with photoresist, ie, the substrate 1, 2, etc. in the figure, is opaque to light, X-ray irradiation is performed instead of light.
なお、コンデンサの誘電体におけるピンホール
に対しても太陽電池の構成層の場合と同様の方法
が成立するのはもちろんである。 It goes without saying that the same method as in the case of the constituent layers of a solar cell can also be applied to pinholes in the dielectric of a capacitor.
以上詳細に説明したように、本発明は太陽電池
等の構成層の半導体層等のピンホールをフオトレ
ジスト露光及びその硬化技術を用いて充填するこ
とによりピンホールを介しての短絡効果を除去
し、デバイス機能向上と製造上の歩留りの向上を
図つたものである。 As explained in detail above, the present invention eliminates short-circuit effects through pinholes by filling pinholes in semiconductor layers, etc., which are constituent layers of solar cells, etc., using photoresist exposure and its curing technology. The aim is to improve device functionality and manufacturing yield.
第1図は本発明を太陽電池に応用した実施例の
説明図で、第1図aは半導体層中にピンホールが
存在する状態を示す図、第1図bは半導体層上に
フオトレジストを塗布し露光している図、第1図
cはフオトレジストの露光、現像、リンス及び焼
成が終了した状態の図、第1図dは半導体及びピ
ンホールに充填したフオトレジスト上に導電性膜
を形成した図、第1図eはネサ膜又は薄い金属膜
とオーム性電極膜に夫々リード電極を付けて太陽
電池を完成した図である。
図中、1はガラス基板、2はネサ膜または薄い
金属膜、3は半導体、4はピンホール、5はフオ
トレジスト、6はオーム性電極膜、7及び8はリ
ード電極である。
Figure 1 is an explanatory diagram of an embodiment in which the present invention is applied to a solar cell. Figure 1a shows a state in which a pinhole exists in a semiconductor layer, and Figure 1b shows a photoresist on a semiconductor layer. Figure 1c is a diagram of the photoresist being coated and exposed, Figure 1c is a diagram of the photoresist after exposure, development, rinsing and baking, and Figure 1d is a conductive film on the photoresist filled in the semiconductor and pinholes. The formed figure, FIG. 1e, shows a completed solar cell by attaching lead electrodes to the Nesa film or thin metal film and the ohmic electrode film, respectively. In the figure, 1 is a glass substrate, 2 is a NESA film or a thin metal film, 3 is a semiconductor, 4 is a pinhole, 5 is a photoresist, 6 is an ohmic electrode film, and 7 and 8 are lead electrodes.
Claims (1)
レジストを塗布し、該フオトレジストを前記ピン
ホールに充填せしめると共に、前記フオトレジス
トで前記半導体膜を蔽う工程と、前記フオトレジ
ストを塗布した半導体膜等の反対側から光あるい
はX線を照射し、前記ピンホールに充填せしめた
フオトレジストに露光し現像、リンス、焼成を行
う工程によつて、前記ピンホールを硬化したフオ
トレジストで塞ぐことを特徴とする太陽電池等の
構成層のピンホール不活性化方法。1. A step of applying a photoresist on a semiconductor film, etc. having a pinhole, filling the pinhole with the photoresist, and covering the semiconductor film with the photoresist, and a step of applying the photoresist to the semiconductor film, etc. The pinhole is closed with a hardened photoresist by irradiating light or X-rays from the opposite side of the pinhole, exposing the photoresist filled in the pinhole, developing, rinsing, and baking. A method for inactivating pinholes in constituent layers of solar cells, etc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145987A JPS5935485A (en) | 1982-08-23 | 1982-08-23 | Method for inactivating pinholes in constituent layers of solar cells, etc. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145987A JPS5935485A (en) | 1982-08-23 | 1982-08-23 | Method for inactivating pinholes in constituent layers of solar cells, etc. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5935485A JPS5935485A (en) | 1984-02-27 |
| JPS6240871B2 true JPS6240871B2 (en) | 1987-08-31 |
Family
ID=15397560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57145987A Granted JPS5935485A (en) | 1982-08-23 | 1982-08-23 | Method for inactivating pinholes in constituent layers of solar cells, etc. |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5935485A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01319579A (en) * | 1988-06-20 | 1989-12-25 | Shin Etsu Chem Co Ltd | Production of cover layer film |
| JPH0379477U (en) * | 1989-12-01 | 1991-08-13 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0236936A3 (en) * | 1986-03-11 | 1989-03-29 | Siemens Aktiengesellschaft | Method for avoiding short-circuits during the production of electrical components, particularly for amorphous silicon solar cells |
| AU2549392A (en) * | 1991-09-13 | 1993-04-27 | United Solar Systems Corporation | Photovoltaic device including shunt preventing layer and method for the deposition thereof |
-
1982
- 1982-08-23 JP JP57145987A patent/JPS5935485A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01319579A (en) * | 1988-06-20 | 1989-12-25 | Shin Etsu Chem Co Ltd | Production of cover layer film |
| JPH0379477U (en) * | 1989-12-01 | 1991-08-13 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5935485A (en) | 1984-02-27 |
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