JPS6240888B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention provides audio ADPCM with a simple circuit configuration.
This relates to an ADPCM regenerator that converts codes into normal PCM codes. ADPCM is used as an audio band compression method.
(Adaptive Differential Pulse Code
Modulation). This method uses the data between adjacent audio samples (time T ₁ and time T ₂ ) to
By taking the difference between the predicted value calculated at T ₁ and the audio signal at T ₂ and encoding it into an ADPCM code, the audio is compressed, and then the code is decoded. By obtaining the quantized value of the difference signal and adding the values sequentially, the normal
This is a method for reproducing audio in PCM code format. Another feature is that the quantization width required to obtain the quantized value of the difference signal is changed according to the ADPCM code. FIG. 1 shows a conventional ADPCM regenerator. In Figure 1, 1 is an input terminal, 2 is an adder, 3 is a multiplier, 4 is an adder, 5 is a register, and 6
is a table that converts the ADPCM code L _o into a quantization step size movement coefficient M _{o and} outputs it. 7
is a multiplier, 8 is a mitsuta, 9 is a register, 10 is a
This is an output terminal for the PCM code, and is a terminal for connecting to a DA converter for converting a digital audio signal to an analog audio signal. Let the ADPCM code of the audio from input terminal 1 be _Lo . L _o is added by adder 2 by 0.5 for bias. The result is multiplied by the output Δ _o of register 9 by multiplier 3 . register 9
The output Δ _o is called the quantization step size. When the output of the multiplier 3 is q _o , q _o is the differential demodulation value reproduced by the ADPCM code L _o , and is given by equation (1). q _o =Δ _o・(L _o +1/2) ......(1) The differential value q _o of the multiplier 3 is the output x^ _o of the register 5
and the result x^ _o+1 is stored in register 5. These x^ _o and x^ _o+1 are the voice PCM codes. On the other hand, the ADPCM code L _o of the input terminal 1 is converted by the table 6, and a movement coefficient M _o is output. Table 6 is a table for obtaining the output M _o for the ADPCM code L _o . The output M _o of table 6 is multiplied by Δ _o by multiplier 7 to obtain Δ _o+1 . Δ _o+1 =Δ _{o ·} Mo (2) Δ _o+1 in equation (2) is limited by the limiter 8 between the minimum value Δ _nio and the maximum value Δ _nax . That is, when Δ _o+1 becomes smaller than Δ _nio , the limiter 8 outputs Δ _nio , and when it becomes larger than Δ _nax , it outputs Δ _nax . The output Δ'o ₊₁ of the limiter 8 becomes the quantization step size at the time of the next sample. Δ′ _o+1 is stored in register 9. As described above, the block diagram of FIG. 1 operates. In the process according to the configuration shown in FIG. 1, the amount of calculation required is one multiplication each by multiplier 3 and multiplier 7, and one addition each by adder 2 and adder 4. It is necessary to perform the above-mentioned calculation every short time interval (for example, 125 μsec) when an audio ADPCM code is input from the input terminal 1. This requires high-speed logic elements, especially multiplication circuits, and the arithmetic circuit itself becomes large-scale. Therefore, the applicant filed Japanese Patent Application No. 55-109800 (Japanese Unexamined Patent Publication No. 57
In Japanese Patent No. 35434), we proposed an ADPCM regenerator that can be realized with a simple circuit configuration using low-speed elements by replacing the multiplication in the second equation with a simple operation on a memory that stores the quantization step size. FIG. 2 shows an explanatory diagram of the method. In Figure 2, 50, 51, 52, and 53 are the input terminals of the ADPCM code that is sent, 50 is the polarity bit, 51 is the most significant bit among the amplitude bits of the ADPCM code, and 52 is the second , 53 are input terminals for the least significant bit. 54 is a serial input of register 58. 55, 56, 5
7, 58 is 1 for storing ADPCM code
This is a bit register. Registers 56-58 have shift capability. 59 is a read-only memory (hereinafter referred to as ROM) in which the output of register 56 is the highest address, the output of register 57 is the second address, the output of register 58 is the third address (the lowest address), and the pointer Movement amount D
Output _o . 60 is a 10-bit output pointer.
The output P _o is changed depending on the output D _o of the ROM 59. A pointer limiter 61 limits the output P _o of the pointer 60 to a specific range and outputs P' _o .
62 is a ROM, which outputs the pointer limiter 61 P′ _o
Outputs 16-bit data X using as the address. This X is a quantity corresponding to the quantization step size, and in this example is a reference value corresponding to the demodulation amount of the most significant bit of the amplitude bit. 63 is a 16-bit shift register which has the function of storing the output of the ROM 62 and shifting down. 64
is composed of 16 Ex _- OR gates, and one input of each Ex _- OR gate is commonly connected to the output of the register 55. Therefore register 55
If the output of is 1, the Ex _- OR gate 64 inverts the output bit of the shift register 63 and
Output to 5. When the output of shift register 55 is 0, Ex _- OR gate 64 outputs the output bit of shift register 63 to adder 65 as is. A 16-bit adder 65 adds the output of the Ex _- OR gate 64 and the output of the register 66. The result is stored in register 66 only when the output of register 56 is 1. 66 is a 16-bit register. 67 is a 16-bit register.
68 is an output terminal of the register 67. Next, the operation will be explained. Input terminal 50,5
The 4-bit ADPCM codes from 1, 52, and 53 are stored in register 55, register 56, register 57, and register 58, respectively. Table 1 shows the relationship between each register pattern and L _o . At the same time that these data are stored, the output X of the ROM 62 is stored in the shift register 63. Register 55, Register 56, Register 57, Register 5
Based on the output bit pattern of 8, the adder 65 performs the operations shown in Table 1. This operation corresponds to equation (1). However, in Table 1, * indicates the value of the register 66 before calculation. Also, [.] represents the largest integer that does not exceed the numbers in it (generally called the Gauss symbol).

[Table] Next, the principle of performing the operation of Δ _o+1 =Δ _o ·M _o (3) expressed by equation (2) without performing multiplication will be explained. In equation (2), M _o and Δ _o are transformed as follows. M _o = A ^Dn (4) Δ _o = Δ _nio ·A ^Pn (5) However, A and Δ _nio are positive constants, and D _o and P _o are integers. Then, according to equation (3), it is expressed as Δ _o+1 = Δ _nio・A ^Pn+Dn (6), and since P _o and D _o are integers, P _o+1 = P _o + D _o ... ...(7) is also an integer, and equation (6) becomes Δ _o+1 = Δ _nio・A ^Pn+1 ......(8), and Δ _o+1 can also be expressed in the same form as Δ _o . can. Also, the maximum value Δ _n of the quantization step size Δ _{o+1
The ax} and the minimum value Δ _nio are also expressed in the same form. Δ _nio = Δ _nio・A ^O ………(9) Δ _nax = Δ _nio・A ^Pmax ………(10) From formulas (8), (9), and (10), P _o+1 is 0 to If P _nax is in the range, Δ _o+1 in equation (8) is limited to a value in the range of Δ _nio to Δ _nax . Therefore, if you are an integer in the range of 0 to P _nax and calculate the value of Δ _nio・A ^Pn in advance, store it in memory, and use P _o as the pointer output (address of the storage element), ( The quantization step size Δ _o+1 can be determined only by the calculation of equation (7) without performing the multiplication of equation (2). D _o in equation (7) is a value corresponding to the audio compression code L _o , similar to the quantization step size movement coefficient M _o , and is herein referred to as the pointer movement amount, and its values are shown in Table 2.

【table】

[Table] ADPCM shown in Table 2 by ROM59
The code L _o is converted to the pointer movement amount D _o , and the calculation of equation (7) is executed at the pointer 60. Furthermore, the pointer limiter 61 limits the output of the pointer 60 to a range of 0 to P _nax .
The output P′ _o of the pointer limiter 61 becomes the address input of the ROM 62 . In the ROM 62, values of quantization step sizes _Δnio A ^O to _Δnio ^APmax are stored using the pointer limiter output _P'o as an address. However, due to the calculation process, a value four times as large as the above (demodulator for the most significant amplitude bit in the ADPCM code) is actually stored. The contents are shown in Table 3.

[Table] A 12-bit PCM code for audio is reproduced from an ADPCM code (usually 4 bits or 3 bits) using the ADPCM method described above. Therefore, the degree of compression of the audio signal by ADPCM encoding is 4÷12=
1/3 or 3÷12=1/4. On the other hand, in addition to the above-mentioned ADPCM method, which compresses the audio band by reducing the number of encoding bits for one sample point, it is possible to compress the audio band by making the basic audio waveform even symmetric. Therefore, there is a method of performing audio band compression. Therefore, consider the amount of information contained in the even symmetrical waveform (nT) with the number of samples of 2N-1 shown in FIG. As shown in Figure 3, since the waveform is even symmetrical, (T) = ((2N-1)T) (2T) = ((2N-2)T) 〓 〓 ((N-1)T) = ((N+1)T) relationship occurs, and N out of 2N-1 sample points
The waveform can be reproduced by the waveform values of the sample points. Therefore, by handling even symmetrical waveforms, the amount of information of speech is reduced to approximately 1/2. In addition, if even symmetrical waveforms can be reproduced using symmetrical ADPCM codes, the amount of audio information can be further reduced.
Therefore, there is a need for an ADPCM regenerator that regenerates even symmetric waveforms from symmetric ADPCM codes. The present invention aims to further improve audio information compression by reproducing an even symmetrical audio waveform (PCM code) from a symmetrical ADPCM code, and will be described in detail below. FIG. 4 shows a first embodiment of the ADPCM regenerator of the present invention. 150-163, 16 in Figure 4
Each part of 6 to 168 corresponds to 50 in FIG.
-63, 66-68 have the same names and functions. That is, 150, 151, 15
2,153 is the input terminal of ADPCM code, 154 is the serial input terminal of register 158, 155,1
56, 157, 158 are 1-bit registers for storing ADPCM codes, 159 is register 1
A read-only memory (ROM) that is addressed by the outputs of 56, 157, and 158 and outputs the pointer movement amount D _o , 160 is a pointer that outputs a 10-bit pointer value P _o , and 161 is a pointer that outputs a 10-bit pointer value P _o . A pointer limiter that limits the range, 162, uses the pointer limiter's output P′ _o as an address to calculate the amount X corresponding to the quantization step size.
Read-only memory (ROM) that outputs 16
3 is a shift register having a function of storing the output of the ROM 162 and shifting it down; 165 is an adder/subtractor; 166 is a 16-bit register that stores the initial value from the terminal 180 or the output from the adder/subtracter 165 by inputting the set signal S. This is a register. Note that the E _x -OR gate 64 and the adder 65 in FIG. 2 are replaced by an adder/subtractor 165 in FIG. 4 to simplify the explanation;

It is controlled as shown in [Table]. In FIG. 4, the blocks added to FIG. 2 are as follows: 180 is an initial value load input terminal to register 166, and 181 is a pointer 16
0 pointer value Initial value input terminal and pointer 160
The value is stored in register 183, which is a component of . 182 is a component of the pointer 160, which adds or subtracts the value of the register 183 and the output _Do of the ROM 159 according to the control signal C'. The control signal C' is given by the controller 200, and the adder/subtractor 182 performs the following calculation based on the control signal C'.

[Table] 185 is one Ex _- OR gate that inverts the output of the register 155 in accordance with the instruction from the controller 200, and inverts the control input C of the adder/subtractor 165. 186 is an AND gate that outputs the set signal S of the register 166 when the signal from the controller 200 is "1" and the output of the register 156 is "1";
If the signal from 0 is 0, the set signal S is set to an update inhibited state, and the value of the register 166 is held.
188 is an input terminal for the number of ADPCM codes for approximately half a pitch period, and 200 is a controller that provides a control signal to each block. This is done under the control of the controller.
The processing of the ADPCM regenerator is classified into the following three types.
Note that detailed processing within each process is performed in the order of description. [Process 1] Load initial value x^ ₁ to register 166 Load pointer initial value P ₂ to pointer 160 Load the value x^ ₁ of register 166 to register 167 and output. [Processing 2] Reading of ADPCM code L _o The ADPCM code L _o is given to the ROM 159,
The amount of movement D _o associated with this is obtained. The pointer value P _o is given to the ROM 162 and an associated output (=4Δ _o ) is obtained. Calculate the quantized value q _o = (L _o +1/2)・Δ _o Update the value of register 166 x _o = x _o-1 +q _o of the pointer value P _o+1 used for the next sample point (n+1 time point) Calculation P _{o +1} = P _o +D _o The value x _o of the register 166 is loaded into the register 167 and output. [Processing 3] Reading of ADPCM code L _o The ADPCM code L _o is given to the ROM 159,
The amount of movement D _o associated with this is obtained. Calculation of pointer value _{P o} The pointer value _{P o is} given to the ROM ₁₆₂ and an associated output (4Δ _o ) is obtained. Calculate quantized value q _o =(L _o +1/2)·Δ _o Update value of register 166 x _o = x _o-1 −q _o The value x _o of register 166 is loaded into register 167 and output. Table 4 shows the control of each block by the controller 200 to perform the above three types of processing.

【table】

[Table] Figure 5 shows the case where five ADPCM codes are received twice in reverse temporal relation.
This is an example of a waveform diagram in which even symmetrical code reproduction for one pitch period is performed by the ADPCM regenerator shown in the figure. In this example, there are 11 time points in one pitch period. The embodiment shown in FIG. 4 will be explained using FIG. 5. First, let the respective time points be T ₁ , T ₂ , ..., T ₁₁ . [Time point T ₁ ]-Processing 1 The initial value x ₁ is given to the register 166 from the terminal 180. A pointer initial value P ₂ is given to the pointer 160 from the terminal 181 . The value x ₁ of the register 166 is loaded into the register 167 and output. [Time point T ₂ ]-Process 2 Reading of ADPCM code L ₂ The ADPCM code L ₂ is given to the ROM 159 and the accompanying output D ₂ is obtained. The pointer value P ₂ is given to the ROM 162 and the corresponding output 4·Δ ₂ is obtained. Quantized value q ₂ = (1/2 + L ₂ )・Δ ₂ Update value of register 166 x ₂ = x^ ₁ + q ₂ Update pointer value P ₃ = P ₂ + D ₂ Load value x ₂ of register 166 into register 167 Output. [Time point T ₃ ]-Process 2 Reading of ADPCM code L ₃ The ADPCM code L ₃ is given to the ROM 159 and the accompanying output D ₃ is obtained. The pointer value _P3 is given to the ROM 162, and the corresponding output 4· _Δ3 is obtained. Quantized value q ₃ = (1/2 + L ₃ )・Δ ₃ Update value of register 166 x ₃ = x ₂ + q ₃ Update pointer value P ₄ = P ₃ + D ₃ Load value x ₃ of register 166 into register 167 and output do. [Time point T ₄ ]-Process 2 Reading of ADPCM code L ₄ The ADPCM code L ₄ is given to the ROM 159 and the accompanying output D ₄ is obtained. The pointer value _P4 is given to the ROM 162, and the corresponding output 4· _Δ4 is obtained. Quantized value q ₄ = (1/2 + L ₄ )・Δ ₄ Update value of register 166 x ₄ = x ₃ + q ₄ Update pointer value P ₅ = P ₄ + D ₄ Load value x ₄ of register 166 into register 167 and output do. [Time point T ₅ ]-Processing 2 Reading of ADPCM code L ₅ ADPCM code L ₅ is given to the ROM 159 and the accompanying output D ₅ is obtained. The pointer value _P5 is given to the ROM 162 and the corresponding output _4.DELTA.5 is obtained. Quantized value q ₅ = (1/2 + L ₅ )・Δ ₅ Update value of register 166 x ₅ = x^ ₄ + q ₅ Update pointer value P ₆ = P ₅ + D ₅ Load value x ₅ of register 166 into register 167 Output. [Time point T ₆ ]-Process 2 Reading of ADPCM code L ₆ The ADPCM code L ₆ is given to the ROM 159 and the accompanying output D ₆ is obtained. The pointer value _P6 is given to the ROM 162, and the corresponding output _4.DELTA.6 is obtained. Quantized value q ₆ = (1/2 + L ₆ )・Δ ₆ Update value of register 166 x^ ₆ = x^ ₅ + q ₆ Update pointer value P ₇ = P ₆ + D ₆ Load value x ₆ of register 166 to register 167 and output. [Time point T ₇ ]-Process 3 Reading of ADPCM code L ₆ The ADPCM code L ₆ is given to the ROM 159 and the associated movement amount D ₆ is obtained. Pointer value update P ₇ =P ₇ -D ₆ =P ₆ The pointer value P ₆ is given to the ROM 162 and the corresponding output (4·Δ ₆ ) is obtained. Quantized value q ₇ = (1/2 + L ₆ )・Δ ₆ = q ₆ Update value of register 166 x^ ₇ = x ₆ - q ₇ = x^ ₅ Load value x ₅ of register 166 into register 167 and output . [Time point T ₈ ]-Process 3 Reading of ADPCM code L ₅ The ADPCM code L ₅ is given to the ROM 159 and the associated movement amount D ₅ is obtained. Pointer value update P ₈ = P ₇ - D ₅ = P ₆ - D ₅ = P ₅ The pointer value P ₅ is given to the ROM 162 and the corresponding output (4·Δ ₅ ) is obtained. Quantized value q ₈ = (1/2 + L ₅ )・Δ ₅ = q ₅ Update value of register 166 x^ ₈ = x ₇ - q ₈ = x^ ₄ Load value x^ ₄ of register 166 into register 167 and output do. [Time point T ₉ ]-Process 3 Reading of ADPCM code L ₄ The ADPCM code L ₄ is given to the ROM 159 and the associated movement amount D ₄ is obtained. Pointer value update P ₉ =P ₈ -D ₄ =P ₄ The pointer value P ₄ is given to the ROM 162 and the corresponding output (4·Δ ₄ ) is obtained. Quantized value q ₉ = (1/2 + L ₄ )·Δ ₄ = q ₄ Update of value of register 166 x ₉ = x ₈ - q ₉ = x ₃ Load value x ₃ of register 166 into register 167 and output. [Time point T ₁₀ ]-Process 3 Reading of ADPCM code L ₃ The ADPCM code L ₃ is given to the ROM 159 and the associated movement amount D ₃ is obtained. Pointer value update P ₁₀ =P ₉ -D ₃ =P ₃ The pointer value P ₃ is given to the ROM 162 and the corresponding output (4·Δ ₃ ) is obtained. Quantized value q ₁₀ = (1/2 + L ₃ )·Δ ₃ = q ₃ Update of value of register 166 x ₁₀ = x ₉ −q ₁₀ = x ₂ The value x^ ₂ of register 166 is loaded into register 167 and output. [Time point T ₁₁ ]-Process 3 Reading of ADPCM code L ₂ The ADPCM code L ₂ is given to the ROM 159 and the associated movement amount D ₂ is obtained. Pointer value update P ₁₁ =P ₁₀ -D ₂ =P ₂ The pointer value P ₂ is given to the ROM 162 and the corresponding output (4·Δ ₂ ) is obtained. Quantized value q ₁₁ = (1/2 + L ₂ )·Δ ₂ = q ₂ Value update of register 166 x ₁₁ = x ₁₀ −q ₁₁ = x ₁ The value x^ ₁ of register 166 is loaded into register 167 and output. In the above example, five ADPCM codes L ₂ ,
L ₃ , L ₄ , L ₅ , L ₆ and initial value x ₁ and pointer initial value P ₂
The case where the even symmetrical waveform at the 11th time point shown in FIG. 5 is reproduced is shown. When this is summarized in a table, Table 5 is obtained.

[Table] As the controller 200 required to perform the above-described processing, a circuit generally called a sequencer can be used. The controller 200 shown in FIG. 6a is one example, and consists of the following parts. 201 is a register that stores ADPCM code number data input from the ADPCM code number input terminal 188; 202 is input from the register 201;
A down counter that sets the ADPCM code number data, counts down every time one processing timing ends using a clock that determines the processing timing, and outputs a status signal of "1" (1 bit) when the count value reaches 0. 203 is a sequencer ROM. The contents shown in FIG. 6b are stored in each address. This stored value indicates the next processing number and also indicates the next address of the sequencer ROM 203. 204 is a sequencer
This is a pipeline register that stores the output of the ROM 203, and the output is input to the gate control circuit 205 and the lower two bits of the sequencer ROM. 20
Reference numeral 5 denotes a gate control circuit that controls the gates of each section according to the output of the pipeline register 204. FIG. 7 shows the operation sequence of the control circuit 200, taking as an example the case where the number of ADPCM codes is five. The numbers in each item indicate input values, output values, processing numbers, etc. With the above method and circuit configuration, symmetrical
Even-symmetric PCM code audio can be reproduced from ADPCM code. As a result, the amount of data in the ADPCM code has been halved compared to the conventional method. The present invention can be used in an ADPCM regenerator that attempts to regenerate even symmetrical waveforms.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional ADPCM circuit, Fig. 2 is a block diagram of another conventional ADPCM circuit, Fig. 3 is a diagram showing an example of an oddly symmetrical waveform, and Fig. 4 is a diagram of an ADPCM regenerator according to the present invention. It is a block diagram. Fifth
6 is a diagram showing an example of a controller used in the present invention, and FIG. 7 is a diagram showing an operation sequence of the controller shown in FIG. 6. 150 to 153...Input terminals (1 bit each),
154...Register 158 serial input, 155
~158...Register (1 bit each), 159...
...ROM (address 3 bits, output 5 bits), 1
60...Pointer (output 10 bits), 161...
Pointer limiter (output 6 bits), 162...
ROM (address 6 bits, output 16 bits), 16
3: Shift register (16 bits), 165... Adder/subtractor (16 bits), 166... Register (16 bits), 167... Register (16 bits), 168
...Output terminal (12 bits), 180...Register 166 load input, 181...Pointer 160 initial value input (6 bits), 182...Adder/subtractor, 1
83...Register (selector), 185...E _x -
OR gate (1 piece), 186: AND gate, 20
0...Controller.

Claims (1)

[Scope of Claims] 1. A first memory 162 that stores a plurality of predetermined quantization step sizes, and a method for specifying an address of the first memory to retrieve one quantization step size from the first memory. The initial pointer value given from the outside is the pointer 160 that is set before reproducing the PCM code of the second sample in the 1-pitch waveform, and the pointer output is output according to the ADPCM code. A second meseri 159 that stores the amount of movement for the movement and an initial value x^ that is capable of storing the reproduction PCM code and is given from the outside.
A register 166 in which ₁ is set as the PCM code of the first sample, and a PCM code of the next sample is reproduced from the reproduced PCM code stored in the register, the output of the first memory, and the ADPCM code, and the PCM code of the next sample is stored in the register. Means 163, 165, 185, 1 for storing
86, and reproduces an even symmetrical one-pitch waveform by repeatedly accepting ADPCM codes corresponding to approximately half the number of samples of a one-pitch waveform twice in reverse temporal order.
In the ADPCM regenerator, in the process of reproducing the PCM code of the first half sample of the pitch waveform, the calculation of the pointer 160 is performed after reproducing the PCM code, and the PCM code of the second half sample is
In the process of reproducing the code, the operation of the pointer 160 is
An ADPCM regenerator characterized in that it is equipped with a means for reproducing a PCM code.