JPS6240902B2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field of the Invention This invention relates to a system in which a document or a form is skewed and input into an image data processing device such as a facsimile device or OCR, and the image data is stored in an image memory while being skewed. The present invention relates to a tilt processing circuit for data in memory, which can be applied to a circuit for correcting image data to a form close to the original image, and can also be applied when it is desired to tilt and edit data in an image memory. It is something.

In recent years, as office automation has become more popular, for example, facsimile machines and OCR have been combined. A facsimile device is a device that transmits original documents as electrical signals.
OCR is a device that recognizes characters on documents. Therefore, by combining these, an application can be considered in which image data sent by a facsimile device is recognized and processed by OCR. However, as is well known, OCR is a device that detects a line of characters and cuts out a single character based on this and performs recognition, so if a form is skewed and input, the recognition accuracy will decrease, causing serious problems. In some cases, it becomes completely unrecognizable.

In addition, some facsimile devices with editing functions have appeared, but it would be better if the data (images) in the image memory could be used at an appropriate angle as part of the editing process. It is advantageous to have diversity.

Technical Background of the Invention Conventionally, image data stored in an image memory is read out stepwise in predetermined bit units (for example, byte or word units) according to the slope of the image data, and arranged in one line. The above-mentioned processing request was met by repeating the process of storing the image in the image memory again.

For example, as image data, a black line l as shown in FIG. (In Figure 1, it is image memory 2.), according to the conventional method, (x, y) =
(0, -3), (1, -2), (2, -1), (3, 0
),
. . . (The coordinates in the x direction are shown using 2 bits as a unit.) These are arranged in one line and stored in the 0th line of the image memory 400 shown in FIG. 300 in steps of 2 bits at a time (x, y) = (0, -2), (1, -1),
(2, 0), (3, 1), . . . are read out, arranged in one line and stored in the first line of the image memory 400, and the same operation is repeated thereafter.

Problems with the Background Art However, according to the conventional method as described above, the black line l in FIG. 8a becomes like the black line l1 in FIG. This resulted in unevenness, making it impossible to obtain an image faithful to the original image.

OBJECT OF THE INVENTION The present invention has been made in view of the drawbacks of the conventional tilt processing circuit as described above, and its purpose is to provide a memory storage system that can obtain an image that is more faithful to the original image as a result of the tilt processing. An object of the present invention is to provide a data slope processing circuit.

Summary of the Invention The present invention includes an image memory in which image data is stored, an image memory that is accessed, the slope of the stored image data is detected, and when the data is read out in stages, a calculation means for determining the number of block bits indicating whether to update the address in the y direction and read the bit data when reading the data, and the shift direction and number of shift bits of the data to be performed to correct the inclination of the data of the image; , stepwise reading means for reading data in the image memory based on the number of block bits determined by the calculating means, and shifting means for shifting data based on the shift direction and the number of shift bits determined by the calculating means. The above-mentioned object has been achieved by realizing a slope processing circuit for data in the memory, having a configuration in which the data in the image memory is processed by both the stepwise reading means and the shifting means.

That is, in the above-described skew correction and editing processing, it is necessary to tilt the image in the image memory without causing distortion. To achieve this, first, read one column (one line) of data in the image memory, shift it by the number of bits necessary to avoid distortion of the image, and then adjust the slope. The second method is to update the address sequentially every several bits (or bytes), which is the number of block bits, and store it again in the image memory.Secondly, when reading data from the image memory according to the slope, The line address is updated every several bits (or bytes), which is the number of block bits, and the data is read out. After the data is shifted to avoid distortion, the data is stored in the image memory using the same line address. One possible method is to store it again.

The line address output circuit of the present invention plays the role of updating and outputting the line address in the two methods described above, and the line data shift circuit plays the role of updating and outputting the line address in the two methods described above. It plays the role of making a shift. That is, in this embodiment, the calculation control section 1 functions as calculation means, the line address output circuit 3 functions as stepwise reading means, and the line data shift circuit 4 functions as shift means.

In the embodiment described below, a case using the second method will be described, but it goes without saying that the first method can also be adopted in the same circuit. Also,
It is also possible to adopt a compromise between the first and second methods. In other words, even when writing image data read from the image memory by updating the line address every few bits (or several bytes) to the image memory, the line address is updated every several bits (or several bytes). . In this way, for example, data that was tilted to the right can be tilted to the left.

Embodiments of the invention Hereinafter, regarding the case according to the above-mentioned second method,
Embodiments of the present invention will be described with reference to the drawings. Further, in the following example, a case will be described in which the circuit is used as a skew correction circuit.

As shown in FIG. 1, an arithmetic control section 1, an image memory 2, a line address output circuit 3, and a line data shift circuit 4 are connected by an address bus 5 and a data bus 6. The address bus 5 has, for example, 24 bits, of which the upper 16 bits are used as a line address, the remaining lower 8 bits are used as a byte address, and the data bus 6 has, for example, 8 bits.

The arithmetic control unit 1 has a processor function, and uses a read/write command (not shown) to process, for example, an image output from a photoelectric conversion unit in an image data processing device to which it belongs or which has been transmitted. Store the data in image memory 2. Then, based on the stored image data, the arithmetic control unit 1 controls the original,
Alternatively, calculate the slope of the form. That is, the arithmetic control unit 1 determines how much the image data should be tilted. For example, as shown in Figure 2,
Assuming that marks ▼ for calculating the inclination are printed on both upper edges 8A and 8B of the original 7, the arithmetic control unit 1 calculates the inclination from the addresses in the image memory 2 where the two marks ▼ are stored. calculate.

Based on the calculated slope, the calculation control unit 1 calculates how many bits the line address should be updated for the data in the image memory 2. For example, when the input document 9 is slightly tilted with respect to the reference line 10 as shown in FIG. 3A, the line address LA is set in units of 20 bytes according to the tilt as shown in FIG. 3B. It is decided to update and read the data. Furthermore, when the document 9 is extremely tilted with respect to the reference line 10 as shown in FIG.
It is decided to read the data by updating it in units of 4 bytes as shown in FIG. 4B. Furthermore, when calculating the above-mentioned inclination, it is also calculated whether the document 9 is tilted upward to the right as shown in FIG. 3A or upward to the left as shown in FIG. 4A. Then, in the case of an upward movement to the right, it is decided that the line address is to be updated continuously up, for example, and in the case of an upward movement to the left, it is decided that the line address is to be updated continuously, for example, down.

Furthermore, based on the calculated slope, the arithmetic control unit 1 determines whether to shift one line of data in the image memory 2 to the right or left, and also calculates how many bits to shift in order to avoid distortion. do. For example, when the document 9 is tilted upward to the right as shown in FIG. 3A, more data that would be stored in the memory area having the lower line address is shifted to the left. Further, when the document 9 is tilted upward to the left as shown in FIG. 4A, more data that would be stored in the memory area having the upper line address is shifted to the left.

The method of continuously updating line addresses and the method of shifting each line data in the above explanation is 1.
Just an example. That is, depending on which position is used as a reference for correcting the skew, the direction and number of shifts of line address up/down and data shifting are variable. For example, if you want to perform correction based on the center of the document 9, if the tilt is as shown in Figure 3A, the further upward you go from the center, the more it will shift to the right, and the more you go below the center, the more it will shift to the left. Make it shift.

In any case, the arithmetic control section 1
For each line of data to be read from the line, it must have data on how many bytes (bits) the line address should be changed, and data on how many bits to shift each line in which direction.

Next, the line address output circuit 3 will be explained. The line address output circuit 3 receives a latch signal LATCH and a load signal from the arithmetic control unit 1.
LOAD, a load signal LOAD, and an up/down signal UP/DOWN are provided. Further, the line address output circuit 3 is supplied with a clock signal BYTE CLOCK generated for each required number of bits and a line address output signal OUT from the line data shift circuit 4.

Specifically, the line address output circuit 3 includes a latch circuit 11, a byte number counter 12, a line address counter 13, a delay circuit 14, a gate 15, and an OR gate 16, as shown in FIG.

The latch circuit 11 receives data from the arithmetic control section 1 via the data bus 6, which indicates how many bytes the line address is to be updated stepwise, as calculated by the arithmetic control section 1. At this time, the data is latched in the latch circuit 11 by the arithmetic control section 1 activating the latch signal LATCH. Next, the data latched in the latch circuit 11 is loaded into the byte number counter 12 when the arithmetic control section 1 activates the load signal LOAD. This byte number counter 12 is counted down by the clock signal BYTE CLOCK output from the line data shift circuit 4 every time one byte of image data is input to the line data shift circuit 4. Then, when the number of bytes loaded into the byte number counter 12 is counted down and reaches zero, the byte number counter 12 outputs the line address advancement clock LADCK to the line address counter 13 and the delay circuit 14.
This line address advancement clock LADCK is delayed for a predetermined time by the delay circuit 14, and then reaches the byte number counter 12 via the OR gate 16.
Functions equivalent to the load signal LOAD. That is,
It has the function of loading the data input to the latch circuit 11 into the byte number counter 12 again.

On the other hand, the line address counter 13 receives a line address (for example, an image The first address of the area where data is stored is output, and the load signal is output.
Load the line address with LOAD active. Furthermore, the arithmetic control unit 1 sends an up-down signal to the line address counter 13.
Use UP/DOWN to indicate whether to count up or down. This line address counter 13 is counted up or down by the line address advance clock LADCK output by the byte number counter 12. The line address that has been counted down or counted up is line address counter 1.
3 and reaches gate 15. gate 15
When the line address output signal OUT indicating the timing at which the line address should be output is made active and applied from the line data shift circuit 4, the output of the line address counter 13 is sent to the address bus 5. .

To explain with a specific example, when the arithmetic control unit 1 decides to update the line address down every 2 bytes and read the data, and starts this process from address #0 of the image memory 2, , 2 (byte) is stored in the latch circuit 11, 2 (byte) is stored in the byte number counter 12, and #0 (address) is stored in the line address counter 13. and,
When the clock BYTECLOCK is given, the contents of the byte number counter 12 decreases from "1" to "0".
When it becomes "0", a signal equivalent to the load signal LOAD is input to the byte number counter 12 via the OR gate 16, and "2" (byte) is loaded again. As described above, when the byte number counter 12 reaches "0", the line address advancement clock LADCK is output, and the contents of the line address counter 13 are updated from #0 to #1. Furthermore, the line address output signal OUT is made active and output to the gate 15 at a predetermined timing, and as a result, #1 (address) is sent onto the address bus 5.

Next, the line data shift circuit 4 will be explained. The line data shift circuit 4 is configured to receive a transfer clock signal BIT CLOCK, a load signal LOAD, a reset signal RESET, a mode signal MODE, a clear signal CLEAR, and a transfer start signal START from the arithmetic control section 1.

Specifically, the line data shift circuit 4
As shown in the figure, a DMA (direct memory access controller) 17, a P/S (parallel-serial) converter 18, an S/P (serial-parallel) converter 19, a line memory 20, a bit address counter 21, and a selector 22. , and a flip-flop (hereinafter referred to as F/F) 23.

When the line data shift circuit 4 operates, the arithmetic control unit 1 first outputs the line data store start address to the bit address counter 21 via the data bus 6, and then outputs the load signal.
Make LOAD active. As a result, the starting address of the line data (starting address #0 of the line memory 20) is loaded into the bit address counter 21. Next, the calculation control unit 1 sends a clear signal
After activating CLEAR, the mode signal
MODE is set as the input mode, and the DMA 17 is caused to transfer data from the image memory 2. That is, the arithmetic control unit 1 sets the data start address, data length, etc. in the DMA 17, and sends a transfer start signal.
Make START active.

Then, DMA17 outputs the line address output signal.
OUT is made active, and 1-byte data is input from the image memory 2 based on the address output by the line address output circuit 3. After that, the DMA 17 outputs the clock signal BYTE CLOCK.
is output to the byte number counter 12 of the line address output circuit 3, and the input 1-byte data is output to the P/S converter 18. The P/S converter 18 sends one byte of data to the line memory 20 bit by bit in synchronization with the transfer clock BITCLOCK output from the arithmetic control section 1. When the sending of one byte is completed, the P/S converter 18 outputs the data request signal REQ as active to the DMA 17. As a result, DMA17 sends the next 1 byte data to P/S.
The signal is sent to the converter 18.

On the other hand, the bit address counter 21 transfers the bit data output from the P/S converter 18 to the line memory 20 while counting up the address for the line memory 20 in synchronization with the transfer clock BITCLOCK sent from the arithmetic control unit 1. are sequentially stored in the line memory 20 starting from the first address #0. When one line of data (one line of image memory 2) is stored in the line memory 20 in this way, the arithmetic control unit 1 is notified of the end of input from the DMA 17 using the terminal count signal TC, and the line memory The operation of transferring the data in 20 to the image memory 2 is started.

That is, the arithmetic control unit 1 loads the number of bytes for one line of the image memory 2 into the latch circuit 11, and loads the transfer destination address in the image memory 2 into the line address counter 13 of the line address output circuit 3. . Then, the bit address counter 21 of the line data shift circuit 4 outputs the number of bits to be shifted (here, we are considering an example of right shift) calculated from the inclination of the document onto the data bus 6 as an initial address. then load signal
Load by activating LOAD. Furthermore, the arithmetic control unit 1 sends a clear signal CLEAR to the DMA 17 as active,
The mode signal MODE is set to output mode, and the transfer start signal START is set to active. The bit address counter 21 counters the transfer clock one bit at a time from a preset address.
Bit data is sent to the selector 22 in synchronization with BITCLOCK.

Here, the selector 22 is controlled by the output of the F/F 23, and it is assumed that, for example, the F/F 23 has been reset by the reset signal RESET output from the arithmetic control section 1 before the start of data transfer. Then, the selector 22 selects the line memory 20
Pass the output of . The data that has passed through the selector 22 reaches the S/P converter 19 and is summarized into 1 byte of data. The formation of one byte of data is detected based on the transfer clock BITCLOCK, and the S/P converter 19 outputs a data output request signal OUTREQ to the DMA 17. As a result, the DMA 17 inputs 1 byte data from the S/P converter 19 and transfers this data to the address output by the line address output circuit 3 of the image memory 2. In this case, in the line address output circuit 3, the byte number counter 12 does not output the line address increment clock LADCK until data has been stored in one predetermined line of the image memory 2.
Every time data is stored in one line of the image memory 2, a line address advance clock LADCK is output, and the output of the line address counter 13 is updated. During this time, the DMA 17 outputs the address (ROW ADDRESS) in the length direction of the image memory 2 for each byte of data, and transfers the data. conduct. Therefore, one line of data stored in the line memory 20 and shifted to the right is arranged in one line at a predetermined address in the image memory 2.

Repeat this operation to store line memory 2.
When the final bit within 0 is output, the bit address counter 21 outputs a line end signal END to the F/F 23. As a result, F/F2
3 is set and its output reaches the selector 22.
As a result, the selector 22 selects the "0" input, and the S/P converter 19 receives "0". Then, this "0" is output by the number of bits to be shifted, and as a result, 1 of the image memory 2 is
The last few bits of the line are stored as "0".

Of course, the control of the selector 22 by the F/F 23 is not limited to the above example, but also differs depending on whether the document is tilted upward to the right or upward to the left, or which part of the document is centered to correct the skew. . That is, in the case of left shift, initially F/
Set F23 and set "0" to selector 22.
is input, and when the required number of bits "0" is input, the arithmetic control unit 1 outputs a reset signal RESET to reset the F/F 23, and allows the output of the line memory 20 to pass from the selector 22. Good too.

In this way, the data in the image memory 2 is read out by updating and updating the line address for each required number of bits to create one line of data. Furthermore, by shifting this data by the required number of bits by the line data shift circuit 4,
Skew correction is performed.

That is, suppose that the image of the document 9 as shown in FIG. 7a is skewed due to skew and becomes an image in the image memory 2 as shown in FIG. 7b. Diagonal line 201
Since this part is not in the original image, it is unclear what will happen when it enters the image memory 2. Further, the diagonally lined portion 202 is a portion that is present in the original image, but was deleted at the stage of inputting it to the image memory 2.

When an image as shown in FIG. 7b is input to the skew correction circuit of this embodiment, it becomes an image as shown in FIG. 7c, which is corrected to an image almost similar to the original image. If the image in FIG. 7b is corrected using only the line data shift circuit 4, it will become an image as shown in FIG. It becomes an image.

In this way, in order to correct one line of data, the processing in which the arithmetic control unit 1 is involved is the start processing when inputting one line data from the image memory 2 to the line memory 20, and the processing when inputting one line data from the line memory 20 to the image memory. This is only the output start process when outputting one line of data to the second line, and the processing time can be reduced. Therefore, for example, the above-mentioned inclination processing circuit for data in memory may be adopted in a facsimile device, etc., and the arithmetic control unit 1 may perform processing for encoding/compressing image data, decoding/expansion processing, and controlling the modem, NCU, etc. In this case, the load on the arithmetic and control unit 1 can be reduced. Furthermore, when a plurality of arithmetic control sections are provided to perform the above control, more control can be assigned to the arithmetic control section 1 that performs the tilt process, and it is also possible to reduce the number of arithmetic control sections. Furthermore, the line memory 20 has a capacity to store data for one line, and can be read from any bit for shifting, so it is possible to easily shift the required number of bits. Next, the operation of correcting the slope of the black line l in the image memory 300 in FIG. 8a using the memory data slope processing circuit as described above will be described.

The arithmetic control unit 1 detects that the black line l is tilted downward by 1/2 to the right using the method explained in Figs. If the images are lined up and shifted by increasing the right shift by 1 bit every two lines from the 5th line (counting from the 0th line), and this image data is stored in the image memory 500 (FIG. 8c), a faithful image will be created. Detects that the data is obtained and calculates the necessary data. The arithmetic control section 1 loads the necessary data calculated above into the line address output circuit 3 and line data shift circuit 4, and causes the line address output circuit 3 and line data shift circuit 4 to start operating. As a result, the image memory 300
The data stored in
),
(3, 0), . . . are read out, arranged in one line and stored in the 0th line of the image memory 500 shown in FIG. ,y)=(0,-2),(1,-
1), (2, 0), (3, 1), ..., and 1
The images are arranged in lines and stored in the first line of the image memory 500. The following image data in the image memory 300 are (x, y) = (0, -1), (1,
0), (2, 1), (3, 2), ..., and 1
This is stored in the second line of the image memory 500, (x, y) = (0, 0),
(1, 1), (2, 2), (3, 3), etc. are read out and arranged in one line, and this is stored in the image memory 50.
stored in the third line of 0, (x, y) = (0,
1), (1, 2), (2, 3), (3, 4), etc. are read out, arranged in one line, shifted one bit to the right, and stored in the fourth line of the image memory 500. , (x,y)=(0,2),(1,3),(2,
4), (3, 5), ... are read out, arranged in one line, shifted one bit to the right, and stored in the fifth line of the image memory 500, so that (x, y)=
(0, 3), (1, 4), (2, 5), (3, 6),...
…
are read out, arranged in one line, shifted 2 bits to the right, and stored in the 6th line of the image memory 500, (x, y) = (0, 4), (1, 5),
(2, 6), (3, 7), . . . are read out, arranged in one line, shifted to the right by 2 bits, and stored in the seventh line of the image memory 500. Thus, the black line l in the image memory 300 corresponds to the image memory 5.
00, and an image faithful to the original image can be obtained without unevenness occurring at both ends.

In the above explanation, when reading from the image memory 2, the line address is updated and read out every few bytes, and this is shifted and stored in the image memory as one line data. According to method 1, when reading from the image memory, one line of data may be read and shifted, and then when storing the data to the image memory, the line address may be updated every several bytes and the data may be stored. Even if this is done, the degree of intervention of the arithmetic control unit does not change, the capacity of the image memory is only increased by an amount corresponding to the assumed maximum slope, and other hardware remains unchanged. As with the above method, an image that is faithful to the original image can be obtained.

Effects of the Invention As described above, according to the present invention, an image that is more faithful to the original image can be obtained by shifting by the line data shift circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the main part of the present invention.
2 to 4 are conceptual diagrams of the slope processing process according to the present invention, FIG. 5 is a block diagram of an embodiment of a line address output circuit, FIG. 6 is a block diagram of an embodiment of a line data shift circuit, and FIG. FIG. 7 is a conceptual diagram for explaining an example of skew correction according to the present invention, and FIG. 8 is a diagram of image data in the image memory showing a comparison between tilt processing according to a conventional example and tilt processing according to an embodiment of the present invention. It is. 1... Arithmetic control unit, 2... Image memory, 3...
Line address output circuit, 4...Line data shift circuit.

Claims (1)

[Claims] 1. An image memory in which image data is stored, and how many bits of data are read in the x direction when accessing this image memory, detecting the slope of the stored image data, and reading the data stepwise. time y
a calculation means for determining the number of block bits indicating whether to update the address in the direction and read out; a calculation means for determining the shift direction and number of shift bits of data to be performed for correcting the inclination of data of the image; and a calculation means for determining the number of block bits determined by the calculation means. stepwise reading means for reading out the data in the image memory based on the number of bits to be shifted; and shifting means for shifting the data based on the shift direction and the number of shift bits determined by the arithmetic means; 1. A slope processing circuit for data in a memory, characterized in that the data of the data in the memory is processed by both the stepwise reading means and the shifting means.