JPS6242300B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address expansion method, and more particularly to an address expansion method that allows addressing in a device before expansion when memory capacity is expanded.

Generally, in a program-controlled electronic computer, as shown in FIG.
The operation part of the instruction word is decoded by
etc. control gate circuits. The contents of the program counter 13 are incremented or decremented and updated by the adder circuit 14 each time an instruction word is read, so that the contents of the program counter 13 are continuously stored in the main memory 13.
The command word is read from 2.

The capacity of the main memory 12 is large enough that instructions can be directly specified using addresses of approximately 24 to 32 bits in large machines, whereas instructions can be specified directly using addresses of up to 20 bits in small machines such as mini-computers. The size is large enough to specify a word. However, since it is impossible to directly specify a 20-bit address using an instruction word due to constraints such as the capacity of each register, an indirect addressing method is usually used for instruction words.

As shown in FIG. 2, an instruction word for indirect addressing generally consists of an operation part OP and an operand part OD, and the operand part OD is further divided into a first operand OD1 and a second operand OD2. When the operation specification of the operation part OP is addition, the data at the addresses specified by the first operand OD1 and the second operand OD2 are added together, and the result is added to the first operand.
It is stored at the address of OD1, and when the operation designation is transfer, the data at the address of the first operand OD1 is transferred to the address of the second operand OD2.

Figures 2a and 2b are format diagrams of command words for large machines.
RS format (Register to
Storage Type): register and main memory 12
Specify the operation between the areas within. each operand
Both OD use the indirect addressing method, and the distance from the basic address specified by the base registers B ₁ and B ₂ is indicated by displacements D ₁ and D ₂ .

On the other hand, Figure 2c is a format diagram of an instruction word for a small machine.In microcomputers, etc., in order to reduce the total number of bits of the instruction word, the first operand OD1 is not specified and the accumulator (accumulator) is used. calculator
ACM), and only the second operand OD2 is specified in the instruction word. Also,
Specify _X2 to add the contents of index register _X2 .

Now, when executing the command shown in Figure 2c,
In FIG. 1, it is first necessary to read the instruction from main memory 12 and then calculate the operand address. ID index register X is 16
If there are multiple bits, 4 bits are required to specify one of them. Arithmetic unit 20 adds the _contents of _index register Displacement D ₂ is set, and the adder 20 adds the contents of registers 18 and 19. Since the second operand address is thus calculated, the second operand is read from the main memory 12 using this register. Next, the operation part OP of the instruction word is decoded by the decoder 16,
The control signal generated by decoding drives the arithmetic unit 20 and each register to drive the accumulator.
An operation is performed between the first operand in the ACM and the second operand read earlier. Finally, the calculated result is written to, for example, the accumulator ACM or a specified address.

By the way, when increasing the capacity of the main memory 12, or when using a virtual memory method that freely expands the address space and assigns addresses without being limited by the physical capacity of the main memory 12,
Since it is limited by the number of bits in the program counter 13, addressing of all data is impossible. In addition, the logical address of virtual memory and the real address of main memory 12 are divided into pages, and it is not possible to tell which page of main memory 12 each page of virtual memory corresponds to without referring to the page table. Attachment is impossible.

Therefore, by specifying the operand portion OD2 of the instruction word shown in FIG. 2c, an address within the same page range in which the instruction word is stored can be specified, but an address outside the page cannot be specified. Therefore, conventionally, when specifying an address outside the page, an address within the same page is specified once using the operand part OD2 in the instruction word, and then the contents of that address are used as the effective address to specify the address outside the page. .

FIG. 3 is an explanatory diagram of a conventional address expansion method for increasing memory capacity.

For example, if the bit length of the program counter 13 is 10 bits, the capacity of the main memory 12 before expansion is large enough to specify ²¹⁰ addresses. Now, if the capacity of the memory 12 is doubled and a memory 12' is added, the range of the memory 12 is the range that can be addressed by the operand part OD in one instruction word. In order to specify addresses within the extended memory 12', a state designation register indicating the address extension state, for example flip-flop 21, is provided, and the presence or absence of the address extension state is determined based on the value of this register.

For example, when the previous instruction word is read into the instruction register 15, the operation part of the instruction word
When the specified bits of OP and operand portion OD have specified contents, flip-flop 21 is set to indicate the address of the expanded portion of memory 12'. In the next step, the area 121 of the memory 12 is specified using the contents of the program counter 13 as an address, but since the flip-flop 21 is set to "1", in this case, the expanded memory 12' An area 122 corresponding to the area 121 is specified, and the instruction word or data (operand) stored there is read out.

However, this method requires address extension hardware and instructions to control the state specification register.

The purpose of the present invention is to eliminate such conventional drawbacks by providing a system that is compatible with existing software and
An object of the present invention is to provide an address extension method that allows a device before address extension to specify a memory address after address extension without newly providing a state specification register for address extension and a command word for address extension.

The address extension method of the present invention compares the value of the address field in the read instruction word with the value of the address of the main memory where the instruction word is stored, and when they match, it is regarded as a two-word instruction, and Read the contents of the next address where the instruction word is stored,
The feature is that this content is regarded as part of the address modification, and an effective address that is expanded beyond the address that can be specified with one instruction word is generated.

Hereinafter, the principle and embodiments of the present invention will be explained with reference to the drawings.

FIG. 4 is a diagram showing the operating principle of the present invention.

In the present invention, the designation of the presence or absence of address extension is determined based on the value of the address part of the read instruction word and the value of the address where the instruction word is stored.

When the microprogram reads one instruction word from the main memory 12 to the instruction register 15, before performing operand address calculation,
The value of the address part A, which is part of the instruction word, is compared with the value of the program counter 13, and if the results do not match, no address conversion is performed and the operation of the one-word instruction is performed. Also, if the comparison results in a match, address conversion is performed, the instruction word is regarded as a two-word instruction, and the address N of the instruction word read earlier is
The contents of the next address (N+1) are stored in the main memory 12.
Read from. Then, using the contents of the next address as an operand, specify address conversion registers B and
and the rest of the operand as displacement D, address conversion register B,
Add to the contents of X to generate an extended effective address.

In this way, the present invention allows micro-instructions to:
It is determined whether it is a two-word instruction or a one-word instruction, and if it is a two-word instruction, the contents of the next address (N+1) are read. Since only the second operand OD2 is provided at the next address (N+1), the displacement D can be large, and therefore even the extended memory address can be specified.
According to the present invention, physical addresses can be expanded without modifying conventional software and only by adding a few microprograms.

FIG. 5 is a detailed explanatory diagram of an address extension method showing an embodiment of the present invention.

The contents of the program counter 13 indicate the address where the program instruction is stored, and here consist of 20 bits. The instruction word consists of a 5-bit operation code 2, a 1-bit indirect specification section 3 that specifies direct or indirect addressing, and a 10-bit address section 4 that specifies the address within the page. Become,
Consists of a total of 16 bits.

After reading the instruction word from the main memory 12 according to the contents of the program counter 13, the microprogram compares the value of the 10 bits of the address field 4 of the instruction word with the value of the lower 10 bits of the program counter 13 using the comparison means 11. Comparison is made, and if there is a mismatch, address extension is not performed and a one-word instruction operation is executed. If the comparison results in a match, the contents of the next address (N+1) of the instruction word are read out as an operand under microprogram control. The operands are a 1-bit index register specification section 5 that specifies the 20-bit index register (XR) 9, and a 2-bit base register that specifies the four 20-bit base registers (BR0 to BR3) 8. It consists of a register designation section 6 and a 13-bit displacement 7, totaling 16 bits.

Under microprogram control, the contents of displacement 7, base register 8, and index register 9 are added to generate a 20-bit effective address 10. This allows address expansion to be achieved.

However, in order to extend the address, it is necessary to store values for address extension in the base register 8 and index register 9 in advance.

In the example shown in FIG. 5, since the effective address has been expanded from 16 bits to 20 bits, the memory capacity that allows ²¹⁶ addresses to be specified can be expanded to a memory capacity that allows ²²⁰ addresses.

As explained above, according to the present invention, there is no need to newly provide an address extension specification register in hardware, and there is no need to add an address extension instruction. Since address expansion can be realized, it is extremely effective when applied to a page address type data processing device.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the main part of a program-controlled computer, Fig. 2 is an explanatory diagram of instruction words for indirect addressing, Fig. 3 is an operational block diagram of the conventional address extension method, and Fig. 4 is a diagram of the present invention. FIG. 5 is a diagram explaining the detailed operation of the address extension method according to an embodiment of the present invention. 2: operation section, 3: indirect specification section, 4: address section, 5: index register specification section, 6: base register specification section,
7: displacement, 8: base register, 9: index register, 10: effective address register, 11: comparison means, 12: main memory, 13: program counter, 15: instruction register, 16: decoder, 17: Local storage (work register), 18, 19: Register, 20: Arithmetic unit.

Claims (1)

[Claims] 1. In an electronic computer that processes one-word instructions under microprogram control, the value of the address part, which is part of the instruction word read from main memory, and the address of the main memory where the instruction word is stored. When the comparison result matches, it is regarded as a two-word instruction, the contents of the next address where the instruction word is stored are read, and the operand address is determined using the contents as part of the address modification. An address extension method featuring: