JPS6242316B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for reading and decoding high-density linear bar codes of the Universal Product Code standard symbol and its variants. In the grocery industry, Universal Products
It uses a linear bar code known as a bar code (UPC). The Universal Product Code symbol is widely used in the grocery industry by marking the packaging, containers, cans, etc. of products that are packaged and sold. This standard symbol consists of a series of parallel light and dark bars of varying widths, with corresponding optical character reading (OCR-B) numbers printed alongside the bar code symbol. This standard UPC symbol is also used on the labels of inventory items to verify inventory and perform inventory adjustments. Conventionally, various standard UPC symbols and their characteristics have been used not only in the grocery industry, but also in other industries, such as medicine and health-related products, general miscellaneous goods, and department store items. It has been published in the literature. In addition, there are additional features such as zero-suppression that make it easier to mark packages that are too small to be marked with the UPC symbol or DCI symbol.
Special methods have been developed. A transportation symbol (DCI) is designed to be printed on shipping containers. The main advantage of using the UPC symbol is that the product can be automatically verified at the verification point in conjunction with automated electronic verification systems. In current verification systems, UPC bar code symbols are read using high-speed laser light scanning devices. To scan the UPC symbol and its series of DCI symbols,
Portable data collection equipment is also a must. This is most easily satisfied with handheld wand scanning devices. Wound scanning device is
Since it is scanned in contact with the label, it does not need to have the field depth required by the scanning device at the verification site, and because it is manually propelled, it does not require laser light scanning. Also, a laser scanning device must reject most of its input as extraneous graphics, whereas a wound scanning device sees very little extraneous input. However, since portable scanning devices are battery powered, it is important that their power consumption be low. Further, although the scanning speed of the laser beam is known, the speed due to hand movement varies over a wide range and exhibits large accelerations. To eliminate printing tolerances due to ink spreading that occurs when printing symbols on surfaces,
The traditional method of reading UPC symbols consists of using delta distance to decipher the symbol. Ink spreading is a major printing error that must be considered when decoding bar coded data. A delta distance measurement is the distance between the leading and trailing edges of a combination of consecutive bars and blanks in a bar coded symbol. This delta distance measurement is used to obtain a selected delta distance ratio for symbol decoding. If the ink spread is uniform within the recorded symbol, these decoding ratios are
It does not change due to the spread of ink. There are 16 combinations of this ratio, and 20 are required if forward and backward orders are taken into account. Therefore, further measurements must be made to resolve the ambiguity that arises when only unambiguous delta distance ratios can be used for decoding purposes. Such alternative measurements do not provide the advantages with respect to printing tolerances that delta distance measurements have. Early prior art decoding methods required the decoding circuitry to discriminate between large numbers of ratios and very close ratios, thus requiring very high resolution for decoding purposes. However, such resolution is not easy to obtain, especially in hand-held wond scanners or portable decoding devices. Recently, another decryption method has been developed in which the number of ratios to be identified is reduced to four, but the distance between them is relatively large so that they can be easily distinguished from each other. In this type of decoding device, the selection of the ratio is such that the numerator and denominator have one bar and one blank, so ink spread is not a factor in the resulting ratio. Since in the UPC symbol each coded digit has a forward order and a backward order, there are still combinations that create ambiguities when relying on these prior art methods. These digits cannot be unambiguously deciphered solely on the basis of the above delta distance ratios, and therefore printing tolerance problems cannot be resolved without using some other means or ratios. Nor can all of the coded digits be deciphered without ambiguity. Conventional methods employing the above decoding techniques based on delta distance measurements generally use a high speed laser light scanning device and associated circuitry to calculate the decoding ratio. In hand-operated wand scanning methods for reading UPC symbols and similar symbols, the wide range of velocities is the result of moving the wand over the recorded symbol, so these conventional techniques for delta distance ratio calculations The circuit is impractical. Some prior art techniques using hand-held wand scanning devices for reading bar coded data use logarithmic time base circuits; however, these circuits
It is not practical for calculating delta distance ratios for UPC symbol decoding. The present invention now provides an improved system for reading and decoding high-density linear bar codes of the UPC symbol type, which can be advantageously used in hand-operated wand scanning devices and can also be used in other decoding devices.
To provide a reliable, low cost and low power consumption method. The present invention provides a reliable reading and decoding method that is highly tolerant of wondrous accelerations, poorly printed symbols, and symbols with wide printing tolerances, yet can resolve ambiguities with simple techniques.
The present invention not only recognizes but utilizes the minimal graphical rejection required by hand-held wands, as opposed to high-speed laser beam scanning devices. One invention of this application measures the width of consecutive bars and blank spaces within a bar coded symbol on the fly and stores it in random access storage so that advanced post-processing techniques can be used after the measurements are completed. It has an advantage over conventional methods and devices in that the measured values are stored. Additionally, the present invention facilitates some calculations using logarithmization techniques that allow for a wide dynamic range without having to multiply or divide large numbers. The present invention utilizes encoding information from the central or standard part of the UPC type coding symbol while selecting an appropriate secondary decoding ratio to resolve ambiguities that are dependent on the primary decoding ratio. This allows the ink spread to be easily corrected and thus ambiguities to be reliably resolved. The invention will now be described in detail with reference to the accompanying drawings. In particular, the concepts of the present invention will be detailed as applied to reading and decoding high density linear bar codes of the Universal Product Code (UPC) type used in the grocery industry. In order to facilitate understanding of the present invention, the basic characteristics of the UPC standard symbol shown in FIGS. 1A and 1B will first be explained. The basic characteristics of the UPC standard symbol shown include a series of light and dark parallel bars with light margins on each side. As shown in Figure 1A, any 10-character code will contain 30 dark bars and 29 light bars. The overall shape of the symbol is a rectangle. As best understood by examining Figure 1B, each letter or number in the code is
It is represented by the book's dark bars and two bright blank spaces. Each coded character is made up of seven modules. One module is one black stick or one
May consist of any of the book's light sticks;
(Alternatively, it may consist of successive combinations of one, two, three or four dark or light bars.) Thus, in Figure 1B, the left side of the character structure represents the number 6; Here, seven modules are represented by two bars and two blank spaces. From this, it can be seen that the bar on the right consists of four consecutive dark modules. The right side of the character structure is similarly encoded in the form of two bars and two blank spaces, representing the decimal value 0. Especially considering Figure 1A, we also see that
It can be seen that the two characters encoded with the UPC symbol have an independent relationship with each other. this
The UPC symbol is designed to be read or printed in the usual way. The UPC symbol is "wandable" in the sense that the symbol can be scanned and read using a simple hand-held device. A fixed position scanning device was developed to scan this symbol in all directions. In particular, the symbol can be automatically read by a scanning device, such as a laser light scanning device, when passed past the scanning device in any direction. In order for the symbol to be read by a hand-held device or a device having omnidirectional characteristics, some relative movement must occur between the recorded symbol and the scanning device. The UPC symbol also includes a standard pattern consisting of a group of coding modules with a known width ratio between successive coding modules, as shown in Figure 1A. It has come to have a As used in the UPC standard symbol, the standard pattern illustrated in Figure 1A includes three such patterns with a 1:1 width ratio, each of which has a left guard bar line. pattern, a right guard bar pattern, and a high center bar pattern.
The right and left guard patterns are limited to represent a dark-bright-dark pattern, i.e. 101, and the high center bar pattern becomes representative of an information 01010 pattern, i.e. a light bar-dark bar-bright bar pattern. ing. A central bar pattern separates the forward and reverse digits, which are encoded with the UPC symbol. To the left of the center bar pattern are five characters representing "forward" coded characters, and to the right are five characters coded "reverse". The forward or left-hand character and the reverse or right-hand character represent the fact that the right-hand character is the binary complement of the left-hand character. For example, for the decimal value 0, the encoding symbol on the left is
0001101, and the coded symbol on the right side is 1110010. Let the characters on the left have odd parity and the characters on the right have even parity. The left-hand text consists of three or five dark modules, always beginning with a bright blank space. The right-hand character consists of two or four dark modules and always starts with a dark module. As shown in FIG. 1A, the standard symbol also includes a module check character encoded between the right guard bar pattern and the last module of the reverse character field. In addition to the right side of the left-hand guard pattern and the right-hand guard bar pattern, other information is recorded, which can be used to determine the number of characters encoded with the symbol and having a preselected width. Can identify the system. When reading any bar-encoded symbol, the symbol is not only read as recorded;
It is customary to detect surrounding recorded information in the vicinity of the bar coded pattern of the desired information as to whether it is associated with the symbol. For example, with laser scanning techniques, a large portion of extraneous figures must be rejected, whereas with hand-held wand scanning devices, very few extraneous figures are detected. As already mentioned and shown in FIG. 1B, the UPC symbol consists of two bars and two blank spaces to represent one character. The order of bars and blanks may be blank-bar-blank-bar or may be reversed depending on the scanning direction and the field of recorded characters. In order to simplify the study of the present invention, the order is A, B,
C, D, in which case blanks and bars are identified based on FIG. 1C for both forward and reverse directions. In other words, each character appears in the order A, B, C, and D, regardless of whether it is recorded in the forward or backward direction. In this order, the two first-order decoding ratios used here are defined as:
That is, (A+B/C+D) and (A+D/B+C). Examining Figure 1C, each of these first-order reading ratios contains one bar and one blank space in both the numerator and denominator, so even if ink spread occurs, there is no difference in the ratio itself. It has no effect. These primary decoding ratios are fractions 2/5, 3/4,
4/3 and 5/2. One pair of these linear ratios is used to decode a single character. However, the following must be kept in mind. In other words, in the delta distance method using the above decoding ratio,
In either case, ambiguities arise and some characters cannot be unambiguously decoded solely on the basis of primary decoding ratios. That's what it means. In the present invention, we resolve this ambiguity by using selection and simplified quadratic decoding ratios, while also correcting for any printing tolerances to improve the
This makes the deciphering of alphabetic symbols based on ratios very reliable. The second-order ratio used in the present invention is determined by the value obtained by expanding two first-order ratios. As shown in Figure 1C, when two primary ratios produce a ratio of 3/4, 4/3 or 4/3, 3/4, the secondary ratio is the value of the primary ratio. shall be allocated on the basis of Determining the secondary decoding ratio If the selected primary ratio is 3/4, the ratio of the widths of modules A and B (A/B) is checked; if the primary ratio is 4/3, The quadratic ratio (C/D) of the widths of modules C and D is checked. Examine these quadratic ratios to determine whether they are 2/1 or 1/2. In any case, for numbers that do not cause ambiguity, such as 1, 7, 2, 8,
These numbers are decoded based on two primary decoding ratios and a selected secondary decoding ratio. All other numbers can be unambiguously decoded based on first-order decoding ratios only. The improved decoding method of the present invention is implemented by a microprocessor. The width of each bar and each blank space of the scanned symbol is measured and stored in a counter driven by a linear time base. These measured distances or widths are then transferred to a storage device after each measurement. Successive measurements are stored in successive storage locations of the storage device until all measurements are completed. As mentioned above, when scanning the recorded symbols there are detectable extraneous figures on the label with the UPC symbol, and this extraneous data is also stored in the storage device along with the required information. Thus, some of the information is scanned before the symbol itself is scanned, and some information is detected after the symbol is stored in the storage device. No decoding occurs while the label is being scanned. This procedure requires that a "label" with the required coded information be assigned a storage location in the storage device, or "framed", before it can be decoded. As mentioned above, the UPC standard symbol has a standard center bar pattern, with characters encoded to the left and right of this center bar pattern. The encoded data can be located within the storage device by examining the data in the storage device and thereby locating the stored data representing the standard center bar pattern. Once the location of this center bar pattern is specified, it can be used in accordance with the present invention to identify the storage locations stored in the coded characters to the left and right of the pattern. In other words, once the storage location of the center bar pattern is specified,
The storage locations of modules A, B, C and D are known for each letter of the symbol. Once these modules are located in storage,
The sum of the modules can be calculated to determine the values of the two primary decoding ratios. Once the primary decoding ratio is calculated, the secondary decoding ratio can be calculated, and as a result, the symbol can be decoded. An ambiguity exists if the two primary ratios are any combination of 3/4 and 4/3, and this ambiguity is therefore resolved using the secondary decoding ratio. See table.

[Table] D 2

[Table] Since the quadratic ratios A/B and C/D do not have delta distance characteristics, their values range over a wide range. Although these do not overlap according to the symbol designation, other errors or out-of-tolerance symbols may cause reading errors. The UPC standard symbol includes a guard bar and a center bar with a one-to-one ratio. If the logarithm of the ratio of the center bar to the center blank is not zero, the ratio will not be 1:1 and the degree of deviation will be expressed by the magnitude of the logarithm. This will provide information regarding directionality and the magnitude of printing tolerances, which information can be used to correct the quadratic ratio measurements. For example, if the ratio of center bar to center blank space is measured as 2 to 1, it can be inferred that the symbol is overprinted. In that case, nominally 2 to 1
The A/B ratio of would be measured to be approximately 4 to 1. If the measured A/B ratio was divided by the measured center bar to center blank ratio, a nominal value of 2 to 1 would be calculated. Use logarithms to simplify calculations. Therefore,
Division is performed using log subtraction. A/B
(or C/D) ratio is a blank to bar ratio, then the logarithm of the center bar to center blank ratio is added to the A/B ratio and multiplied. When reading from left to right, the correction factor is added logarithmically to the measured width of the first half of the symbol and conversely subtracted from the right-hand character. If the reading is reversed, the first half will be the right half. Under conditions of ink spreading, a 1:1 ratio does not change proportionally to 2:1. However, modifications are possible if the nominal ratios are only 1:2 and 2:1. If other ratios appear, such as the ratio of intermediate bars to intermediate bar gaps, the accuracy of the correction will be relatively low. Now, keeping in mind the above structure and the general concept for symbol decoding described above, the general mechanism of the decoding device shown in the block diagram of FIG. 1 will be explained.
A UPC symbol is recorded or printed on the label 10. The optical wand 11 passes over the symbol,
Bars and blank spaces representing data in the form of UPC symbols are detected and signaled. The optical wand 11 generates symbols representing the displacement from the white bar to the white blank and vice versa. Such optical wands 11 are well known to those skilled in the art, and such wand reading systems are described in U.S. Pat.
This is exemplified by the description in No. 3925639. Now, these wond signals, ie, raw data, are sent to a linear time-to-digital converter 12. converter 1
2 the time required for the wand 11 to traverse each bar and each blank space is measured, and these width measurements are stored in read/write storage 13. The width measurements are then stored in sequence in a memory in the memory 13. Conveniently, read/write storage 13 is random access storage (RAM). Once the displacement detection by the wand 11 is completed, control of the system is transferred from the linear time-to-digital converter 12 to the central rod locator 14. The locator 14 searches the storage device 13 to locate the pattern for the center bar of the UPC symbol, that is, the center bar pattern.
Find a ratio that satisfies 01010. For this purpose, the locator 14 uses a ratio calculator 15. Ratio calculator 15 is also used by character decoder 16. The ratio calculator 15, when under the control of the center bar locator 14, receives from the storage device 13 modules A,
Receive linear values of width measurements for B, C, and D, add selected pairs of these values, and calculate a preselected ratio to determine whether a valid center bar pattern exists. decide. The center bar locator 14 is
If it is confirmed that both of the pair of preselected ratios are 1, the position of the central bar pattern in the storage device is determined. Assuming that the center bar pattern is pattern 01010, and that these can be considered to be A, B, C, D and E modules when read from left to right, the effective center bar is the memory device. To determine whether the central bar ratio is (A+B/C+D) and (B+C
/D+E) and inspect it. Both ratios are 1
If so, the center bar pattern is correctly placed in the storage device 13. In testing both of the above ratios, if correct results are obtained, it is confirmed that the center bar pattern starts from a blank space and is correctly positioned in this device. As a result of calculation, if any of the above ratios does not become 1, the matching 2
The same process needs to be repeated until one continuous ratio is detected. The following points must be noted when calculating the position of the center bar pattern. This means that because the delta distance is used, it is not possible to determine the correct location of the center bar pattern if the ink spread is uniform. If the desired ratio is not detected after a preselected number of trials, the reading must be stopped. Once the valid center bar condition is met, record or calculate the printing tolerance correction factor. Printing tolerance correction calculations are performed based on the sensed width of the module including the center bar pattern. The magnitude of the modification is obtained by measuring the ratio of standard bar to guard void. Therefore, to determine the value of the printing tolerance correction, the ratio (A+C/B+D) can be calculated. In this ratio, (A+C) represents the width of the bar and (B+D) represents the width of the blank area, so if the center bar pattern is correctly positioned, this ratio equals 1. This is the basic logic of the symbol prior to the recording or printing of the pattern. Once this printing tolerance correction value has been calculated, the storage address of the storage device 13 is set to the starting position of the first character to be decoded. At this point in the decoding process, control has passed to the character decoder 16. The character decoder 16 uses the ratio calculator 15 to
Its function is to decipher the pattern of modules on the left and right sides of the central bar pattern. If a valid center bar pattern is recognized, the character is read by a series of ratios calculated by ratio calculator 15 under control of character decoder 16. The character decoder 16 then reads the storage device 1 starting from the storage device specified by the center bar locator 14.
3. Step through the series of 12 characters and center bar patterns stored in step 3. Once each of the primary ratios has been calculated, the secondary ratios are calculated to resolve any ambiguities that may arise. Prior to calculating the secondary decoding ratio, the printing tolerance correction factor and storage device 13
and the data representing the width of the module stored in , and then use this modified value to
Calculate the next decoding ratio. If any one of the 12 characters cannot be correctly decoded, control is returned to the center bar locator 14. Once all characters have been correctly decoded by the character decoder 16, control is transferred from the decoder 16 to the validity checking circuit 17. Since the validation circuit 17 itself is not new, it will not be described in detail. It is included solely for read cycle repeat loop integrity purposes. For this reason, each character includes a reading direction indicator. All reading direction indicators must be consistent for the decoded information to be valid. When the direction of reading by the won 11 is reverse, the order of the characters is also reversed and the test digits are inspected. If any of these tests fail, control of the system must be returned to the center bar locator 14 to determine the correct location of the center bar pattern within the storage device 13. This process determines whether a valid reading is achieved or not.
Alternatively, the process is repeated until all possible positions of valid symbols stored in the memory 13 have been exhausted. With the above general mechanism of the decoding system in mind, the linear time-to-digital converter 12 shown in FIG. 2 will now be described in detail. This converter 12 is
It consists of circuit elements that receive the raw wound data information from the wound 11 and circuit elements that process the data so that it can be stored in the storage device 13.
To this end, AND circuit 20 is provided with one input terminal connected to receive wond raw data information at its input. The other input of the circuit 20 is connected to a start/stop toggle 21 .
The output circuit of the AND circuit 20 is connected to a differentiating circuit 22, and the latter is connected to a rectifier 23. Toggle TM has a set input S connected directly to the output of rectifier 23. The reset output of Toggle TM is shown as _M1 . The set output section of the toggle TM is connected to an AND circuit 24.
The output section of the AND circuit 24 sequentially outputs the output signals M ₂ , M ₃
and _M4 . Real-time measurements are obtained by providing a count rate oscillator 26. The oscillator 26 generates clock pulses to an AND circuit 27 at a preselected rate. Another input to the AND circuit 27 is the reset output _M1 of the toggle TM. A clock pulse from oscillator 26 is also applied as a second input to AND circuit 24 to control the operation of sequencer 25. The AND circuit 27 is an 8-bit counter 28
has an output connected to an incremental input of.
Eight-bit counter 28 can be preset by a signal applied to its preset input, which signal is shown in FIG. 2 as signal _M3 from sequencer 25. The 8-bit counter 28 also has an overflow output, shown as a carry output, and this output signal is applied as its one input to an OR circuit 29. The count output of 8-bit counter 28 is coupled as one input to AND circuit 30. Another input of the AND circuit 30 is the signal from the sequencer 25.
It is _M2 . The output of the AND circuit 30 is the memory device 13
The data input terminal of the storage device is enabled and the data is simultaneously transferred to consecutive storage locations of the storage device. Storage device 13 is under the control of address counter and register 31. Address counter and register 31 has an increment input, represented by signal M ₃ generated from sequencer 25 and coupled to the register, by which the increment of successive addresses of storage device 13 is performed. It can be carried out. Address counter and register 31
also has an overflow output terminal, shown as "carry", and this output signal is
It is applied as a second input to the OR circuit 29. A start signal is applied to the reset terminal of address counter 31 to initiate the read cycle.
OR circuit 29 generates an overflow signal, indicated by signal _M5 , if any of its inputs receives an overflow signal from counter 28 or register 31. The signal _M4 from the sequencer 25 is applied to the reset terminal R of the toggle TM to reset the toggle upon completion of the module reading of the UPC symbol. The "start" signal is also applied to the reset terminal of toggle 21,
AND gate 20 is enabled. Now, taking the above structure into consideration will facilitate understanding of the operating principle of the linear time-to-digital converter 12. This element 12 is equipped with a switch which initiates the read operation and which resets the toggle 21 or "T" toggle 21 and the address counter and register 3.
This is a switch for applying a "start" signal to the reset terminal of No. 1. On the other hand, the device 12
For example, as disclosed in U.S. Pat. No. 3,925,639, the label 10 has a wand 11 disposed on the white surface or end surface of the label 10.
can be designed to automatically react to certain conditions that indicate that an attempt should be made to read the data. When the wand 11 moves over the label 10, the wand 11 detects the displacement between the dark bar and the white blank area. These displacements, as they occur, are transferred through an AND gate 20, differentiated in a differentiator 22, rectified in a rectifier 23, and the resulting signal is applied to the "set" terminal of the toggle TM. . The toggle TM is adapted to be "set" for each displacement between the sensed modules. The clock pulses generated by oscillator 26 are accumulated in 8-bit counter 28 at the time of the reset of toggle TM caused by applying signal _M1 to AND gate 27. By setting the toggle TM, the sequencer 25 is enabled, and therefore the 8-bit counter 2
Application of clock pulses to 8 is prohibited. This inhibition of the application of clock pulses to the counter 28 is mediated by a change in the state of the signal _M1 when the toggle TM is "set". At this point,
The information accumulated in the counter 28 is transferred to the storage device 13, the address of the storage device for storing the next information is incremented between displacements, and the toggle TM is then reset. The sequencer 25 is arranged to sequentially transmit these functions to the signals M ₂ , M ₃ ,
and M ₄ in this order. The sequential operations that occur after setting the ToggleTM are as follows. Sequential signal function M ₂ Stores the count of counter 28 in storage device 13 . The memory address of the _M3 register 31 is incremented and the count of the counter 28 is preset. M ₄ Reset toggle TM and accumulate count for next sensed module or next bar or blank. Signal M ₁ is considered a "stop" signal, while the signal
_M5 transfers control of the system to the center bar locator 14. The storage device 13 preferably has a capacity for accumulating the results of 64 measurements and the ward 11 has a label 1.
It is better to be able to cross any unrelated figures that may be related to the UPC symbol on 0. The count interval of the counter 28 is approximately 40 microseconds, and the count capacity is 8 bits or 8 counts.
It is of course understandable that a finite amount of time is required for the wand 11 to perform its function after a certain displacement point has been detected. For this purpose, counter 28 is preset to a value representing the count that will be accumulated during this processing time. In one configuration, presetting the minimum count to 7 provided sufficient time to store post-displacement cumulative measurements in storage 13.
Presetting the counter 28 to a count of 7 with signal _M3 at the beginning of each measurement maintains the accuracy of the decoding system. Counter 28 or storage address counter 3
1 overflows and generates an output signal, the overflow is the output signal of the OR gate 29.
Represented by _M5 . If the signal M ₅ occurs, it can be inferred that the end of the label 10 has already been reached, so that the signal M ₅ causes the system to control the converter 1.
2 to the center bar locator 14. Now, FIG. 3, FIG. 3A, and FIG. 3B will be explained. Here, UPC in storage device 13
A block circuit diagram for locating and identifying the center bar pattern of a symbol will now be described in detail. Basically, the center bar locator 14 includes a center bar ratio detector 14D, a retry counter 14C, a center bar locator sequencer 14S, and a storage address controller 14M. The center bar locator device 14 is adapted to work in conjunction with a ratio calculator 15 which calculates the required ratios processed by the locator 14. During the time interval during which the center bar pattern is stored, the ratio calculator 15 is under the control of the locator device 14. The principle of operation of the ratio calculator 15 will be explained more fully later. The central bar locator/sequencer 14S, indicated by the dashed line block in FIG. 3, includes P ₁ , P ₂ ,
Contains the sequence for generating the signals denoted P ₃ etc. and S ₁ , S ₂ , S ₃ etc. The sequencer 14S has a function such that when it is preset to a particular state, all other positions of the sequencer 14S are reset. These preset positions are designated P ₁ , S ₁ , P ₉ etc. in FIG. 3 at the bottom of the sequencer 14S. The sequencer 14S is advanced by its input circuitry each time it receives a sequential signal at its step input. The sequencer 14S is controlled and advanced in a sequential manner in response to clock pulses generated by a clock pulse generator 26. A clock pulse from oscillator 26 is applied to AND circuit 35 at one of its inputs. The other input to AND circuit 35 comes from the "SET" output of toggle 35T. When toggle 35T is in its "set" state, applying a clock pulse to the input of AND circuit 35 produces an output signal that is applied to the sequencer's step input, thereby advancing the sequencer to the next consecutive position. That is, when toggle 35T is in the set state, the sequencer advances sequentially in response to each clock pulse that AND gate 35 receives. The set input of toggle 35T is controlled by OR gate circuit 36. This OR circuit 36
receives an overflow signal M ₅ from the linear time-to-digital converter 12 in addition to the "retry" signal. Recall that control of the system is transferred from linear time-to-digital converter 12 to center bar locator 14 in response to signal _M5 . The output of the OR circuit 36 is connected to the set input of the toggle 35T as well as to the _P1 preset position of the sequencer. The storage address controller 14M of the center bar locator 14 uses the address counters and registers 31 of the storage device 13 used in the linear time-to-digital converter 12, ie, in a time-sharing manner. The register 31 is shown as a separate circuit element in FIG. 3 to simplify the description of the invention. The storage address register 31 has a ``preset'' input for setting the desired address in the register 31, and an ``incrementing'' input for sequentially incrementing the address stored in the register. There is. It is also possible to preset an address in register 31, such as a "starting" address placed in device 37, to achieve the objectives of the invention. This "start" address is stored in the register 31 so that reading of the storage device can begin at that address location. For this purpose, the value of the desired address stored in device 37 is transmitted to signal M ₅ (from device 12).
At the same time, in addition to the AND circuit 38, a sequential search for the center bar pattern position is started in the storage device.
The output of the AND circuit 38 is connected to one input of the OR circuit 39. Another input of the OR circuit 39 is connected to the output of an AND circuit 40 which receives the signal P ₁₃ from the sequencer and the output signal from the storage address register 31. The output signal of OR circuit 39 is applied to control circuitry, which is a preset next start address controller 41. The output of the control device 41 is applied to the AND circuit 42 together with the signal _P1 from the sequencer 14S. The output signal of the AND circuit 42 is applied to the OR circuit 43 as one input signal. The output signal of the OR circuit 43 is applied to the preset input of the address register 31 so that the address entered into the device 37 can be stored in the register 31. Control circuitry is shown to the right of storage address register 31 and serves to subtract a preselected value from the address to which address register 31 is set. The network includes a memory 44 for storing the number to be subtracted from the address stored in address register 31. As shown in FIG. 3, the subtractive number N is represented by the number 26 stored in device 44. The output of the storage device 44 is sent to the AND circuit 45 together with the signal _P13 from the sequencer 14S. AND
The output signal of circuit 45 is applied to one input of OR circuit 46. Another input of the OR circuit 46 is a control circuit having a storage element 47 for storing another number (for example, the number 2 shown in FIG. 3) to be subtracted from the address stored in the register 31. They are sent with the net as their companion. The output signal of element 47 is applied to one input of AND circuit 48. An OR circuit 49 is provided,
The output signal is applied to the other input of AND circuit 48. The input signals to the OR circuit 49 are sent from the sequencer 14S, and are shown as two signals P ₆ and P ₁₁ in the figure. AND circuit 48
The output signal is applied to the OR circuit 46 as another input signal. The output of OR circuit 46 is sent to the preset input of subtraction register 50.
In that case, the subtraction register 50 stores the number stored in device 44 or device 47 for further processing. The output signal of the subtraction register 50 is sent to the subtracter 51
sent to. The other input of subtractor 51 comes from the output of address register 31.
The address value sent from address register 31 is stored in subtraction register 50, where it is subtracted and applied to and stored in difference register 52.
The signal generated by the difference register 52 is sent to the AND circuit 53
sent to. Another input signal to the AND circuit 53 is sent from the OR circuit 54. OR circuit 54
The two signals applied to the center bar locator sequencer 14S come from the center bar locator sequencer 14S and are shown as two signals _P8 and _P15 . The output signal of AND circuit 53 is applied as another input signal to OR circuit 43, thereby presetting the address for storage address register 31. That is, 29-26=3. Incremental input of storage address register 31 is OR
It is controlled by the output signal of circuit 55. The OR
Circuit 55 is center bar locator sequencer 1
It receives signals S ₁ , S ₂ and S ₃ from the address register 31 and sequentially increments the address stored in the address register 31. The center bar ratio detector 14D is shown on the left side of FIG. Ratio detector 14D receives a signal from ratio calculator 15 representing the logarithm of the desired ratio. This logarithmic signal is applied to and stored in the log ratio register 56. The log ratio value is used to address a conversion table stored in read-only storage. The storage device is shown in the figure as device 57, as well as ROM E. The device 57 stores table data and
Convert calculated log ratios to numbers in the decimal or other convenient number system. In order to facilitate understanding of the invention, it will be assumed here that the conversion is performed in a decimal number system.
Thus, the log ratio signal applied to ROM E, device 57, and representing the logarithm of the ratio, is converted into a numerical signal representing the calculated ratio. The numerical signal representing the ratio read from the read-only storage device ROM E57 is sent to a pair of AND circuits 58,59. The output signal of the device 57 is sent to an AND circuit 59
is applied to the AND circuit 58 as its one input via the NOT circuit 60, while it is applied directly to the AND circuit 58 in an unmodified state. Another input signal to each of these two AND circuits 58, 59 is the center bar locator sequencer 14.
The same signal P ₂ sent from S. two ANDs
The output signals of circuits 58 and 59 are both sent to a cycle counter 61 for controlling it. However, although the output signal of the AND circuit 58 is sent directly to the increment input section of the cycle counter 61, the output signal of the AND circuit 59 is once applied as an input to the OR circuit 62.
The output of OR circuit 62 is applied directly to the reset input of cycle counter 61. Another input signal applied to the OR circuit 62 is the AND circuit 63
It is sent from. AND circuit 63 is controlled via an OR circuit 64 responsive to signals P ₁ and P ₈ generated from sequencer 14S. Furthermore,
An odd/even bit signal generated from the retry counter device 14C is applied as another input to the AND circuit 63. The output of cycle counter 61 is sent to cycle counter decoding circuitry 65 where the decimal value of counter 61's count is signaled. The output signal of network 65 is applied as one input to AND circuit 66 along with signal P ₄ from sequencer 14S. The output signal of the AND circuit 66 is output to the sequencer 1 as shown in the figure.
Applied directly to the _P9 preset position of 4S. The retry counter 14C includes a retry binary counter 67. The binary counter 67 counts the number of attempts the system has made to locate the center bar pattern in memory and store the results. Retry counter 67 is reset at its input R by signal M ₅ from converter 12. The increment input of counter 67 is responsive to signal _P3 from sequencer 14S. The odd-even signal of the counter 67 is sent to the AND gate 63,
Cycle counter 61 is controlled as described above. The count stored in the retry counter 67 is sent directly to a retry decoding circuit 68 to decode the output signal generated by the counter 67 in response to the counting of the counter 67. Circuit 68 is also adapted to respond to signal _P5 from sequencer 14S. After 10 attempts have been made to locate the center bar pattern within storage 13, circuit 68
That is, the configuration and definition are such that reading is terminated after the 10th trial. Therefore circuit 6
The output signal from 8 is shown as such.
A choice must be made regarding this value, since even a valid symbol may exceed the capacity of the storage device. When considering the search for the position of the standard center bar pattern in the storage device 13, first assume the following. That is, when reading the label 10, no displacement occurs before the guard bar given to the UPC symbol on the label 10, and therefore the central bar pattern is stored in the storage device 13 at addresses 27-31. Assume that The first storage location φ is always 1
The measurements of one module, which is a book bar, are included, so all even addresses in the storage 13 store bar measurements. This storage configuration is illustrated in Figure 3A, in which the center bar pattern encoding modules are designated A, B, C, and D with decoding ratios determining valid center bar patterns. ing. As such, the search for the location of the center bar pattern in storage 13 always begins at address 27. It is of course understandable that in the unlikely event that irrelevant data is stored in the storage device 13 during scanning, the storage location will shift and the initial attempt to specify the location of the pattern will therefore result in failure. be. This starting address is device 37
and examines the data stored at address locations 27-31 to determine if the known center bar width ratio is stored data that can clearly specify the location of the center bar pattern in storage device 13. Decide whether you are satisfied or not. The two ratios (A+B/C+D) and (B+
C/D+E) are both 1, a valid bar pattern is specified. Table Sequence Function P ₁ Loads the storage address register 31 with the starting address. Load the S ₁ A register and increment the storage address register 31. Load the S ₂ B register and increment the storage address register 31. Load the S ₃ C register and increment the storage address register 31. S ₄ Load into D register. S ₅ Select the contents of the A register and press B
Add to register contents. Load S ₆ log(A+B) into E register. S ₇ Select the contents of the C register and press D.
Add to register contents. Load S ₈ log(C+D) into F register. S ₉ Subtract the contents of the F register from the contents of the E register. If the result of P ₂ log is 1, increment the cycle counter 61 and
If not, the counter 61 is reset. Increment _P3 retry counter 67. When P ₄ cycle counter 61 signals 2, jump to sequence P ₉ . When the _P5 retry counter 67 signals 10, the reading is aborted. P ₆ Load the number 2 into the subtraction register 50. P ₇ Subtract the contents of the subtraction register 50 from the contents of the storage address register 31. Load the contents of _P8 difference register 52 into storage address register 31. If retry counter 67 signals an "even" bit, cycle counter 61 is reset. Skip to step _S1 . P ₉ Select the contents of the B register and press C.
Add to register contents. Store P ₁₀ log(B+C) in E register. P ₁₁ Select the contents of the D register and press E.
Add to register contents. Load the number 2 into the subtraction register 50. Load P ₁₂ log(D+E) into register F. The contents of the subtraction register 50 are subtracted from the contents of the storage address register 31. P ₁₃ Subtract the contents of the F register from the contents of the E register. Load the subtraction register 50 with the number 26. _P14 Load into modified value register 100 (see Figure 5). The contents of the subtraction register 50 are subtracted from the contents of the storage address register 31. Store the contents of _P15 difference register 52 in storage address register 31. Jump to decoder 16. The table shows a step-by-step sequence for locating the center bar pattern within the storage device, which will now be described. The basic sequence of events that occurs when searching for the correct address of stored center bar data in storage 13 is that, starting at storage address 27, the values for modules A, B, C and D are first determined at step _P1 . It is read from the storage device 13. The first ratio (A+B/C+D) is calculated by the ratio calculator 15 and further processed by the central bar ratio detector 14D. This ratio is 1
If so, cycle counter 61 is incremented at time _P2 . At time P ₃ ,
A retry counter 67 is incremented to record the completion of the decryption attempt. In the next sequence, a new set of data stored in memory 13 starting from address 28 and ending at address 31, representing modules A, B, C and D, is read from memory 13. This is achieved by first modifying the starting address sequentially via steps P ₆ to P ₈ , then retrieving the data and then calculating the ratio via steps P ₉ to P ₁₃ . Ru.

[Table] In the table, the table is associated with the storage address of register 31, and at the same time during the order of operations detailed in the table when the central bar pattern is located in storage on the first try. The counts of cycle counter 61 and retry counter 67 are shown. For this new data, the ratio (B+C/D+E) is calculated and if this ratio is determined to be 1, then
Cycle counter 61 is incremented. On top of that,
Retry counter 67 is again incremented. In this case, cycle counter 61 should signal a count of two and decoding circuitry 65 should signal a decimal value of two. This condition is confirmed at time P ₄ ,
The resulting signal from AND gate 66 presets the sequencer position to _P9 . At time _P9 , the recording or printing correction factors are calculated, as will be described later. The above discussion of the operation of center bar locator 14 assumes that only two attempts are required to locate the center bar pattern to the first indicated address location 27-31. If a ratio of 1 is not calculated in either of the two trials of specifying the center bar position, the search must be repeated until two consecutive ratios with a value of 1 are detected. During this trial, the retry counter 67 is incremented for each trial, and when the number of trials reaches 10,
As shown in FIG. 3, a valid label is deemed to exceed the capacity of storage device 13 and the read is therefore aborted. Furthermore, cycle counter 61 does not count up to 2, and retry counter 67 does not count to ``even'' for AND gate 63.
It should be noted that when generating an output signal, cycle counter 61 is reset by the signal from OR circuit 62 at time _P8 . This confirms the following: That is, two consecutive ratios of value 1 always start from a blank space, and this is one necessary condition to satisfy the condition for detecting a valid center bar pattern. At this point, the detailed step-by-step operation of the center bar locator 14, which specifies the storage location of the center bar information shown in the table, includes steps S ₁ - _{S 9 and} P ₉ - P ₁₃ . It is shown. It should be understood that the steps are processed within the ratio calculator 15. These steps provide information regarding the address locations of the storage device 13 containing modules A, B, C, D and E, as well as information about the log ratio signal applied to the log register 56 of the ratio detector 14D. Calculations are made. Ratio Calculator 1 for these sequential operations
This will be explained together with the operation of step 5. The table shows the cycle counter 61 and retry counter 6 during the center bar location procedure when the center bar pattern is located on the first try.
A count of 7 is recorded. This table corresponds to the detailed operation of the sequencer shown in the table. As we follow the step-by-step sequence shown in the table, we see that there is a correspondence between the operations shown in the table and the values shown in the table. It can be seen that in order P ₆ of the table, the subtraction register 50 is loaded with the decimal value 2 from the device 47. This value is subtracted from the address of the storage location where the last information is obtained. Following the steps to obtain the values of A, B, C, and D from storage 13, it will be recalled that at sequence time _S4 , the final storage location queried was number 30. Therefore, if the number 2 is subtracted from memory location 30 at ordinal time P ₈ , the memory address identified is 28;
This corresponds to what is shown in the table.
Address 28 then identifies the starting address of the second cycle of the first attempt to identify the center bar pattern, information obtained from addresses 28-31. This information is obtained via the sequence of table steps P ₉ to P ₁₂ corresponding to the table sequence P ₈ , S ₁ -S ₃ . After this interval, in sequence P ₁₃ , the number 26 stored in device 44 is fed into subtraction register 50 . order
In P ₁₄ , the number 26 is subtracted from the storage address to which the storage device is pointing, i.e. 29, so that the order
At P ₁₄ , the new storage address stored in register 31 will point to storage location 3. Please refer to the table. Of course, this number 3 is the storage location where the first character module A to be decoded is located. After this storage location is identified in sequence P ₁₅ , control of the system is transferred to the character decoder 16, as can be seen from the table. The character decoder 16 begins decoding the stored data from memory location 3;
Move forward step by step. The contents of the center bar ratio read-only storage device 57 are
Note that this is as shown in Figure B. The logarithm of the ratio stored in this ROM E is
Since it can take values of minus 1, 0, or plus 1, any quantization error can be taken into account. This ROM E is used to convert the log ratio signal applied to it into a decimal number of ratios. As defined and recorded in FIG. 3A, the resulting ratio output signal is:
Represents a ratio of 1 or a ratio other than 1. To complete the understanding of the search for the center bar pattern in the memory, the tables and are inserted, whereby the center bar pattern is specified in the memory 13 on the first try. The storage address of the register 31 and the counts of the cycle counter 61 and retry counter 67 are associated with each other.

[Table] The table describes the value of the register 31 of the first retry after decoding failure. This new trial begins at address location 29 in memory and follows the same order as shown in the table.
At the beginning of the "retry" procedure, counters 61 and 67 both count two. At time P ₁ , a signal is applied to AND gate 63 resulting in
The cycle counter is reset to zero. By this _P1 signal, the output signal of the OR gate 64 is
An even bit (2) signal is applied to AND gate 63 and from retry counter 67. In this case, the order of operations begins with data retrieved from address locations 29-32 based on sequential operations of the table. Cycle counter 61 counts up to one during the first search cycle at time P ₂ and again during the second cycle at the same time P ₂ . At time P ₃ during the first cycle, retry counter 67 increments to three and again increments to four at time P ₃ during the second cycle. As mentioned above, at time P ₁₂ , address register 31
2 is subtracted from the position, and after time P ₁₃ , 26 is subtracted. Therefore, the address register 31
P ₁₄ indicates address 5 to start the next decryption attempt.

[Table] ｜
P8 29 0 2
The table shows the address value of the register 31 when, during the first trial, a center bar pattern that is not 1 occurs in the first cycle and a pattern that is 1 in the second cycle. Therefore, this table is
With the exceptions mentioned above, it corresponds to the table.
Cycle counter 61 only increments to one at time _P2 during the second cycle of the new trial. Referring to the table, it can be seen that if retry counter 67 generates an even bit signal to AND gate 63, cycle counter 61 is reset at time _P8 . Since this is true under these conditions, counter 61 is reset to zero at time _P8 . Since no valid center bar pattern has yet been specified in storage, the order is S ₁
start from. Please refer to the table. The search for a valid center bar pattern now begins at storage address 29 and the retry counter is two.

[Table] ｜
P8 29 0 2
The table shows the same values as the address register values in the table, except that the cycle relationships are reversed. That is, the table shows that the number of attempts to locate a valid center bar pattern is 1 in the first cycle and 1 in the second cycle.
The address position specification is shown in cases where this is not the case. During these assumed conditions, cycle counter 61 counts only during the first cycle at time _P2 . As shown in the table, during the second cycle at time _P2 , the cycle counter is reset to zero. After this attempt is complete, the search is repeated from memory location 29 and the retry counter records two. Now, explaining the table again, at time P ₄ ,
It will be seen that if a valid center bar pattern has already been assigned to the storage location, the sequence will skip to time _P9 . At time P ₉ , the calculation of the recording or printing tolerance correction factor begins. At time P ₄ , the output signal from the AND gate 66 is
, the sequencer 14S is preset to _P9 . The reason for the generation of this signal is that the decoding circuitry 65 receives the "2" signal read out at time _P4 .
This is to apply it to the AND gate 66. Then, at time _P9 , a correction calculation begins based on the width measurement stored at the address location indicated in step _S1 based on the location designation that yields a valid search. If this happens on the first try, e.g.
Address position is 27. This calculation continues for modules B, C and D during steps _P10 to _P12 . This calculation is performed by a ratio calculator 15, which will be explained next. The resulting character modification value is stored in a modification value register 100 of the character decoder 16 for use during the decoding procedure described below. Now, with reference to FIG. 4, the general mechanism of the ratio calculator 15 will be described. Ratio calculator 15 is used in conjunction with both center bar locator 14 and character decoder 16. The ratio calculator 15 operates based on data read from the storage device 13 and performs the required ratio calculations to either the center bar locator 14 or the character decoder 1.
6 to produce an output signal that is the logarithm of the desired ratio used in either. The data read from storage 13 and processed by ratio calculator 15 are width measurements representing the measured values for modules A, B, C and D of a character. This A, B, C and D
Data is read from storage 13 and stored in separate storage registers A, B, C and D within ratio calculator 15. Data modules stored in registers are identified in the form of data read from the registers. Therefore, the A module measurements are stored in the A register and the B module measurements are stored in the B register. Similarly, C module measurements are stored in the C register and D module measurements are stored in the D register. Each of registers A, B, C and D has an input controlled by a separate AND circuit, shown as AND circuits 70, 71, 72 and 73, respectively, which are shown on the left in FIG. or arranged in order on the right. Data from the storage device 13 is sent to AND circuits 70 to 7 in a parallel circuit relationship.
3. That is, these AND
applied as one input to each of the circuits.
AND circuit 70 is activated by signal _S1 from sequencer 14S to store the A module measurement value. Similarly, signals S ₂ , S ₃ and S ₄ activate each AND gate 71, 72 and 73, respectively. The output circuits of registers AD are controlled by one or two AND gates. The output circuit of the A register is one two-input AND gate 74.
The output circuit of the B register is controlled by two input type AND gates 75 and 76. Similarly, the output of the C register is one AND gate 77
The D register is controlled by a pair of AND gates 7
8 and 79. Connect to A register
The second input of AND gate 74 is the output signal generated from OR gate 80. OR gate 80 is responsive to input signals _S5 , _S11 , _S17A and _P9 . These signals generate an output signal from OR circuit 80 for reading the data stored in the A register and further processed by ratio calculator 15. Similarly, the OR gate 81 works with the B register.
One of the input signals of AND gate 75 is controlled.
OR gate 81 is responsive to signals S ₁₃ , S ₁₉ B and P ₁₁ in sequence. The output signal of the B register is applied as one input to both AND gates 75 and 76 in a parallel circuit relationship. Another input to AND gate 76 is signal _S5 from sequencer 14S. OR gate 82 provides one of its input signals to AND gate 77 to cause it to read information from the C register. OR gate 82 is responsive to sequencer signals S ₇ , S ₁₃ , S _17C and P ₉ . Sequencer signal S ₇ controls the data transfer of the D register via AND gate 78 . D register data is applied to both AND gates 78 and 79 in parallel. The OR circuit 83 is AND
The input signal at the second input of gate 79 is controlled.
OR gate 83 receives sequencer signals S ₁₁ and S _19D
and in response to P ₁₁ . Since it takes many tries to decipher the recorded symbol, register A,
The data stored in B, C, and D (as well as the storage device 13) is designed not to be read destructively. The raw measurement data stored in these registers is read only for the purpose of processing within the ratio calculator 15. Registers A, B, C and D
The data stored in is applied to a two-input binary adder 84. One of the inputs of the adder 84 is
The other is controlled by OR gate 85, and the other is controlled by OR gate 86.
controlled by OR gate 85 is AND circuit 7
4, 75 and 78.
OR gate 86 includes AND circuits 76, 77 and 79
responds to the output signal of The output signal of summer 84 represents the linear sum of the width measurements of the two modules applied thereto, ie the sum of the signals applied thereto by OR gates 85 and 86. Using the output signal of adder 84, in FIG.
Addresses a table stored in read-only storage designated ROM A. The data stored in ROM A is a conversion table,
The linear sum signal is converted into a binary coded decimal number, that is, the sum signal is converted into a binary coded decimal number which is the logarithm value of the sum signal. A method for selecting the base of the logarithm is disclosed in commonly assigned United States patent application Ser. No. 638,056 (application no. 147,050). The content of the above-mentioned application is incorporated herein by reference, and the disclosure of the above-mentioned US patent application Ser. No. 638,056 may be relied upon as necessary for understanding the present invention.
Now, the above sum signal is used as an address signal for reading ROM A. The signal read from ROM A is stored in a logarithm register 87 which is connected to receive the binary encoded output signal from ROM A. Register 87 has an 8-bit capacity and is shown in FIG. 4 as consisting of a left half and a right half each having 4 bits. The right half of the register is binary bit 2 ⁰
2 to ³ , while the left half stores binary bits 2 to ⁴ .
2 Memorize ⁷ .

TABLE Recall that the minimum linear value selected for counter 28 was seven. Therefore, values below 7 need not be taken into account in the table. The logarithmic values shown in the table start arbitrarily from zero, with the value 15
After reaching , it starts again from zero. When calculating the correction factor, the ratio A/B or C/D is
It is calculated in the form (A+φ)/B+φ and (C+φ)/D+φ. The output signals of the two parts of logarithm register 87 are:
It is controlled for further processing via a pair of AND gates 88 and 89. The output signal on the left side of register 87 is applied as one input to AND gate 88, and the output signal on the right side is applied as one input to AND gate 89. 4 consisting of input signals applied to AND gates 88 and 89.
The two bits represent the decimal value recorded in the table. OR gate 90 is another one of AND gate 88
control two inputs. This gate 90 has S ₆ ,
Responsive to signals from sequencer 14S, illustrated as S ₈ , S ₁₂ , S ₁₄ , S ₁₈ and S ₂₀ . Similarly, OR gate 91 controls another input of AND gate 89. This gate 91 is responsive to sequencer signals _P10 and _P12 . AND gate 88
and 89 output signals are connected to these
Controlled by OR gate 92. OR gate 9
The output signal of 2 is a pair of parallel circuits.
Added to AND gates 93 and 94. Another input of AND gate 93 is controlled by OR circuit 95. This OR circuit 95 is responsive to sequencer signals S ₆ , S ₁₂ , S ₁₈ and P ₁₀ . Another input of AND circuit 94 is controlled by OR gate 96. The OR gate 96 receives signals S ₈ ,
Respond to S ₁₄ , S ₂₀ and P ₁₂ . AND circuits 93 and 94 are independent logarithm registers E and F, respectively.
control the data that is fed into Registers E and F are each 4-bit registers that store the value of the logarithm of the sum of measured widths, such as the logarithm of the sum A+B. Registers E and F each have their own output circuits and are connected so that their contents can be transferred to subtracter 97. Subtractor 97 performs a logarithmic subtraction of the two sums stored in registers E and F, i.e. subtracts the value in register F from the value in register E, and then produces an output signal which is the logarithm of the desired ratio signal. Occur. Subtractor 97 is enabled under the control of OR gate 98. This OR gate 98 is responsive to sequencer signals S ₉ , S ₁₅ , S ₂₁ and P ₁₃ . subtractor 97
The output signal of is applied to either the center bar locator 14 or the character decoder 16 depending on the use of the ratio calculator 15. Now, with the above structure of the ratio calculator 15 in mind, its operating principle will be further explained. The information from the storage device 13 representing the modules A, B, C and D is stored in the sequential signals S ₁ , S ₂ ,
In response to the occurrence of S ₃ and S ₄ are loaded into the corresponding module registers. One, A, B, C and D
Once all of the data has been fed into the registers, the A and B data are added to adder 84 to form a linear sum of their measured widths, since the sequential operations are performed sequentially as shown in the table. is obtained. This result is obtained when the sequential signal S ₅
is generated and applied to the OR gate 80 in the form of its one input, and the A register is read out via the AND gate 74 and the OR gate 85. This same sequence signal S ₅ transfers the B register data through AND gate 76 and OR gate 86 to adder 84 . The linear sum obtained from adder 84 addresses ROM A to read the logarithm value of the sum. This sum is stored in register 87. As shown in the table, this data is transferred to the E register upon the occurrence of the sequence signal _S6 . That is, signal S ₆ becomes the input signal of AND gate 88, activates it, and transfers the data to register 87.
OR gate 92 and AND gate 93 from the left half of
The data is transferred to the E register via the . AND gate 93 is responsive to the output signal of OR gate 92 as well as the output signal of OR gate 95;
Note that generates an output signal in response to receiving signal S ₆ at its input. The next sequence shown in the table is the generation of signal S ₇ , which is connected to OR gate 82 and AND gate 7.
7 and OR gate 86 to add "C" data to adder 84. At the same time, the signal S ₇ is also D
Data is transferred from the D register to another input of adder 84 via AND circuit 78 and OR circuit 86. Similarly, this data is sent from adder 84 to
It is transferred to the F register via ROM A and the logarithm register 87. The sequence signal _S8 is the logarithm of the sum of C and D data, as shown in the table.
Transfer via AND gate 88, OR gate 92 and AND gate 94. This result occurs because
A signal _S8 is applied to OR gates 90 and 96,
This is to activate AND gates 88 and 94. In this way, at time S ₉ within the order operation,
Subtractor 97 is activated to subtract the data in the F register from the data in the E register to generate the required log ratio signal. 5, the general mechanism of character decoder 16 will now be described. The character decoder 16 is adapted to work in conjunction with the ratio calculator 15, as described above, from which the calculated logarithmic ratio is stored in the logarithmic ratio register 101 for the decoder 16. Receive the output signal. It will now be recalled that during the operation of the ratio calculator 15 in locating the center bar pattern, a printing error correction value was also calculated and transferred to the character decoder. Assume that this value is stored in the modified value register 100 for the decoder 16. Modified value register 100
stores the modified value added therein under the control of AND gate 102. This AND gate controls the input of register 100 and at the same time
Its input is connected to the output of log ratio register 101 as well as signal P ₁₄ from sequencer 14S of FIG. Table Order Function S ₁ Store the A register and increment the storage address of register 31. Store the S ₂ B register and increment the storage address of register 31. Store the S ₃ C register and increment the storage address of register 31. Store the S ₄ D register and increment the storage address of register 31. S ₅ Selects the contents of the A register and adds this contents to the contents of the B register in adder 84. Sequence function S ₆ Store log(A+B) in E register. S ₇ Selects the contents of the C register and adds this contents to the contents of the D register in adder 84. Store S ₈ log(C+D) in F register. _S9 adder 97 subtracts the contents of the F register from the contents of the E register. Translate S ₁₀ log (A+B/C+D) in ROM B and store the result in R ₁ register. S ₁₁ Selects the contents of the A register and adds it to the contents of the D register in adder 84. Store S ₁₂ log(A+D) in E register. S ₁₃ Select the contents of the B register and transfer it to the C
Add to register contents. Store S ₁₄ log(B+C) in F register. _S15 subtractor 97 subtracts the contents of the F register from the contents of the E register. Translate S ₁₆ log A+B/C+D in ROM B and store the result in R ₂ register. Sequence Function S ₁₇ If the R ₁ register is 1, select the contents of the A register (Figure 4); if the R ₁ register is 2, select the contents of the C register (Figure 4). Store the value of S ₁₈ log (A or C) in the E register (Figure 4). If S ₁₉ R ₁ is 1, select the contents of the B register (FIG. 4); if R ₁ is 2, select the contents of the D register (FIG. 4). Store the value of S ₂₀ log (B or D) in the F register. _S21 Subtractor 97 subtracts the contents of the F register from the contents of the E register. Combine the _S22 tolerance correction value with logA/B or C/D in adder 108 or subtracter 112. S ₂₃ Validation element 17 decoded characters
Transfer to. S Increment the ₂₄ character counter 123 and restart the sequence. The table stored in ROM A also includes character modifications due to printing UPC symbols on labels, etc. Therefore, the calculation in the ratio calculator 15 of the correction value is performed after the location of the valid center bar pattern and prior to the decoding of the characters of the symbol. This modified value is stored in register 10 of character decoder 16.
Stored as 0. Calculation of correction values is performed in the present invention by examining a standard pattern with a known one-to-one ratio for bars and blanks. To decode the UPC standard symbol, the standard pattern examined is the center bar pattern width. To obtain the correction value, the actual or printed ratio of the central pattern bars to the blanks can be measured. This ratio is set to minimize the effects of local printing irregularities.
It has been preselected to include two bars and two blank spaces. In the UPC standard symbology, the ratio is defined as two center bars to two center blank spaces. That is, the ratio is A+C/B+D. For nominal symbols,
The value of these ratios is 1. For overprinted symbols or labels, they will be greater than 1, and for underprinted labels, they will be less than 1. In other words, the ratio is defined as the width of two dark bars to the width of two bright bars. known ratio,
That is, since the width of the bar line and the blank space are the same, whenever the termination ratio is other than 1, modules A, B, C
The corrected values must be combined with the stored measured values of and D. The correction calculation in the sequence of events begins with the reading of data for the two center bars from registers A and C at time _P9 . These width measurements are read out with signal _P9 appearing at OR gates 80 and 82 at time _P9 . They are each
It is transferred to the adder 84 via the AND gate 74, the OR gate 85, the AND gate 77, and the OR gate 86. The logarithm of the resulting sum is
It is read from ROM A and stored in register 87. At time _P10 , the contents of register 87 are transferred to the E register. This result occurs because the signal
P ₁₀ is applied to OR gates 91 and 95, and in response, AND gate 89, OR gate 92 and
This is because the AND gate 93 is activated. Similarly, the B and D registers are read at time P ₁₁ during the sequence. These width measurements are applied to adder 84 as a result of signal P ₁₁ being applied to OR gates 81 and 83.
input. At time _P12 , the logarithm of the sum signal is transferred from register 87 to the F register. This occurs because signal P ₁₂ is applied to OR gates 91 and 96. At time P ₁₃ , signal P ₁₃ is applied to OR gate 98 resulting in
The subtracter 97 becomes available for use. The resulting logarithm of the modified signal is stored in a modified value register 100 for the decoder 16 and used during decoding using the quadratic ratio. Now, here, the decoding sequencer 14S shown in FIG. 5 is the same as the sequencer 14S shown in FIG. 3 exclusively for the center bar locator 14, and what is duplicated in FIG. Note that this is merely to simplify the discussion of the operating principle of the decoder 16. The sequencer 1
Those skilled in the art will naturally understand that 4S can be implemented in a time-sharing manner in a decoding system. The output signal of log ratio register 101 is applied to a primary ratio read-only storage, designated ROM B in FIG. This ROM B converts the logarithm of the ratio for the primary ratio generated during the decoding process into the primary ratio 4/
It stores a table that converts into a number representing one of 3, 5/2, 2/5, or 3/4.

[Table] The table shows the relationship between the address of ROM B and the output data representing the above-mentioned linear ratio. In other words, when the output data of ROM B is "2", the primary ratio is 4/3, and when the output data is "1"
Note that for , the linear ratio is 3/4. Output data generated from ROM B is input to a pair of AND circuits 103 and 104 in a parallel circuit relationship. The AND circuit 103 functions to transfer the output data of ROM B through the circuit in response to the signal _S10 from the sequencer 14S.
Therefore, the output of the AND circuit 103 sends this data to the _R1 register for storing the first linear ratio. Similarly, the AND circuit 104 outputs the ROM B output data under the control of the signal _S16 .
Transfer to _R2 register. The _R2 register stores the second primary decoding ratio. The output circuits of AND circuits 103 and 104 are also connected to OR circuit 105 and serve to control decoding circuit 106. Decoder circuit 106 indicates an error if the primary ratio data signal from ROM B is 4, as shown in the table. The output signals of registers R ₁ and R ₂ are binary coded decimal ratios.
Input to ROM C. Specifically, register R ₁
The data output signal of is input to bits b ₂ and b ₃ of ROM C, and the output signal of register R ₂ is input to bit b ₀ of ROM C.
and b input to ₁ bit.

【table】

[Table] The contents of ROM C are as shown in the table. This table associates two linear and quadratic ratios, decodes the required characters in the form of decoded decimal values shown in the data field, and determines whether the data is a forward bit or a backward bit. Identifies whether it is a read bit. For example, the zero φ bit indicates a forward number,
Bit 1 indicates the number in the opposite direction. Forward direction is 1st A
It is used in the sense of scanning from left to right as shown in the figure; the reverse direction refers to scanning from right to left. Both right-hand and left-hand characters are interpreted as "forward" in a left-to-right scan, and "reverse" in a right-to-left scan. The binary coded decimal output of ROM C is input to an AND circuit 107 controlled by a signal _S23 from the sequencer 14S. AND
The output of circuit 107 is a binary coded decimal character with directional bits and is sent to validation circuit 17. As you can easily recall, before calculating the quadratic ratio for character decoding, the modules A, B, and C are
The correction value character must be added or subtracted to the measured width of and D. On the left side of the label 10, correction values are added to the measured data, and on the right side, correction values are subtracted from this data. For this purpose, a binary adder 108 is provided, which performs the task of adding this information to the left character. Operation of adder 108 is controlled by AND gate 109. AND
Gate 109 is the "left" signal and sequencer 1
Adder 108 is activated in response to signal S ₂₂ from 4S. Adder 108 combines the signal from log ratio register 101 and the signal from modified value register 100 and produces a modified module data signal via lead 110 to OR circuit 111. Similarly, for the right half of the UPC symbol, subtractor 11
2 are arranged. Subtractor 112 is enabled by an AND circuit 113 responsive to the "right" signal and the signal S ₂₂ from sequencer 14S. Subtractor 112 combines the data from log ratio register 101 and the data from modified value register 100, ie subtracts the modified signal from the ratio signal. The modified module value signal appears on conductor 114 and is applied to OR circuit 111 as its second input. The output signal of the OR circuit 111 is applied to address the secondary ratio ROM D.

[Table] The contents of the quadratic ratio ROM D are shown in Table XI.
The output signal of ROM D determines whether the ratio A/B or C/D is 2/1 or 1/2 to resolve the ambiguity. The output of ROM D is represented in the form of b ₀ and b ₁ outputs. If the b ₀ output of ROM D is 1, the ratio is 2/1, and if the b ₀ output is zero, the ratio is 1/2.
It is. The other output signals are the b ₁ signals, which all have a value of 2 and represent decoding errors. Table XI
Please refer to ROM D's _b1 output is AND circuit 1
15 as its one input.
The second input of AND circuit 115 is constituted by the output signal from element 116A, and is configured by the output signal from element 116A.
16A is also described as having R ₂ =1 or 2. The input signal for element 116A comes from the output of the _R2 register. The b ₀ output signal of ROM D is
Applied to the _b4 bit of ROMC. To resolve any ambiguity, there are two requirements, depending on whether the first linear ratio, i.e. the ratio stored in the _R1 register, is 3/4 or 4/3. One of the quadratic ratios needs to be selected. Therefore, the output of the R ₁ register is coupled to a pair of decoding registers 11 that store the R ₁ value for decoding.
6 and 117. If the decoding register 116 signals that the R ₁ register is 1, then the primary ratio is 3/4 and the selected secondary ratio is A/B. The decoding register 117
If the R ₁ register signals 2, the primary ratio is 4/3 and the selection ratio is C/D. 1st C
Please refer to the figure. Decoding registers 116 and 11
Each of the 7 output circuits is applied as an input signal to the OR gate 118. The output of OR gate 118 is applied to AND circuit 115 as its third input. For this reason,
If R ₁ is 2 or 1, R ₂ is 2 or 1, and a b ₁ signal of value 2 appears at AND circuit 115, an error signal is generated from the circuit 115. The output signal of each of decoding registers 116 and 117 is input to a respective pair of AND circuits 119 and 120, and AND circuits 121 and 122, respectively, in parallel circuit relationship. AND circuit 11
9 responds to the signal S ₁₇ and R ₁ decoding signal
Generates the output signal shown as S ₁₇ A. This output signal is sent to a ratio calculator 15. Similarly,
Another input of the AND circuit 120 is the input signal S ₁₉
output signal to the ratio calculator 15 in response to
Generate S ₁₉ B. AND circuits 121 and 122
are each responsive to the output signal of decoding register 117 in parallel circuit relationship. AND circuit 121 also generates output signal S ₁₇ C in response to sequencer signal S ₁₇ . Similarly, AND circuit 122 generates signal S ₁₉ D which is transferred to ratio calculator 15 in response to signal S ₁₉ . The character decoder 16 typically has six left (0-
5) Since we are decoding both the left and right sides of the UPC symbol in order across the letters, the center bar pattern will begin at the time of letter 6 and will therefore be decoded. In order to prevent this central pattern from being decoded, the storage address is advanced by five positions. This causes decoding to start from the first character on the right. For this reason,
A character counter 123 is provided, and the counter 123 is configured to detect whether the character is a signal from the sequencer or not.
Count the characters as they are sequentially decoded in response to each _S24 . Counter 123 sends an output signal to decoding register 124 indicating that six characters have been decoded. This device 124 is also named Character Count=6 Decipher. Similarly, another register 125 is responsive to the twelfth count of counter 123 to indicate that the symbol has been completely decoded. Decode register 124 generates signal CH ₆ to reset toggle element 126 to the "right"
generate a signal. The output of decoding register 125 is input to the reset terminal of toggle 21. The toggle 21 has a set terminal connected in response to a signal _P15 from the center bar sequencer 14S of FIG. Toggle 21 sends a signal to AND circuit 35 when set. signal
_P15 is also applied to reset the character counter 123 as well as to set the toggle. When set, toggle 126 causes AND circuit 10
Send "left" signal to 9. Signal P ₁₅ is also OR circuit 1
27, in which case it resets the decoding sequencer 14S (FIG. 5). Sequencer 14S, like the previously mentioned sequencer,
It is controlled by an AND circuit 35 which applies a clock pulse to the sequencer step input in response to the "set" state of toggle 21. OR circuit 127 also receives an input signal from AND circuit 128 and functions to reset the sequencer. AND circuit 128 is responsive to signal CH ₆ from decoding register 124 and signal S ₅ from sequencer 14S. The output of the circuit 128 is also OR
Applied to circuit 129 to generate signal _M3 for incrementing the storage address. For this purpose, the OR circuit 129 also provides sequential signals S ₁ , S ₂ , S ₃ for incrementing the storage addresses of the other four locations.
and S ₄ . Now, with the above structure of character decoder 16 in mind, step-by-step operation can be explained. This ordering operation will be explained in conjunction with tables. Recall that first, a correction value was calculated to correct the measured width of the module during the center bar positioning sequence. Thus, at time P ₁₄ of the positioning sequence, the AND gate 102 for the decoder 16 is activated and the logarithm of the tolerance correction character is transferred from register 101 to the correction value register prior to the start of the actual character decoding operation. 1
Transferred to 00. At time P ₁₅ , control of the system is transferred from the center bar locator 14 to the character decoder 16.
Since it has been moved to , the character deciphering of the UPC symbol begins. In this regard, please refer to the table. Here, we would like you to understand the logic for modifying the measurement width of a module. For both forward and backward scanning of the UPC symbol, the tolerance correction character or value is added to the measured module width for modules in the left field of the symbol and subtracted from the measured width of the right field. It is becoming more and more common. In a backward scan operation, the modification is made before reversing the backward scanned character. This logic applies when the correction value is calculated from the bar/blank ratio. Because the character decoder 16 is dependent on the ratio calculator 15, some of the operations in decoding are the same as those required for locating the center bar pattern. In this regard, please refer to the table. As such, the initial sequential steps S ₁ to S ₉ are the same as described with respect to the operation of center bar locator 14 and form the required logarithm of the decoding ratio stored in register 101. Therefore, after the occurrence of sequential step _S9 , the first ratio calculation, i.e.
logA+B/C+D is transferred from ratio calculator 15 to decoder 16. This logarithmic signal addresses ROM B,
A numerical output signal is generated representing a linear ratio based on the table. At time _S10 in the sequence, the data read from ROM B is stored in the _R1 register. Similarly, during sequence steps _S11 to _S16 , the ratio calculator 1
5, the second linear ratio is calculated, and the decoder 16
The data is transferred to the register 101 of. This second linear ratio logarithmic signal represents the ratio A+D/B+C. At the end of time _S16 , the data read from ROM B is stored in register _R2 . If the primary decoding ratios both occur and are stored in registers _R1 and _R2 , a decision must be made as to which secondary ratio to use to resolve the ambiguity. Please refer to FIG. 1C. The ratio A/B or C/D is calculated during each decoding operation, whether necessary or not. To this end, the contents of decoding registers 116 and 117 are examined to determine whether the first linear ratio is 3/4 or 4/3. register 116
The data stored in and 117 is based on tables. Now, if the data signal stored in either register 116 or 117 is 4 (i.e., R ₁ or R ₂ is 4), an "error" occurs.
Note that an (ERROR) signal is generated to return control of the system to center bar locator 14. The "error" signal is generated by OR gate 118. The gate 118 is connected to the register 11
6 or “4” stored in 117 is detected and an input signal is sent to AND gate 115. ROM
The b ₁ signal from D is true if it signals "2", as shown in Table XI. If there are no errors at this point, the selection of the correct secondary decoding ratio continues according to sequence step _S17 . If register 116 signals that R ₁ is 1, then the ratio is 3/4 (table) and therefore module A is selected or ratio calculator 1
The A register in 5 is queried. For this purpose, the decoder 16 generates a signal _S17A in response to the sequential step _S17 , reads out the contents of the A register in the ratio calculator 15, and outputs the OR circuit 80, the AND circuit 74,
and the adder 84 of the ratio calculator via the OR circuit 85
Transfer to. If register 117 signals that R ₁ is 2, the ratio is 4/3 (table) and therefore ratio calculator 15 receives signal S ₁₇ C in sequence S ₁₇ and this signal S ₁₇ C is applied to the OR circuit 82
The AND circuit 121 is enabled. This signal causes the data in the C register of the ratio calculator 15 to be read out, and the OR circuit 82, AND circuit 77, and
It is transferred to the adder 84 via the OR circuit 86.
In step S ₁₈ , the measuring module width A or C
The logarithmic signal of is stored in the E register of the calculator 15 according to the advance selection. The same procedure occurs at sequence time _S19 , with either the B or D register being read and data transferred to adder 84, depending on whether _R1 is 1 or 2. In step _S20 , the composite logarithmic signal of module B or D is stored in the F register of ratio calculator 15. At time S ₂₁ , the contents of the F register are subtracted from the contents of the E register to input the logarithm of the ratio signal into register 101 . At time _S22 , the tolerance correction value previously stored in the register 100 is
It is added or subtracted depending on whether left field characters or right field characters are being decoded. If the correction value is added to the measurement width, a logical condition for this addition must be fulfilled. At time P ₁₅ of the center bar position specification order, toggle 12
6 was "set" to produce a "left" signal that was in the true state. This "left" signal is AND gate 10
9 and is applied to adder 1 at the same time as the time S ₂₂ occurs.
08 becomes available for use. Log ratio register 10
The contents of 1 are added to the contents of modified value register 100 so that a modified module width signal is generated on conductor 110 and applied to OR gate 111. If the correction value is to be subtracted from the measured module width, the logical conditions for the subtraction must be fulfilled. Assuming an initial forward scan, after the left field is decoded, the character counter 123
is counted up to 6. This 6 count is decoded by character 6 decoding circuitry 124 and
An output signal representative of the count is generated. This output signal is applied to the reset input of toggle 126 to generate a ``right'' signal that is in a ``true'' state. This "right" signal is sent to AND gate 113, which enables subtracter 112 at the same time as signal _S22 is input. The contents of modified value register 100 are subtracted from log ratio register 101 so that a modified module width signal is generated on conductor 114 and ORed.
It is input to gate 111. If a modified module width signal for either the left or right field appears at the input of OR gate 111, its output signal is the quadratic decoding ratio.
Address ROM D. The signals read from ROM D are according to Table XI. When the quadratic ratio data is read from ROM D, a data signal representing a valid quadratic ratio, 2/1 or 1/2, is sent to bit 4 of ROM C.
(b ₄ ), and at the same time data from the R ₁ and R ₂ registers are also input to ROM C. More precisely, R ₁ data is sent to the b ₂ and b ₃ locations of ROM C, and R ₂ data is sent to its b ₀ and b ₁ locations. The contents of ROM C correspond to the data shown in the table. When relating the data in this table to the circuit operation of the character decoder 16, the quadratic ratio value is applied to the highest address bit, the _b4 location of ROM C, so that the quadratic ratio value for unambiguous decoding is Note that the characters that do not require , appear twice in ROM C. For these characters, 2
The next ratio is an ``irrelevant'' bit, so you can ignore it. The values recorded in the table can be easily translated to represent the decoding of the recorded characters in linear and quadratic ratios. If the primary ratios are decoded to 2/5 and 3/4, the decoded character is defined only by these two primary ratios. That is, the character is clearly table forward direction 4 and table address 1. 2
If the two primary ratios are 3/4 and 3/4, a reverse 7 or a reverse 1 may occur, so the secondary ratio must be checked. Please refer to the table. If the quadratic ratio of A/B is the resultant ratio of 2/1, then the reverse direction 7 is decoded. Similarly, if the quadratic ratio is 1/2, it is obvious that the reverse 1 will be decoded. The table shows the b ₀ to b ₄ address locations and quadratic ratios of ROM C for both forward and reverse scans, 1/
The relationship with 2 and 2/1 is described. The "Address" column of the table represents the decimal bits corresponding to the binary coded bits _b0 to _b4 . Bit b ₀ to b ₃
takes values 0, 1, 2, or 3 as valid linear ratios, as shown in the table. Bit b ₄ is table
As shown in XI, take either 1 or 0 as a valid quadratic ratio. The F/R column of the table determines whether the decoded data character is a forward or backward bit. The φ symbol means forward bit and 1 means backward bit. In sequence _S23 , the addressed memory location of ROM C is inputted with AND gate 107 as a companion and is converted into a binary code with directional bits as described above.
Generates decimal decoded characters. at this point
The output signal of AND gate 107 is transmitted to validation circuit 17. The remaining steps in the decoding procedure are
It is _S24 . Signal S ₂₄ increments character counter 123 to a count of twelve. This twelfth character is decoded in register 125, which generates an "R" output signal. Register 125 is
Signaling that the 12th character has been decoded, toggle 21 is reset and AND gate circuit 35 is activated.
Therefore, the decoder sequencer 14S is disabled. At this point, the character decoding sequence can be restarted. The characters decoded according to the table must match either the forward scan or the backward scan. This fully satisfies the requirements for parity testing as described in the UPC Standard Symbol Processing Instructions. In order to produce a valid decoded output signal, there must be 12 valid characters and a test digit check must be made.
If the read direction indicators do not match and the check digit test fails, control is returned to the center bar locator 14 to attempt searching for another location. In discussing the operating principles of this system, various conditions have been described herein. For example, in the event of an illegal decoding operation, control of the system is returned to the center bar locator 14 which reexamines the memory for a valid center bar pattern. Furthermore, it is stated that the reading is aborted when the retry counter 67 counts up to 10 (5 trials and 2 cycles per trial).
Other conditions for aborting reading are as follows. (1) If any of the data from won 11 is added together, or summed (A+B, C+
D, . . . ), the reading is aborted by 8 bits. (2) If any of the character ratios, i.e. A/B or C/D ratios, are in the area marked "Error" in the table and XI, an abort of the reading is carried out in addition to the conditions indicated in the table. be done. It will be understood by those skilled in the art that the circuit elements described in this specification are well known and available on the general market, and therefore it is possible to configure the present system based on the above description. It is possible.
Elemental functions that are reiterated herein for convenience of explanation can be performed by a single element that can be time-shared by an operating system (OS). The improvements described herein advance the current state of the art in reading and decoding dense linear bar codes of the UPC standard symbology and its derivative symbology types, and readily resolve decoding ambiguities. At the same time, it is highly tolerant to manual acceleration and resistant to recording or printing. The improvements are directly applicable to high speed laser scanning devices as well as portable, battery operated handheld scanning devices.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of a reading device for manually reading UPC symbols or their derivative symbols and for implementing the present invention; Fig. 1A is a diagram showing representative examples of UPC standard symbols; Fig. 1B is a diagram showing a typical example of the character structure of the symbol shown in FIG. 1A,
Figure 1C is a representative example of the character structure of the symbol in Figure 1A, showing the primary and secondary decoding ratios, and Figure 2 is a diagram of the linear time-to-digital converter used in the system of Figure 1. 3 is a schematic block diagram of a center bar locator used in the system of FIG. 1; FIG. 3A is a schematic block diagram of a center bar locator for use in the system of FIG. 1A; A schematic diagram of address locations, FIG. 3B, is a representative example of the information stored in read-only storage E used in the center bar locator of FIG. 3, and FIG. FIG. 5 is a schematic block diagram of the ratio calculator used. FIG. 5 is a schematic block diagram of the character decoder used in the system of FIG. 10... Label, 11... Optical wand, 12...
Linear time/digital converter, 13...RAM, 1
4...Center bar locator, 14D...Center bar ratio detector, 14C...Retry counter, 14M...Storage address controller, 14S...Center bar locator/sequencer, 15...Ratio calculator, 16...Character decoder, 17 ... Validity check circuit, 25 ... Sequencer, 26 ... Count rate oscillator, 28 ... 8-bit counter, 31 ... Address counter and register, 41 ... Next successive start address controller,
50... Subtraction register, 51... Subtractor, 52... Difference register, 56... Log ratio register, 57... ROM
E, 61... Cycle counter, 65... Cycle counter decoding circuitry, 67... Retry binary counter, 68... Retry decoding circuit, 87... Logarithm register, 97... Subtractor.

Claims (1)

Claims: 1. A method of decoding one or more delta distance coded segments recorded on a surface, the coded segments representing each coded character.
4 coding modules A and C of various widths having the same optical properties and coding modules B and D having the same optical properties different from those of the coding modules A and C; The decoding method consists of groups of fixed width in which coding modules are arranged in the order A, B, C, D, and the decoding method is based on and the width ratio (A+
B) calculating /(C+D) and (A+D)/(B+C) to obtain a pair of primary decoding ratios including 2/5, 3/4, 4/3 or 5/2; examining said primary decoding ratio to determine whether it indicates either 3/4 and 4/3 or 4/3 and 3/4, i.e. contains an ambiguity; If the primary decoding ratio test shows ambiguity, the primary decoding ratio (A+B)/(C+D) is 3/
If the primary reading ratio is 4/3, the secondary reading ratio A/B is calculated, and if the reading is 4/3, the secondary reading ratio C/D is calculated. unambiguously decoding the coded segment based only on the primary decoding ratio, or on one of a pair of primary decoding ratios and secondary decoding ratios which, if it includes said ambiguity, creates an ambiguity; A method for decoding a delta distance encoded segment, comprising: 2. A method for decoding one or more delta distance coded segments recorded on a surface, the coded segments representing each coded character;
4 coding modules A and C of various widths having the same optical properties and coding modules B and D having the same optical properties different from those of the coding modules A and C; a group of information of a constant width in which coding modules are arranged in the order A, B, C, D, and a coding module B having mutually identical optical characteristics with a width of a known ratio;
D and the coding modules A, C, and E, each having the same optical properties that are different from those of the coding modules B and D, are A, B, C, D, A group of non-information of a constant width arranged in the order of E, and the decoding method has a known ratio of coding modules A, B,
measuring the width of each coding module of the coding segment comprising C, D, and E; and storing the measured width of each coding module in a storage device as the measurement occurs; The width ratio (A+
B) Coding modules A, B, C, D of known ratios by calculating and testing these ratios until it is found that /(C+D) and (B+C)/(D+E) are equal to 1. , E in the storage device, and the coding modules A, B, C, D, of known ratio in the storage device.
determining the storage location of E and the storage location of related information coding modules A, B, C, D; and determining the storage location of coding modules A, B, C of known ratio according to the ratio (A+C)/(B+D) , D, and E groups based on the measurement width; a step of correcting the measurement width of each coding module according to the calculated recording tolerance correction factor; and showing a delta distance characteristic. The width ratio (A
+B)/(C+D) and (A+D)/(B+C)
and obtain a pair of primary decoding ratios including 2/5, 3/4, 4/3 or 5/2; /4, that is, whether or not there is an ambiguity, the step of checking the primary reading ratio, and if the checking of the primary reading ratio includes an ambiguity, The primary decoding ratio (A+B)/(C+D) is 3/
If the primary reading ratio is 4/3, the secondary reading ratio A/B is calculated, and if the reading is 4/3, the secondary reading ratio C/D is calculated. unambiguously decoding the coded segment based only on the primary decoding ratio, or on one of a pair of primary decoding ratios and secondary decoding ratios which, if it includes said ambiguity, creates an ambiguity; A method for decoding a delta distance encoded segment, comprising: